JPS6214397A - Pattern generator for testing memory element - Google Patents

Abstract

PURPOSE:To generate a pseudo-random data pattern by a simple circuit by feeding the data pattern in synchronization with a basic clock, and feeding a inversing data pattern in a longer cycle than the basic clock and inputting outputs of two fixed memory devices to an unit small block. CONSTITUTION:An initial counter value of an x counter 2 is '0' and the contents of a count signal 3 are '0' and until the count value of the x counter 2 reaches to a maximum value, a carry signal 5 is naturally '0' and a count signal 7 of a Y counter 6 is also '0'. Similarly, when an address given to a fixed memory device 4 reaches to (F, 1), the output 7 of the Y counter 6 goes to '2' and the address is changed to (0, 2). To an inversion fixing memory device 8, the count signal 7 of the Y counter 6 and a carry signal 9 of the Y counter 6 are inputted to be an address. Accordingly, to the inversing fixed memory device 8, the address in a cycle changing F times as long as the cycle by the Y counter 6 is given.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a large-capacity storage device to be tested, such as a magnetic pub tv-
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□Emit virtually random data patterns to be transmitted using a relatively small circuit.
! Information regarding pattern generators for memory element testing that can be used.
1 [Prior Art] The capacity of memory elements has been increasing rapidly in recent years, and in particular, magnetic bubble memory elements have already reached 4, d,...t?
7) (7) 4 (7) Ka, Ka□96, Awa, 3 F, I, [However, when testing a memory element, a means of generating a random data pattern is required, and this - Random data pattern generators that generate data patterns have existed, and there is a problem in that creating the data patterns requires considerable manpower and expense.

[Problem that the invention seeks to solve]

Conventionally, testing has been carried out by dividing a large-capacity storage element under test into several small blocks, but in the present invention, pseudo-random data is repeatedly generated and input into the middle of these small blocks. - The purpose is to generate patterns using a simple circuit that is easy to operate.

[First step to solve the problem] In order to achieve the above object, in the present invention, X and Y counters are operated by the basic clock of the device, and one fixed memory having a capacity equal to the above-mentioned small block is provided. Generates an address for the device and sends out the stored data pattern in synchronization with the sample clock, and also sends out the inversion data pattern stored in another fixed storage device at a cycle longer than the basic clock. Then, the output of these two fixed storage devices is further made into a pseudo-random data pattern which is common to both and is taken out through a dynamic OR circuit and input into the 1- medium small block.

In this way, depending on the storage of the inversion data pattern and the sending cycle, 1! (12 random data patterns can be created with extremely simple circuitry.

[Embodiments of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure,
1 is the input basic clock, 2 is the X counter, 3 is the count signal of the basic clock l by the X counter, 4 is the data
A fixed storage device (with a capacity equal to the small blocks obtained by dividing the large-capacity storage element under test) in which the pattern is stored, and 5 is a digit l that is output every time the count value of the X counter reaches the maximum value.
- count signal, 6 is a Y counter that counts carry signal 5, 7 is a digit by Y counter - count signal of carry signal 5, 8 is a capacity equal to storage device 4 (if they are equal, the circuit configuration is very large) 9 is a fixed storage device for inversion that stores the data pattern for inversion (in principle, they do not necessarily have to be equal), and 9 is output every time the count value of the Y counter reaches the maximum value. A carry signal, 10 is the output of the fixed storage device 4, 11 is the output of the inversion fixed storage device, 12 is the exclusive OR circuit, and 13 is the output of the device of the present invention.

Initially, the count value of X counter 2 is 0 (base clock l
(because nothing is input), the content of count signal 3 is 0. Furthermore, the carry signal 5 is naturally 0 until the count value of the X counter 2 reaches the maximum value of the counter. Therefore, the count signal 7 of the Y counter 6 is also 0. In other words, signals 3 and 7 are stored in fixed storage device 4.
Give address (0, O) to . When one basic clock 1 is input, the address given to the fixed storage device 4 becomes (1, O).
While the address remains 0, only the X address gradually increases, and the address that reaches the maximum value (for example, F becomes (F2O)), a carry signal 5 is output, and the count signal 7 from the Y counter 6 becomes 1. , the address given to the fixed storage device 4 is (0, I). Similarly, when the address given to the fixed storage device 4 reaches (F, 1), the output of the Y counter 6 becomes 2 and the address changes to (0, 2).

On the other hand, the count signal 7 of the Y counter 6 and the carry signal 9 of the Y counter 6 are input to the inversion fixed storage device 8 and become an address. Therefore, in the inversion fixed storage device 8, Y
The counter 6 provides an address that changes at a cycle F times as long. Output 1 of fixed storage device 8 for reversal
When 1 is 0, the output 10 of the fixed storage device 4 passes through the exclusive OR circuit 12 as it is and becomes the device output 13, but when the output 11 of the inversion fixed storage device 8 is 1, the fixed storage device 4 The output [0] of the device 4 is inverted by the exclusive OR circuit 12 and becomes the device output 13. The "inversion" of the fixed storage device 8 for inversion originates from this fact, and does not mean that the stored contents are inverted. In this way, pseudorandom data patterns are generated that are comprised of a large variety of combinations of data patterns.

〔Effect of the invention〕

As explained above, according to the present invention, a pattern for testing a large capacity storage element can be generated using an extremely detailed circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1 Basic clock, 2 X counter, 3-X counter count number 6, 4-Fixed storage device storing data pattern, 5-Carry signal from X counter, 6 X counter that counts fRRb2 by digit , 7 count signal of the X counter, 8 fixed storage device for inversion, 9-carry signal from the X counter, 10 output of fixed storage device 4, 11 output of fixed storage device for inversion, 12-exclusive rectification sum circuit ,
13-Output of the device of the present invention.

Claims (1)

[Claims] Divide the large-capacity storage element under test in the X and Y directions, further divide the divided X and Y directions into small blocks, and use these small blocks as one block of the basic data pattern to generate pseudo-random patterns into these unit blocks.・Data stored in a fixed storage device with a capacity equal to the above small block as a basic data pattern for a device that repeatedly generates and inputs a basic data pattern consisting of data for testing.
The pattern is synchronized with the basic clock of the device, and the inversion data pattern stored in another fixed storage device is sent to a common exclusive OR circuit with a relatively long period different from the basic clock. 1. A pattern generation device for testing a memory element, characterized in that an output obtained by input is used.