JPS62259145A - Generating device for algorithmic pattern - Google Patents

Abstract

PURPOSE:To produce not only regular pattern signals but random pattern signals by providing a selection part which selects the control signal received from an instruction memory or the pattern signal received from an arithmetic part. CONSTITUTION:Microinstructions of a microprogram are successively read out of an instruction memory 10 via a sequence control part 12 and executed by an arithmetic part 20 according to a control signal 16. Thus the pattern signal 22 having a regular change is produced. A switch signal 18 is kept at level 0 and therefore the signal 22 is selected by a multiplexer 24 and outputted outside as an output signal pattern signal 26. In case the microprogram is loaded to the memory 10 for production of the random pattern signal, the control signal 16 serving as a random pattern signal is outputted from the memory 10. In this case, the signal 18 is kept at level 1 and therefore the signal 16 is selected by the multiplexer 24 and sent outside as the signal 26.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram-controlled algorithmic pattern generation device.

[Prior art] In an IC tester that tests LSI memory, etc.,
Microprogram controlled algorithmic pattern generators are commonly used to generate pattern signals such as data and addresses.

This type of algorithmic pattern generator basically generates instructions that store microinstructions.
The structure is such that a pattern signal is generated by calculation in a calculation section in accordance with a control signal output from the memory.

[Problems to be solved] Such an algorithmic pattern generator (
0000)2, (0001)2, (0010)2.
(0011)2. (0100)2. A regular pattern signal such as an address that changes regularly, such as ".phi.", can be efficiently generated using a short microprogram.

- In the case of general RAM inspection, etc., it is sufficient to generate such a regularly changing address signal.

However, 0100)2. (0000)2. (1000)
2. (0010)2. It is difficult to generate random pattern signals such as addresses that change irregularly. Such a random address signal is
This is necessary for testing video RAM, etc.

[Second aspect of the invention Accordingly, it is an object of the present invention to provide a microprogram-controlled algorithmic pattern generator capable of generating not only regular pattern signals but also random pattern signals.

[Means for Solving the Problem] In order to achieve this object, the present invention provides an instruction memory and an arithmetic unit, which are the basic components of a microprogram-controlled algorithmic pattern generator. - A selection section is added that selects either the control signal output from the memory or the pattern signal output from the calculation section according to the switching signal output from the instruction memory and outputs the selected signal to the outside.

[Operation] The control signal output from the intrastructural memory is a specific signal of the microinstruction stored therein. Therefore, by storing a suitable group of microinstructions in the instruction memory, the control signals continuously outputted from the instruction memory can be outputted as random pattern signals to the outside.

Further, if the selection section selects the calculation section side, regular pattern signals can be generated by calculation and output to the outside as in the conventional case.

Further, the selection switching of the selection section is controlled by a microinstruction (a switching signal that is a specific signal thereof). Therefore, microinstructions for generating a random pattern are sequentially loaded from the first device into the instruction memory, and specific signals (control signals) of each microinstruction are outputted to the outside via the selection section in almost real time. By this, a desired random φ pattern signal is continuously generated, and when necessary, a microinstruction for generating a regular pattern is loaded into the instruction memory, and a regular pattern signal is generated. It is possible to dynamically switch between generating a pattern signal and generating a random pattern signal.

[Example 1] An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing one embodiment of the present invention. In this figure, lO is an instruction memory, 12 is a sequence control unit, and each bus 1
4 from a higher-level device (not shown). The instruction memory 10 can also be accessed from the sequence control section 12.

Instruction memory 10 is loaded with microinstructions of a microprogram for generating patterns from the 11th place device. The sequence control unit 12 is a part that controls the execution side of the microprogram (controls the pattern generation sequence).

A microinstruction accessed by the sequence controller 12 has a specific field that is accessed by the sequence controller 12.
Based on this input, control such as branching is performed.

Information in other fields of the microinstruction is provided by the control signal 16.
and is outputted from the instruction memory 10 as a switching signal 18.

Reference numeral 20 denotes an arithmetic unit consisting of an arithmetic and logic operation circuit, registers, etc., to which the control signal 16 is input. This calculation section 20 generates a pattern signal 22 by calculation according to the control signal 16.

24 is a multiplexer as a selection section, into which the pattern signal 22, control signal 16 and switching signal 18 are input. This multiplexer 24 receives the switching signal 18
When the switching signal 18 is at the "0" level, the pattern signal 22 is selected and sent out as the output cover turn signal 26, but when the switching signal 18 is at the "L" level, the control signal 16 is selected and sent out as the output cover turn signal 26. do.

Note that if it is not necessary to input all bits of the control signal 16 to the multiplexer 24, only some of the bits are inputted to the multiplexer 24 manually.

Next, the pattern generation operation will be explained.

First, a case will be described in which a microprogram for generating a regular pattern signal is loaded into the instruction memory IO.

In this case, the bit corresponding to the switching signal 18 of each microinstruction is "0".

The microinstructions of the microprogram are sequentially read out by the sequence control section 12, and operations according to the control signal 16 are executed by the arithmetic section 20 to generate a regularly changing pattern signal 22. Since the switching signal 18 is always held at the "0" level, the pattern signal 22 generated by calculation by the calculation section 20 is selected by the multiplexer 24 and sent out as the output pattern signal 26. This is similar to the operation of the conventional algorithmic φ pattern generation S4.

Next, a case will be described in which a microprogram for generating a random pattern signal is loaded into the instruction memory 10.

In this case, the bit corresponding to the switching signal 18 of each microinstruction is "l".

The microinstructions of the microprogram are sequentially read out by the sequence control unit 12, and a control signal 16 as a random pattern signal is output from the instruction memory 10.

In this case, since the switching signal 18 is always held at the "1" level, the control signal 16 is selected by the multiplexer 24 and sent out as the output cover turn signal 26.

Note that by continuously loading microinstructions such that the switching signal 18 goes to the "0" level from the host device into the instruction memory 10, and immediately outputting them from the instruction number memory 12 and outputting them to the outside through the multiplexer 24, , it is also possible to continuously send out random pattern signals.

Also, in this way, a random pattern signal is continuously generated for a certain period of time, and then a group of microinstructions for generating a regular pattern signal is loaded into the instruction memory, and a regular pattern signal is generated. ,
It is possible to dynamically switch between generating regular pattern signals and generating random pattern signals.

Although one embodiment of the present invention has been described above, the present invention is not limited thereto, and can be implemented with appropriate modifications within the scope of the invention.

[Effects of the Invention] As is clear from the above description, the present invention provides an output from the instruction memory in addition to the instruction memory and the arithmetic unit, which are the basic components of the microprogram-controlled algorithmic φ pattern generator. A selection section is added that selects either the control signal to be outputted or the pattern signal/signal outputted from the calculation section according to the switching signal outputted from the instruction memory and outputs it to the outside. It is possible to realize an algorithmic pattern generation device that can generate not only pattern signals but also random pattern signals, and can dynamically switch and generate regular pattern signals and random pattern signals.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Instruction memory, 12... Sequence control part, 16... Control signal, 18... Switching signal, 20... Arithmetic part, 24... Multiplexer (selection part).

Claims (1)

[Claims] (1) A microprogram-controlled algorithmic pattern generation device, which includes an instruction memory in which microinstructions are stored, and an arithmetic unit that generates a pattern signal by calculation according to a control signal output from the instruction memory; An algorithmic pattern generation device comprising: a selection section that selects either the pattern signal or the control signal and outputs the selected signal to the outside according to a switching signal output from the instruction memory.