JPS5698796A - High-speed memory test system - Google Patents

High-speed memory test system

Info

Publication number
JPS5698796A
JPS5698796A JP17231379A JP17231379A JPS5698796A JP S5698796 A JPS5698796 A JP S5698796A JP 17231379 A JP17231379 A JP 17231379A JP 17231379 A JP17231379 A JP 17231379A JP S5698796 A JPS5698796 A JP S5698796A
Authority
JP
Japan
Prior art keywords
data
register
test
memory
tester
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17231379A
Other languages
Japanese (ja)
Inventor
Takahiko Ogita
Yukio Nozoe
Tsune Morioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17231379A priority Critical patent/JPS5698796A/en
Publication of JPS5698796A publication Critical patent/JPS5698796A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To test a high-speed memory by adding a simple additional circuit to an existing memory tester.
CONSTITUTION: Test address information and test data generated by existing memory tester 10 are used to generate memory test cycles by an additional circuit (part other than tester 10) corresponding to one cycle of a test pattern generated by memory tester 10. The address information from memory tester 10 is written into address registers A and X and through address selecting circuit 1, data of register A or its inverted data, or data of register X or its inverted data is selected and set in address register 9 before being sent as address information to an equipment to be tested. Then, the test data from memory tester 10 is written in register T and selecting circuit 2 selects and sends the data of register T or its inverted data to shift register 3, so that it will be sent to the equipment to be tested.
COPYRIGHT: (C)1981,JPO&Japio
JP17231379A 1979-12-29 1979-12-29 High-speed memory test system Pending JPS5698796A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17231379A JPS5698796A (en) 1979-12-29 1979-12-29 High-speed memory test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17231379A JPS5698796A (en) 1979-12-29 1979-12-29 High-speed memory test system

Publications (1)

Publication Number Publication Date
JPS5698796A true JPS5698796A (en) 1981-08-08

Family

ID=15939593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17231379A Pending JPS5698796A (en) 1979-12-29 1979-12-29 High-speed memory test system

Country Status (1)

Country Link
JP (1) JPS5698796A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455800A (en) * 1987-08-14 1989-03-02 Ibm Memory testing circuit
JPH0574194A (en) * 1991-09-10 1993-03-26 Nec Corp Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455800A (en) * 1987-08-14 1989-03-02 Ibm Memory testing circuit
JPH0574194A (en) * 1991-09-10 1993-03-26 Nec Corp Semiconductor memory device

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