JPH01258130A - Pseudo random number generator - Google Patents

Abstract

PURPOSE:To generate pseudo random number sequence having uniformity with a high level and to perform logical analysis by generating the same pseudo random number repreatedly by enabling the pseudo random number to be generated only by a shift register having a fly-back circuit. CONSTITUTION:When a random number request signal is generated, a shift signal generation circuit 17 generates a shift signal, and changes the output values of shift register circuits (11-13) by shifting via exclusive OR circuits 14 and 15 and an inversion circuit 16. A multiplexer 18 receives the output of 16 bits of the shift register circuits (11-13), and selects eight bits by a bit selection indication signal and outputs them as a random number. In such a way, it is possible to generate the pseudo random number having the uniformity with the high level with simple constitution, and to generate the same pseudo random number repeatedly, and to perform the logical analysis.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an apparatus for performing analysis using a probabilistic model, a simulation, etc., a communication control apparatus for realizing a protocol using random numbers, a cryptographic generation apparatus for using random numbers, and This invention relates to a pseudorandom number generator used in game machines and the like.

(Prior art) Conventionally, this type of pseudo-random number generator
As described in Japanese Patent No. 3435), it is constructed as shown in FIG. In FIG. 3, 31 is a free-running counter that increases the output value at fixed time intervals, 32 is a temporary memory circuit that stores the output value of the free-running counter 31, and 33 is a random number that stores the contents stored in the temporary memory circuit 32. This is an output circuit that outputs.

Next, the operation of the above conventional example will be explained. In FIG. 3, the output value of the free-running counter 31 always increases at regular intervals regardless of external signals. When a random number request signal is generated, the value of the free-running counter 31 at that time is stored in the temporary storage circuit 32.
Store in. The output circuit 33 extracts some or all bits from the multiple-bit numerical value stored in the -time memory circuit 32 and outputs it as a random number.

In this way, even with the above-mentioned conventional pseudo-random number generator, if the random number request signal is generated non-periodically at a time interval sufficiently larger than the time interval at which the free-running counter 31 increases the output value, it is possible to pseudo-generate random numbers. can.

(Problem to be Solved by the Invention) However, in the conventional pseudo-random number generator described above, the random number value is determined by the time at which the random number request signal is generated, and therefore it is impossible to perform logical analysis.

The problem was that it could not be used for applications that required ideal random numbers. Furthermore, it cannot be used when it is necessary to repeatedly generate the same pseudo-random number sequence.The present invention solves these conventional problems, and has a simple configuration that approximates natural random numbers. The object of the present invention is to provide an excellent pseudo-random number generation device that enables logical analysis by generating pseudo-random numbers and making it possible to repeatedly generate the same pseudo-random number sequence.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a code sequence generator consisting of a feedback circuit and a shift register consisting only of an exclusive OR circuit and an inverting circuit or an exclusive OR circuit. and a control circuit that generates a shift signal for the shift register when a random number request occurs, and an arithmetic circuit that outputs some of the plurality of bits output from the shift register with the bit order unchanged or with the bit order changed. It is something that

(Function) The present invention has the following effects due to the above configuration. That is, when a random number request signal is generated, the control circuit outputs a shift signal to the shift register, and the output value of the shift register is changed by shifting the contents of the shift register through a feedback circuit. Since this output value has properties close to uniform random numbers, it is possible to generate pseudo-random numbers with a high degree of uniformity by passing some bits through a circuit that outputs them with the bit order unchanged or with the bit order changed. Furthermore, by setting the initial values of the shift registers to the same value, it is possible to generate the same pseudo-random number sequence.

(Embodiment) FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, reference numerals 11, 12, and 13 are shift register circuits, and a feedback circuit consisting of exclusive OR circuits 14, 15 and an inverting circuit 16 constitutes a non-longest sequence generator. 17 is a shift signal generation circuit, and 18 is a multiplexer.

Next, the operation of the above embodiment will be explained. In the above embodiment, when a random number request signal is generated, the shift signal generation circuit 17 generates a shift signal, and the shift register circuit 11.
The output values of the shift register circuits 11, 12, and 13 are changed by shifting the signals 12 and 13 through the exclusive OR circuits 14 and 15 and the inverting circuit 16. The multiplexer 18 outputs 1 of the shift register circuits 11, 12, 13.
It receives 6 bits, selects 8 bits in response to a bit selection instruction signal, and outputs them as random numbers. As mentioned above, according to this embodiment, 8 of the 16-bit shift register values
Since only bits are output, it has the advantage that the period of the generated pseudorandom number sequence is very long. Furthermore, since the bits to be output and their order can be selected by the bit selection instruction signal, various pseudorandom number sequences can be generated.

FIG. 2 shows the configuration of another embodiment of the present invention.

In FIG. 2, 21, 22, 23, and 24 are shift registers, 25, 26, and 27 are exclusive OR circuits, 28 is a shift signal generation circuit, and 29 is a register. In the embodiment shown in FIG. 2, an m-sequence generator is constructed using a 16-bit shift register and three exclusive OR circuits. Furthermore, since only 8 bits of the output of the 16-bit shift register are used, it has the advantage that all possible values, including O, can be output in a maximum period of 65,535.

In addition, in this embodiment, shift registers 21, 22, 23
The output of ゜24 is sent to the register 29 immediately after the random number request signal is generated.
is stored in the memory. Therefore, since the next output value is stored in the register when the random number request signal is generated, there is an effect that the random number can be output immediately when the random number request signal is generated.

In the above embodiment, an 8-bit random number is generated, but the number of bits of the random number is not particularly limited. Therefore, it is possible to obtain a pseudo-random number generator that outputs pseudo-random numbers with a longer period or a pseudo-random number generator that has a smaller circuit than the above embodiment.

(Effects of the Invention) As is clear from the above examples, the present invention has the following effects.

(1) Since the pseudorandom number sequence is generated only by a shift register having a feedback circuit, the pseudorandom number generation device can be realized by a logic circuit with a simple configuration.

(2) Since physical development that does not have reproducibility or the time interval at which the random number request signal is generated is not used, the same pseudorandom number sequence can be repeatedly generated.

(3) Since the same pseudo-random number sequence can be generated repeatedly,
It is possible to design a device that can perform logical analysis and generate pseudorandom number sequences with properties that suit the purpose.

(4) Since it is constituted by a simple logic circuit, random numbers can be generated immediately when a random number request signal is generated.

[Brief explanation of the drawing]

FIG. 1 is a schematic functional block diagram of a pseudo-random number generator according to an embodiment of the present invention, FIG. 2 is a schematic functional block diagram of a pseudo-random number generator according to another embodiment of the present invention, and FIG. 3 is a schematic functional block diagram of a pseudo-random number generator according to another embodiment of the present invention. FIG. 2 is a schematic functional block diagram of a pseudo-random number generator. 11.12, 13, 21, 22, 23.24... Shift register, 14.15, 25, 26.27... Exclusive OR circuit, 16... Inverting circuit, 17.28...
・Shift signal generation circuit, 18... multiplexer, 2
9...Register, 31...Self-propelled force Ushita, 32...
-Time memory circuit, 33...output circuit. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 I+, +2.13, - Shift register 0 path +4.1
5 ,・,Slander and othersSerishima Rihada 1Takashi Tada 1611An 11th Route 2nd figure

Claims (1)

[Claims] a code sequence generator consisting of a feedback circuit and a shift register constituted only by an exclusive OR circuit and an inversion circuit or an exclusive OR circuit; a control circuit that generates a shift signal for the shift register when a random number request occurs; A pseudo-random number generator comprising: an arithmetic circuit that outputs some of the plurality of bits output by the shift register, either with the bit order unchanged or with the bit order changed.