JP3452706B2 - Test equipment and test method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus and a test method for performing a functional test of an integrated circuit, a functional circuit, etc., and more particularly, a test pattern is generated to test a memory circuit, a sequential circuit, etc. suitable test equipment and used for
Regarding test methods .

[0002]

2. Description of the Related Art As a conventional technique relating to a test apparatus for generating a test pattern to test various circuits, for example,
The technique described in Japanese Patent Laid-Open No. 61-142476 is known.

FIG. 4 is a block diagram showing a schematic structure of a conventional test apparatus of this type. In FIG. 4, 1 is a control circuit, 2 is a test pattern storage memory group, 3 is a dedicated test pattern generator, 4 is a signal selection circuit, 5-1 and 5
-N is a switching circuit, 6-1 and 6-n are drivers / comparators, and 7 is a device under test.

The test apparatus according to the prior art shown in FIG. 4 can test a random logic circuit, a memory circuit, etc. as the device under test 7, and can test the random logic circuit etc. A test pattern storage memory group 2 that stores test patterns to be performed and a dedicated test pattern generator 3 that generates a test pattern to test a memory circuit or the like are configured.

The reason for providing the test pattern storage memory group 2 for a random logic circuit or the like and the dedicated test pattern generator 3 for a memory circuit or the like is that in the case of a logic circuit test, a random test pattern is a signal of the logic circuit under test. Since it is not possible to perform an efficient test even if applied to the terminal, it is necessary to store multiple sets of valid signals created in advance as test patterns to be applied to the terminal in order to perform an efficient test. This is to avoid this because testing of a memory circuit that is effective and requires a large set of test patterns requires a large amount of memory to store those test patterns.

In the illustrated test apparatus, the output terminal of the test pattern storage memory group 2 is usually provided for each signal terminal of the device under test 7, and the output terminal of the dedicated test pattern generator 3 is From the viewpoint of the pattern generation principle of the dedicated test pattern generator 3 and from the viewpoint of cost, it is not provided for each signal terminal of the device under test, and each signal terminal of the device under test 7 is connected to the signal terminal of the device under test 7 from the generated test pattern. The required signal is selected by the signal selection circuit 4.

The testing apparatus shown in the figure outputs the test pattern storage memory group 2 and a dedicated test pattern according to the type of the DUT such as whether the DUT 7 is a logic circuit or a memory circuit. The output selected by the signal selection circuit 4 of the machine 3 is used by switching the switching circuits 5-1 to 5-n. The signals from the switching circuit are used as drivers / comparators 6-1 to 6-n. The signal is applied to the signal terminal of the DUT 7 via the to perform the functional test of the DUT 7.

[0008]

The test apparatus according to the prior art described above has a test pattern signal of a dedicated test pattern generator when the number of signal terminals increases as the degree of integration of the device under test such as an integrated circuit and a memory circuit increases. Hardware required to selectively distribute the signal to each signal terminal of the device under test, and the hardware for switching the test pattern from the test pattern signal storage memory group provided for each signal terminal of the device under test The problem arises that the amount increases.

An object of the present invention is to solve the above-mentioned problems of the prior art, to enable a test pattern to be generated by a simple method, and to reduce the amount of hardware to generate a test pattern. And to provide a test method .

[0010]

SUMMARY OF THE INVENTION The present invention is based on the premise that a value applied to each signal terminal of a device under test or a comparative expected value with respect to an output from each signal terminal has a repetitive regularity. According to the present invention, the object is to simultaneously provide a plurality of address signal terminals of the device under test.
Apply a test pattern to test the DUT.
In the test equipment, the test equipment is
Address signal terminal of each address signal terminal
Provided corresponding to each address signal terminal that applies a turn
A plurality of test pattern generating means,
Each of the pattern generation means holds a test pattern
Memory and the test pattern held in the memory
To any one of the associated address signal terminals
And a control unit for repeatedly outputting the number of times,
Two adjacent address signal terminals of the address signal terminals
A first address signal terminal and a second address signal
Terminals and associated with these address signal terminals
The two test pattern generating means are the first test pattern
As the generating means and the second test pattern generating means,
Output a test pattern to the first signal address terminal.
The first test pattern generating means that applies the force is the first test pattern.
Stored in the first memory of the strike pattern generating means.
After the signal of 0 continues for 2 ⁿ (n is an integer) bits,
The first test pattern in which the signal is continuous for 2 ⁿ bits
And a control unit included in the first test pattern generating means.
To the first address signal terminal a predetermined number of times.
Return and output the test pattern to the second address signal terminal.
The second test pattern generating means for outputting a turn is
A second memory included in the second test pattern generating means
After the signal of 0 held at 2 ^{n + 1} bits continues,
Second test pattern in which the signal is 2 ^{n + 1} consecutive bits
And a control unit included in the second test pattern generating means.
To the second address signal terminal by the
Repeated a predetermined number of times in synchronization with the strike pattern generation means
It is achieved by outputting .

Further, the above-mentioned object is to provide a plurality of objects to be tested.
0 or 1 signal is simultaneously applied to the address signal terminals of
Then, in the test method for performing the test of the DUT,
Address signal terminals of each of the plurality of address signal terminals
On the other hand, a test pattern that combines 0 and 1 signals
Each of the test patterns prepared above is prepared.
Repeatedly any number of times,
Of the plurality of address signal terminals applied to the child
Connect the two address signal terminals that match to the first address signal end.
When used as a child and a second address signal terminal,
A signal of 0 is 2 ⁿ (n is an integer)
The first signal is 2 ⁿ bits in succession after
1 test pattern is prepared, and the first test pattern
Are repeated a predetermined number of times to generate the first address signal terminal.
And a signal of 0 is applied to the second address signal terminal.
1 signal is 2 ^{n + 1} bits with the following but a continuous 2 ^{n + 1} bit
A second test pattern that follows is prepared, and the second test pattern
The test pattern is repeated a predetermined number of times to repeat the first test.
To the second address signal terminal in synchronization with the strike pattern.
It is achieved by applying .

According to the present invention, which has the above-mentioned structure, the test pattern for the memory circuit, the sequential circuit, etc. is utilized repetitively for each signal terminal, and repetitive control is performed for each signal terminal. It is possible to easily generate an arbitrary number of arbitrary test patterns by repeating short test patterns.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION A test apparatus according to the present invention and
An embodiment of the test method will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a test apparatus according to an embodiment of the present invention, FIG. 2 is a flow chart for explaining an operation of generating a test pattern for each signal terminal of a device under test, and FIG. It is a figure which shows the example of the test pattern when a thing is a memory circuit. In FIG. 1, 1-1 to
1-n is a control circuit, 2-1 to 2-n are test pattern storage memories, and other symbols are the same as in the case of FIG.

A test apparatus according to one embodiment of the present invention is
The dedicated test pattern generator 3, the signal selection circuit 4, and the switching circuits 5-1 to 5-n are removed from the configuration of the conventional test apparatus described with reference to FIG.
Each of the control circuits 1-1 to 1-n and the test pattern storage memories 2-1 to 2-n provided independently corresponding to each signal terminal of the device under test 7 such as a sequential circuit is configured. The test pattern generating means is provided.

In the above description, each of the test pattern storage memories 2-1 to 2-n stores a core short test pattern, and the test pattern is controlled by the control circuits 1-1 to 1-n. Then, it is read out and output according to a predetermined repeating rule which differs for each test pattern generating means. Each test pattern generating means is operated in a synchronized cycle and outputs a test pattern, but it is independent so that the respective repetitive control contents may be different.

FIG. 2 shows an example of a flow chart group for generating test patterns for each signal terminal of the device under test by the independent test pattern generating means in FIG. 1 when the device under test is a memory circuit. ing.

In FIG. 2, signals A0 to A3, ...
Is an address signal of the memory circuit under test, and a flow chart for the test pattern generating means corresponding to the signal terminals of these address signals A0 to A3 to generate a test pattern is shown corresponding to the signals A0 to A3. ing. Similarly, the signal W is a write control signal for the memory circuit under test. Although not shown in FIG. 2, when the device under test 7 is a memory circuit, as will be described later, a data input signal sequence and a data output signal sequence indicating an expected value for read data are generated as test patterns. It

As can be seen from FIG. 2, the signal A0 is 2 of "01" stored in the test pattern storage memory.
Repeat the short pattern that is the core of the bit 512 times,
Further, a signal that repeats this twice is applied to the signal terminal of the DUT. Similarly, the signal A1 is "0".
The 011 ″ 4-bit core short pattern is stored in the test pattern storage memory, and this is repeated 256 times, and further, a signal that is repeated 4 times is applied to the DUT.

As described above, each test pattern generating means can generate a test pattern of an arbitrary length by repeatedly generating a short test pattern a specified number of times.

A test apparatus according to one embodiment of the present invention is
As described above, the test pattern generating means corresponding to all the signal terminals of the device under test 7 are provided with the necessary core test pattern and the repeat control, and the processes by the flowchart group shown in FIG. 2 are simultaneously synchronized. The test pattern is applied to all the signal terminals of the device under test 7 via the driver / comparator by starting them. In the example shown in FIG. 2, the number of test patterns in all the flow charts is the same, so the pattern ends at the same time for all signals.

FIG. 3 shows an example of a test pattern when the device under test generated by the test pattern generating means operating according to the flow chart shown in FIG. 2 is a memory circuit. In this figure, the test pattern signals for each signal terminal are listed from left to right in the order of test progress, and the column direction represents the signal value applied to the DUT at the same time.

In FIG. 3, the signal DO is not a signal applied to the memory circuit which is the DUT, but an expected value signal with respect to the output signal from the memory circuit, "X" indicates that no comparison is made, and The "1" and "0" are
The expected value of the output signal read from the memory circuit,
These values are compared with the value of the output signal read from the memory circuit by the driver / comparator. The signal W is a write control signal, and "1" indicates write.
"0" indicates reading. Also, the signal DI is
"1" and "0" when the signal W = 1 is a write input signal, and these values are written in the memory.

In the example shown in FIG. 3, 2048 test patterns are input to the memory circuit as the device under test to perform a functional test of writing and reading, but the number of test patterns is the number of test patterns generated. It can be arbitrarily set by the control circuit of the means, and their pattern shapes can be arbitrarily generated.

In the above-described embodiment of the present invention, the function test of the memory circuit is performed as the device under test, but the present invention is also applicable to other integrated circuits, functional circuits, sequential circuits and the like. The test can be conducted.

As described above, according to the embodiment of the present invention, a short test pattern serving as a core is stored in the test pattern generating means provided corresponding to each signal terminal of the device under test, and this is stored. A long test pattern can be easily generated by performing appropriate repetitive control and outputting.

[0027]

As described above, according to the present invention, it is not necessary to provide a dedicated test pattern generator and a circuit for switching the test pattern generator, and with a small amount of hardware, a desired long test pattern can be easily obtained. Therefore, it is possible to inexpensively provide a test device for performing a functional test or the like of the device under test.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a test apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of generating a test pattern for each signal terminal of a device under test.

FIG. 3 is a diagram showing an example of a test pattern when the device under test is a memory circuit.

FIG. 4 is a block diagram showing a schematic configuration of a test apparatus according to a conventional technique.

[Explanation of symbols]

1, 1-1 to 1-n control circuit 2 Test pattern storage memory group 2-1 to 2-n Test pattern storage memory 3 Dedicated test pattern generator 4 signal selection circuit 5-1 and 5-n switching circuit 6-1, 6-n driver / comparator 7 DUT

─────────────────────────────────────────────────── --Continued from the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01R 31/28 G01R 31/3183 G11C 29/00 657

Claims (2)

(57) [Claims] 1. A test apparatus for testing a device under test by simultaneously applying a test pattern to a plurality of address signal terminals of the device under test, wherein the test device comprises: A plurality of test pattern generating means provided corresponding to each address signal terminal for applying a test pattern to an address signal terminal is provided, and each of the test pattern generating means includes a memory for holding a test pattern and a memory for holding the test pattern. A control unit that repeatedly outputs the held test pattern to the associated one address signal terminal an arbitrary number of times, and sets two adjacent address signal terminals of the plurality of address signal terminals to a first address signal terminal. One address signal terminal and a second address signal terminal, and two address signal terminals associated with these address signal terminals. When the strike pattern generating means is the first test pattern generating means and the second test pattern generating means, the first test pattern generating means for outputting a test pattern to the first signal address terminal is the first test pattern generating means. 0 stored in the first memory of the test pattern generating means
Of the first test pattern in which the 1st signal continues for ²ⁿ bits after the 2nd signal continues for ²ⁿ (n is an integer) bits by the control unit included in the first test pattern generating means. The second test pattern generating means for repeatedly outputting to the address signal terminal a predetermined number of times and outputting the test pattern to the second address signal terminal is held in a second memory included in the second test pattern generating means. Was 0
The second test pattern in which the signal of 1 continues for 2 ^{n + 1} bits after the signal of 2 ^{n + 1} continues for the second test pattern by the control unit included in the second test pattern generating means.
To the address signal terminal of the first test pattern generating means repeatedly and repeatedly outputting a predetermined number of times. 2. A test method for testing a device under test by simultaneously applying signals of 0 or 1 to a plurality of address signal terminals of the device under test, the address signals of each of the plurality of address signal terminals. A test pattern formed by combining signals of 0 and 1 is prepared for each terminal, and the prepared test pattern is repeated an arbitrary number of times to be applied to each of the address signal terminals. When the two adjacent address signal terminals of are the first address signal terminal and the second address signal terminal, a signal of 0 is 2 ⁿ (n
Is an integer), and a first test pattern in which 1 signal is continuously 2 ⁿ bits is prepared, and the first test pattern is repeated a predetermined number of times and applied to the first address signal terminal, A second test pattern in which a 0 signal continues for 2 ^{n + 1} bits and a 1 signal continues for 2 ^{n + 1} bits is prepared for the second address signal terminal. Is repeated a predetermined number of times and is applied to the second address signal terminal in synchronization with the first test pattern.