This repository contains source code for past labs and projects involving FPGA and Verilog based designs
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Updated
Oct 2, 2019 - Verilog
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Connecting FPGA and Arduino using SPI.
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog
CAD for automatically configuring FPGA "Marsohod"
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
A project to implement and test synchronous and asynchronous FIFO using Questasim software.
Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.
A project to implement and test interrupt controller using Questasim software.
Computer Architecture Lab Projects
Simple ipod made using System Verilog and implemented on the De1Soc
This Repo contains some of my Verilog & SystemVerilog Programs.
Demo of a simple 2 layer feed forward perceptron using system verilog (RISC V project)
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