Bus bridges and other odds and ends
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Updated
Jan 12, 2024 - Verilog
Bus bridges and other odds and ends
Repurposing existing HDL tools to help writing better code
Xilinx Virtual Cable Server for Raspberry Pi
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
This repository contains all labs done as a part of the Embedded Logic and Design course.
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
SPI ELF bootloader for Xilinx Microblaze processors
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Bazel rules for Xilinx Vivado
Repository to store all design and testbench files for Senior Design
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
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