Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
-
Updated
Mar 13, 2024 - SystemVerilog
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
16 bit serial multiplier in SystemVerilog
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Pulse Width Modulator programmed through an Advanced Peripheral Bus interface
Quartus II project for a basic interface for writing in a LCD screen using a PS2 keyboard using Altera DE2-70 board
RISC-V five stage pipline CPU
UVM Test bench for a 8-bit ALU
A systemverilog implementation of the data structures: priority queue, queue and stack
Verilog Codes for various Design
An FPGA-based Chess Engine and TPU
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
This testbench is based on SV and UVM Class based to verify Verilog HDL Design
Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.
Multiple DUT with parallel stimulus
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
Add a description, image, and links to the system-verilog topic page so that developers can more easily learn about it.
To associate your repository with the system-verilog topic, visit your repo's landing page and select "manage topics."