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Nidhinchandran47/README.md

Welcome to my GitHub!

Tip

  • 👀  I’m interested in Front-end VLSI Design
  • 🌱  I’m currently learning System Verilog and UVM.
  • 💞️  I’m looking for moments of peace
  • ⚡  Fun Fact : "I'm always there, front and center, for every Liverpool game." #YNWA

🏄🏼‍♀️protfolio

📫  How to reach me? 🔗  My Free-time Crafts (Build with ) 🎯  I'm Currently Buzy with

Caution


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  1. DV200 DV200 Public

    A go-to repository for exploring, learning, and mastering RTL design and verification.

    Verilog 3

  2. HDLbits-Solutions HDLbits-Solutions Public

    The HDL Bits Solutions repository provides answers to the HDL Bits exercises, which are designed for practicing digital hardware design using Verilog HDL. Join us to learn, share, and master digita…

    Verilog 4 2

  3. my_rtl_code my_rtl_code Public

    Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

    Verilog 11 1

  4. MIPS_testbench_generator MIPS_testbench_generator Public

    A MIPS based microprocessor and a python script for automatic generation of testbench corresponding to the input assembly file

    Verilog 1 1