This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Binary adder implementation in the Game of Life written in JavaScript using canvas.

A 4bit Multiplier in VHDL

A simulation where I can connect virtual logic gates and build virtual CIs.

A simple binary calculator based on a system of gates

Digital System Design Lab Codes using Verilog

A simple program that converts a binary number into it's two's complement equivalent. This is used within the SimpleBinaryCalculator repository.

This repository contains HWs and material from the nand to tetris course

Different adders code in VHDL and Comparison

Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/

VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design

All the various adders in Verilog!

A repository for some modules I made while learning Verilog

Skript zur Einführung in die Digitaltechnik

bitwise operation examples

This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.

Assignment 3, Digital Logic Design Lab, Spring 2021, IIT Bombay

CSE-2112 Digital Syatem Design LAb

Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦

Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module