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42 Open 66 Closed
42 Open 66 Closed
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Issues list

about the gen.scala and ifetch
#119 opened Jul 17, 2024 by duanjiulon
5
Nax not trap on store fault
#116 opened Jul 16, 2024 by atkarim
2
The check of the register Rd/Rs is not equal to zero is missing for some compressed instructions
#114 opened Jul 3, 2024 by Bill94l
1
storeFresh unused : trap-store_access_fault
#111 opened Jun 28, 2024 by Bill94l
5
A trap is triggered when the pmpcfg register is read by csrr
#110 opened Jun 28, 2024 by Bill94l
8
Does NaxRiscv update mtval after trap illegal_inst?
#107 opened May 31, 2024 by zhangkanqi
2
about litex and dhrystone
#96 opened Apr 30, 2024 by duanjiulon
37
Error in implementation of SRAW and SRAIW instructions
#95 opened Apr 12, 2024 by Nanotrust
3
Changing Naxriscv instructions - command
#92 opened Apr 10, 2024 by mdmriscv
1
L1/L2 cache and integration with CPU pipeline
#91 opened Apr 8, 2024 by SoCScholar
2
Read a sram that is changed by other host
#90 opened Apr 8, 2024 by zyn810039594
1
Some guidance on better timing
#89 opened Apr 6, 2024 by tristanitschner
3
riscv tests with virtual memory enabled fail
#83 opened Feb 23, 2024 by Bill94l
3
how to run a nax_core with a AXI4 interface
#81 opened Feb 23, 2024 by duanjiulon
13
Default branch direction prediction should be TAKEN (currently NOT TAKEN)
#79 opened Jan 30, 2024 by ronan-lashermes
1
[BUG] CSR write verification error in the Verilator wrapper
#78 opened Jan 26, 2024 by Bill94l
5
Mark framebuffer as non-cacheable
#74 opened Jan 11, 2024 by egorxe
5
NaxRiscv running custom test cases prompts FAILURE ???
#72 opened Jan 3, 2024 by LMiaoH
9
Request for Guidance: Starting with a Minimal Framework
#71 opened Dec 27, 2023 by skylayer
4
Failing to reproduce the NaxRiscv/Debian setup
#69 opened Nov 15, 2023 by newinnovations
25
json2dts issue
#65 opened Nov 9, 2023 by Renemiess
naxriscv boot on tang_primer 20k
#64 opened Nov 9, 2023 by 54o8
16
threshold of maxiumum count of Naxcore that can be possible to simulate ?
#62 opened Nov 6, 2023 by SoCScholar
3
L2 cache writeback Counter of specific core
#61 opened Nov 4, 2023 by SoCScholar
5
integrating both L2 cache miss counter and throttle
#58 opened Oct 29, 2023 by SoCScholar
39
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