Request for Guidance: Starting with a Minimal Framework

[skylayer]

Hi,

I've been working with SpinalHDL for a few months and am inspired by the design of NaxRiscv. I aim to deepen my understanding by building a toy CPU from scratch. While I appreciate the complexity and sophistication of NaxRiscv, I'm seeking an empty or minimal framework as a starting point for my project. Could you provide or direct me to such a simplified version of your framework? This would greatly aid in learning and applying your design methodology.

[Dolu1990]

Hi,

So i kinda had to recently make such framework because i wanted to start working on VexiiRiscv, which kinda adopt / improve many aspect of NaxRiscv :
https://github.com/SpinalHDL/VexiiRiscv

What aspect of the framework are you insterrested in ?

• Plugin
• Pipelining API
• ...

Like something with the plugin + one main pipeline ?

[skylayer]

Hi,

Thank you for your prompt response and for pointing me towards VexiiRiscv. I apologize for the delay in replying; I've been occupied with a course's final project recently.

I am interested in starting with a fundamental understanding of CPU design using SpinalHDL. My initial aim is to create a minimal implementation, such as a simple RV32I CPU that can perform basic operations like addition, equipped with a basic decoder and instruction/data buses. The plan is to gradually introduce more complex features, including cache management, a broader set of instructions, and hazard handling logic.

I've reviewed VexiiRiscv and noticed that its framework components, like Database and PluginHost, have been integrated into the main SpinalHDL line. Could you confirm if this allows me to begin my CPU design directly with SpinalHDL, utilizing these features, instead of building the foundational infrastructure from the ground up as seen in NaxRiscv and VexRiscv? This would greatly assist in efficiently planning my approach to the project.

[Dolu1990]

Hi,

Yes, the things merged into SpinalHDL 1.10.0 should be enough.
I would say, just copy past the https://github.com/SpinalHDL/VexiiRiscv/blob/dev/src/main/scala/spinal/lib/misc/database/DataBase.scala into your project if you want to use the database stuff ^^

Also, here are the things i did (in order) for VexiiRiscv :
SpinalHDL/VexiiRiscv#1

In general, for cpu design, you need to go little step by little step, it realy help.

[MahirAbbas]

@skylayer here are some textbooks to help (in order of complexity, from beginner to advanced)
Digital Design and Computer Architecture RISC-V Edition, Sarah Harris, David Harris
Computer Organization and Design RISC-V Edition The Hardware Software Interface (David A. Patterson, John L. Hennessy)
Next-Gen Computer Architecture: Till the End of Silicon, Smruti R. Sarangi
Computer Architecture: A Quantitative Approach, Sixth Edition, John L. Hennessy & David A. Patterson