Read a sram that is changed by other host

[zyn810039594]

Hi!
Is there anyway to read a block of sram that I have previously read but has been overwritten by another host(like a dma)? I use the Axi4 interface so there's not any cache coherency solution... Maybe there's someway to flush the cache?

[Dolu1990]

Hi,

They way that this is implemented in litex (for instance), is that there is an AXI to tilelink bridge which then goes toward the L2 cache.

NaxRiscv/src/main/scala/naxriscv/platform/litex/NaxSoc.scala

Line 74 in 8816542

val bridge = new Axi4ToTilelinkFiber(64, 4)

So all the axi trafic has to go through l2.

The main issue is that converting Axi to Tilelink is tricky / bottlneck, as AXI ordering need to be preserved for similar ID, while tilelink is fully out of order.
So it all depend how much efficiency / bandwidth / bridge implemention / axi ordering requirements you have