L1/L2 cache and integration with CPU pipeline

[SoCScholar]

Hi charles,

I have some doubt regarding L1 and L2 cache sets and cache line in each set of L1 and L2 data cache. can you please help me to clarify the doubt.

Is single cache line size of both L1 and L2 is of 64 Byte ?

Is L2 cache is 8 ways ?

Is the data cache is composed of 64 sets ?

I$ 16KB/4W, D$ 16KB/4W

64 (sets) × 4 (ways) × 64 (bytes in one way) = 16KB

Is physical addresses in the NAX RISC V data cache is 64-bit long (same as CPU) ?

is the data handled in the size of a single way :64 bytes) ?

I wonder how many stages of pipeline does NAXRISCV has ?
https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/introduction/index.html#pipeline

I also wonder how NAXRISCV core pipeline communicate/interacts with L1 data cache ? I couldn't understand How does it work?

Load Queue (LQ)/Store Queue (SQ) : Usually, 16 of each

https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/memory/index.html#memory-system

I also wonder what will happen in following situation in dual core Naxriscv

• load with hit in L1
• load with hit in L2
• load with miss in both
• store with hit in L1
• store with hit in L2
• store with miss in both

When the L2 cache is disabled, how does the L1 cache communicate with the DRAM memory controller? Specifically, what is default the data width used for communication between the L1 cache and the memory controller && between L1 cache and CPU core?

Similarly, What is default size of data width between L1 and L2 ? and what is default size of data width between L2 and Memory controller ?

[Dolu1990]

Hi,

Is single cache line size of both L1 and L2 is of 64 Byte ?

By default yes

Is L2 cache is 8 ways ?

i don't know which one you are using exactly, that is a parameter. You can add a println to figure that out at generation if you want.

Is the data cache is composed of 64 sets ?

L1 yes by default, that's the sweet spot, i hopped RISC-V had bigger pages

Is physical addresses in the NAX RISC V data cache is 64-bit long (same as CPU) ?

No, 32 bits for 32 bits RISC-V, 39 bits for 64 bits riscv

is the data handled in the size of a single way :64 bytes) ?

Data are always handled with 64 bytes (one line)

I wonder how many stages of pipeline does NAXRISCV has ?

Something around 10+, i don't remember exactly, would need to take mesurment to be realy sure.

I also wonder how NAXRISCV core pipeline communicate/interacts with L1 data cache ?

Through the Lsu2Plugin, its has 2 pipeline, one for load/store execute, one for store writeback

I also wonder what will happen in following situation in dual core Naxriscv

coherency is implemented with the MESI protocol between L1/L2

When the L2 cache is disabled, how does the L1 cache communicate with the DRAM memory controller?

It goes through a "Hub" which hold request while it send probe request to other L1. Then it proceed to DRAM

L1 cache and the memory controller

L1 -> Hub -> DDR

L1 -> Hub is using MESI memory coherency

default the data width

64 bits, as memory blocks in FPGA doesn't scale well past that threshold for 4KB pages

[SoCScholar]

Through the Lsu2Plugin, its has 2 pipeline, one for load/store execute, one for store writeback

The Load and store buffer is connected to the CPU through the Load and Store Unit (LSU) that have 16 entries for both Load Queue (LQ) and Store Queue (SQ). The Core pipeline interacts with the L1 caches through various mechanisms such as load and store queues, address generation units (AGU), cache hit speculation, hazard prediction, store-to-load bypassing, parallel memory translation, and a shared address pipeline.

As there is 64 Bit data width between core and L1 cache, I wonder how exactly core communicate with L1 cache ?