CN104795326A - Method for manufacturing silicon nanowire structure - Google Patents
Method for manufacturing silicon nanowire structure Download PDFInfo
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- CN104795326A CN104795326A CN201410020189.0A CN201410020189A CN104795326A CN 104795326 A CN104795326 A CN 104795326A CN 201410020189 A CN201410020189 A CN 201410020189A CN 104795326 A CN104795326 A CN 104795326A
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- silicon
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 87
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 87
- 239000010703 silicon Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000002070 nanowire Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 44
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 22
- 238000001039 wet etching Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000010790 dilution Methods 0.000 claims description 3
- 239000012895 dilution Substances 0.000 claims description 3
- 239000000428 dust Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 3
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 238000001035 drying Methods 0.000 abstract 1
- 238000009740 moulding (composite fabrication) Methods 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a method for manufacturing a silicon nanowire structure, comprising the following steps: providing a semiconductor substrate, and forming a silicon layer for constituting a silicon nanowire structure on the semiconductor substrate, wherein a hard mask layer is formed on the top of the silicon layer; forming a sacrificial material layer on the semiconductor substrate through depositing to cover the hard mask layer and the silicon layer; patterning the sacrificial material layer to make the sacrificial material layer only cover the two sides of the upper surface of the semiconductor substrate and the two sides of the hard mask layer and the silicon layer, wherein the sacrificial material layer at the two sides of the silicon layer forms spacers; implementing high-dose ion implantation and annealing, and forming an ion implantation area in the semiconductor substrate not covered by the sacrificial material layer; implementing wet drying to remove the ion implantation area and the part of the semiconductor substrate located under the spacers and the silicon layer in order to form the silicon nanowire structure composed of the silicon layer above the semiconductor substrate; and removing the remaining sacrificial layer and the remaining hard mask layer. According to the invention, the process window for forming a silicon nanowire structure is larger, and the precision is easier to control.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to the manufacture method of a kind of silicon nanowires (Nanowire) structure.
Background technology
According to Moore's Law, the size of semiconductor device progressively reduces in proportion, in the case, in order to more effective control short-channel effect, the semiconductor device with nonplanar structure is used widely, such as fin formula field effect transistor (FinFET) and nano-wire field effect transistor (Nanowire FET).
For nano-wire field effect transistor, the technique forming nano wire is very complicated, such as, first, forms stacked germanium silicon layer on a semiconductor substrate from bottom to top and is etched with for implementing the silicon layer forming nano wire; Then, silicon layer forms the first hard mask layer, graphical first hard mask layer; Then, form the second hard mask layer covered through patterned first hard mask layer, graphical second hard mask layer, with exposed portion first hard mask layer; Then, with through patterned second hard mask layer for mask, etching remove described in the silicon layer of the first hard mask layer of exposing and below thereof, to expose germanium silicon layer; Finally, germanium silicon layer is removed in etching, forms nano thread structure.In above-mentioned technical process, need formation twice hard mask layer, and respectively different patterning process is implemented to two hard mask layers, owing to being subject to the restriction of device feature size, very strict requirement is had to the process window of the etching process of above-mentioned patterning process and subsequent implementation and Parameter Conditions, very large to the difficulty of the precision controlling implementing above-mentioned technical process, very easily there is deviation, and then cause the final nano thread structure formed not reach the requirement of device layout.
Therefore, need to propose a kind of method, make nano thread structure by more simple technical process.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of silicon nanowire structure, comprising: Semiconductor substrate is provided, form the silicon layer for forming described silicon nanowire structure on the semiconductor substrate, and the top of described silicon layer being formed with hard mask layer; Deposition forms sacrificial material layer on the semiconductor substrate, to cover described hard mask layer and described silicon layer; Patternized technique is implemented to described sacrificial material layer, the two side portions of the upper surface of described Semiconductor substrate and the both sides of described hard mask layer and described silicon layer are only covered to make described sacrificial material layer, wherein, the sacrificial material layer being positioned at the both sides of described silicon layer forms side wall; Implement heavy dose of ion implantation and anneal, to form ion implanted region in the Semiconductor substrate of not covered by described sacrificial material layer; Implement wet etching to remove described ion implanted region and be positioned at the semiconductor substrate section below described side wall and described silicon layer, to form the described silicon nanowire structure be made up of described silicon layer above described Semiconductor substrate; Remove remaining described sacrificial material layer and described hard mask layer.
Further, form the step that described top has a silicon layer of hard mask layer to comprise: deposition forms hard mask layer on the semiconductor substrate; The photoresist layer with the top pattern of described silicon layer is formed by spin coating, exposure, developing process; Etching is removed not by the hard mask layer that described photoresist layer covers, and forms the hard mask layer with the top pattern of described silicon layer; Described photoresist layer is removed by cineration technics; There is the hard mask layer of the top pattern of described silicon layer for mask with described, etch described Semiconductor substrate, to form described silicon layer.
Further, the thickness of described hard mask layer is 20-500 dust, and the width of described silicon layer is 5-50nm, and the height of described silicon layer is 5-50nm, and the material of described hard mask layer is silicon nitride or silicon oxynitride.
Further, the thickness of described sacrificial material layer is 2-50nm, and the material of described sacrificial material layer is silicon nitride or silicon oxynitride.
Further, the injection ion of described ion implantation is arsenic or phosphorus, and implantation dosage is greater than 1.0 × e
18ion/square centimeter, Implantation Energy is 2-50KeV, and the angle injected between the incident direction of the ion direction perpendicular relative to described Semiconductor substrate is 0-7 degree, and the temperature of described annealing is higher than 1000 DEG C.
Further, removing the corrosive liquid of described wet etching implemented described ion implanted region is the chemical substance part not forming Doped ions of described ion implanted region and described Semiconductor substrate to high selectivity.
Further, the HF acid of the corrosive liquid of described wet etching to be concentration the be dilution of 1:10.
Further, employing wet etching process implements the removal to described remaining described sacrificial material layer and described hard mask layer.
Further, the corrosive liquid of described wet etching is phosphoric acid
According to the present invention, the process window forming the required technique such as photoetching, etching implemented of silicon nanowire structure is larger, and simple for process, craft precision more easily controls.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The vertical view of the device that Figure 1A-Fig. 1 E obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 2 A-Fig. 2 E is the schematic cross sectional view corresponding respectively to the device that the middle part along Semiconductor substrate of Figure 1A-Fig. 1 E and the perpendicular trend of silicon nanowire structure obtain;
Fig. 3 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the manufacture method of the silicon nanowire structure that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
With reference to Figure 1A-Fig. 1 E and Fig. 2 A-Fig. 2 E, the schematic cross sectional view of the device that the vertical view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively and the middle part along Semiconductor substrate of correspondence and the perpendicular trend of silicon nanowire structure obtain.
First, as shown in Figure 1A and Fig. 2 A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.
Next, form the silicon layer 101 for forming silicon nanowire structure on a semiconductor substrate 100, and the top of silicon layer 101 is formed with hard mask layer 102.In the present embodiment, the processing step that formation top has the silicon layer 101 of hard mask layer 102 comprises: deposition formation hard mask layer 102 on a semiconductor substrate 100, its constituent material preferred nitrogen SiClx or silicon oxynitride; The photoresist layer with the top pattern of silicon layer 101 is formed by techniques such as spin coating, exposure, developments; Etching is removed not by the hard mask layer 102 that described photoresist layer covers, and forms the hard mask layer 102 with the top pattern of silicon layer 101; Described photoresist layer is removed by cineration technics; There is the hard mask layer 102 of the top pattern of silicon layer 101 for mask, etching semiconductor substrate 100, to form silicon layer 101.The thickness of hard mask layer 102 is 20-500 dust, and the width of silicon layer 101 is 5-50nm, and the height of silicon layer 101 is 5-50nm.
Then, deposition forms sacrificial material layer 103 on a semiconductor substrate 100, to cover hard mask layer 102 and silicon layer 101.Then, as shown in fig. ib and fig. 2b, Patternized technique is implemented to sacrificial material layer 103, with the two side portions of upper surface and the both sides of hard mask layer 102 and silicon layer 101 that make sacrificial material layer 103 only cover Semiconductor substrate 100, wherein, the sacrificial material layer 103 being positioned at the both sides of silicon layer 101 forms side wall.In the present embodiment, the material preferred nitrogen SiClx of sacrificial material layer 103 or silicon oxynitride, the thickness of sacrificial material layer 103 is 2-50nm.
Then, as shown in figures 1 c and 2 c, implement heavy dose of ion implantation 104 and anneal, to form ion implanted region not being sacrificed in the Semiconductor substrate 100 that material layer 103 covers.In the present embodiment, the injection ion of heavy dose of ion implantation 104 is arsenic or phosphorus, and implantation dosage is greater than 1.0 × e
18ion/square centimeter, Implantation Energy is 2-50KeV, and the angle injected between the incident direction of the ion direction perpendicular relative to Semiconductor substrate 100 is 0-7 degree, and the temperature of annealing is higher than 1000 DEG C.
Then, as shown in Fig. 1 D and Fig. 2 D, implement wet etching and remove described ion implanted region and be positioned at Semiconductor substrate 100 part below described side wall and silicon layer 101, to form the silicon nanowire structure be made up of silicon layer 101 above Semiconductor substrate 100.In the present embodiment, the corrosive liquid of described wet etching is concentration is 1:10(HF:H
2the HF acid of dilution O) or other part not forming Doped ions for described ion implanted region and Semiconductor substrate 100 have the chemical substance of high selectivity.
Then, as shown in Fig. 1 E and Fig. 2 E, remaining sacrificial material layer 103 and hard mask layer 102 is removed.In the present embodiment, adopt wet etching process to implement described removal, the corrosive liquid of described wet etching is phosphoric acid.
So far, the processing step that the method according to an exemplary embodiment of the present invention that completes is implemented, next, can complete the making of whole semiconductor device by subsequent technique.According to the present invention, the process window forming the required technique such as photoetching, etching implemented of silicon nanowire structure is larger, and simple for process, craft precision more easily controls.
With reference to Fig. 2, illustrated therein is the flow chart of method according to an exemplary embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 201, providing Semiconductor substrate, form the silicon layer for forming silicon nanowire structure on a semiconductor substrate, and the top of silicon layer being formed with hard mask layer;
In step 202., deposition forms sacrificial material layer on a semiconductor substrate, to cover hard mask layer and silicon layer;
In step 203, implement Patternized technique to sacrificial material layer, to make sacrificial material layer only cover the two side portions of the upper surface of Semiconductor substrate and the both sides of hard mask layer and silicon layer, wherein, the sacrificial material layer being positioned at the both sides of silicon layer forms side wall;
In step 204, implement heavy dose of ion implantation and anneal, to form ion implanted region not being sacrificed in the Semiconductor substrate that material layer covers;
In step 205, the semiconductor substrate section that wet etching is removed described ion implanted region and is positioned at below described side wall and silicon layer is implemented, to form the silicon nanowire structure be made up of silicon layer above Semiconductor substrate;
In step 206, remaining sacrificial material layer and hard mask layer is removed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a manufacture method for silicon nanowire structure, comprising:
Semiconductor substrate (100) being provided, form the silicon layer (101) for forming described silicon nanowire structure on the semiconductor substrate, and the top of described silicon layer being formed with hard mask layer (102);
Deposition forms sacrificial material layer (103) on the semiconductor substrate, to cover described hard mask layer and described silicon layer;
Patternized technique is implemented to described sacrificial material layer, the two side portions of the upper surface of described Semiconductor substrate and the both sides of described hard mask layer and described silicon layer are only covered to make described sacrificial material layer, wherein, the sacrificial material layer being positioned at the both sides of described silicon layer forms side wall;
Implement heavy dose of ion implantation and anneal, to form ion implanted region in the Semiconductor substrate of not covered by described sacrificial material layer;
Implement wet etching to remove described ion implanted region and be positioned at the semiconductor substrate section below described side wall and described silicon layer, to form the described silicon nanowire structure be made up of described silicon layer above described Semiconductor substrate;
Remove remaining described sacrificial material layer and described hard mask layer.
2. method according to claim 1, is characterized in that, forms the step that described top has a silicon layer of hard mask layer and comprises: deposition forms hard mask layer on the semiconductor substrate; The photoresist layer with the top pattern of described silicon layer is formed by spin coating, exposure, developing process; Etching is removed not by the hard mask layer that described photoresist layer covers, and forms the hard mask layer with the top pattern of described silicon layer; Described photoresist layer is removed by cineration technics; There is the hard mask layer of the top pattern of described silicon layer for mask with described, etch described Semiconductor substrate, to form described silicon layer.
3. method according to claim 2, is characterized in that, the thickness of described hard mask layer is 20-500 dust, and the width of described silicon layer is 5-50nm, and the height of described silicon layer is 5-50nm, and the material of described hard mask layer is silicon nitride or silicon oxynitride.
4. method according to claim 1, is characterized in that, the thickness of described sacrificial material layer is 2-50nm, and the material of described sacrificial material layer is silicon nitride or silicon oxynitride.
5. method according to claim 1, is characterized in that, the injection ion of described ion implantation is arsenic or phosphorus, and implantation dosage is greater than 1.0 × e
18ion/square centimeter, Implantation Energy is 2-50KeV, and the angle injected between the incident direction of the ion direction perpendicular relative to described Semiconductor substrate is 0-7 degree, and the temperature of described annealing is higher than 1000 DEG C.
6. method according to claim 1, it is characterized in that, removing the corrosive liquid of described wet etching implemented described ion implanted region is the chemical substance part not forming Doped ions of described ion implanted region and described Semiconductor substrate to high selectivity.
7. method according to claim 6, is characterized in that, the HF acid of the corrosive liquid of described wet etching to be concentration the be dilution of 1:10.
8. method according to claim 1, is characterized in that, employing wet etching process implements the removal to described remaining described sacrificial material layer and described hard mask layer.
9. method according to claim 8, is characterized in that, the corrosive liquid of described wet etching is phosphoric acid.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410020189.0A CN104795326A (en) | 2014-01-16 | 2014-01-16 | Method for manufacturing silicon nanowire structure |
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| CN201410020189.0A CN104795326A (en) | 2014-01-16 | 2014-01-16 | Method for manufacturing silicon nanowire structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415902A (en) * | 2020-03-05 | 2020-07-14 | 中国科学院微电子研究所 | Metal nanostructure, manufacturing method thereof, electronic device and electronic equipment |
| CN112490118A (en) * | 2019-09-12 | 2021-03-12 | 长鑫存储技术有限公司 | Semiconductor device, hard mask structure and manufacturing method of hard mask structure |
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| CN103021806A (en) * | 2012-09-18 | 2013-04-03 | 上海集成电路研发中心有限公司 | Method for preparing silicon nanowire on monocrystalline silicon substrate |
| US20130224924A1 (en) * | 2012-02-27 | 2013-08-29 | International Business Machines Corporation | Pad-less gate-all around semiconductor nanowire fets on bulk semiconductor wafers |
| CN103295903A (en) * | 2012-03-05 | 2013-09-11 | 中国科学院微电子研究所 | Method for manufacturing fin type semiconductor device with wrap gate structure |
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2014
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| WO2006078281A2 (en) * | 2004-07-07 | 2006-07-27 | Nanosys, Inc. | Systems and methods for harvesting and integrating nanowires |
| US20080237684A1 (en) * | 2007-03-26 | 2008-10-02 | Michael Specht | Method of manufacturing a nanowire transistor, a nanowire transistor structure, a nanowire transistor field |
| US20130224924A1 (en) * | 2012-02-27 | 2013-08-29 | International Business Machines Corporation | Pad-less gate-all around semiconductor nanowire fets on bulk semiconductor wafers |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112490118A (en) * | 2019-09-12 | 2021-03-12 | 长鑫存储技术有限公司 | Semiconductor device, hard mask structure and manufacturing method of hard mask structure |
| CN112490118B (en) * | 2019-09-12 | 2022-05-17 | 长鑫存储技术有限公司 | Semiconductor device, hard mask structure and manufacturing method of hard mask structure |
| CN111415902A (en) * | 2020-03-05 | 2020-07-14 | 中国科学院微电子研究所 | Metal nanostructure, manufacturing method thereof, electronic device and electronic equipment |
| CN111415902B (en) * | 2020-03-05 | 2023-07-14 | 中国科学院微电子研究所 | Metal nano structure, manufacturing method thereof, electronic device and electronic equipment |
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Application publication date: 20150722 |