CN104124142B - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN104124142B CN104124142B CN201310143239.XA CN201310143239A CN104124142B CN 104124142 B CN104124142 B CN 104124142B CN 201310143239 A CN201310143239 A CN 201310143239A CN 104124142 B CN104124142 B CN 104124142B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 117
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims 2
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 phosphorus Ion Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor devices of present invention offer and its manufacturing method, the method includes：Semiconductor substrate is provided, sequentially forms the first sacrificial material layer and the second sacrificial material layer with the first opening on a semiconductor substrate；Offset side wall is formed on the side wall of the first opening；First sacrificial material layer of the first opening of etching lower section, to form the second opening；The semiconductor substrate of the second opening of etching lower section, to form groove；Gate oxide layers are formed in the trench, and form gate material layer on gate oxide layers and in the first opening and the second opening；The second sacrificial material layer and the first sacrificial material layer are removed successively, have jagged grid to form outer rim bottom.According to the present invention, the overlap capacitance between the source/drain region in grid and substrate can be reduced, the effective width of grid both sides offset side wall is reduced, the high stress contact etch stop layer of enhancing covering grid acts on the stress of the channel region below grid, promotes channel carrier mobility.
Description
Technical field
The present invention relates to semiconductor fabrication process, have jagged grid in particular to a kind of formation outer rim bottom
Method.
Background technology
When the manufacturing process node of cmos device reach 90nm and it is following when, low channel mobility, short-channel effect and
Overlap capacitance between grid and the source/drain region of substrate, which becomes, makes the principal element that the performance of such device declines.For this purpose, ability
The technical staff in domain promotes the channel mobility of device using various stress techniques.It is most widely used for NMOS
One of stress technique be to form the contact etch stop layer with high tensile stress on substrate（CESL）It is formed in covering
Grid on the substrate.The stress technique is mutually compatible with traditional semiconductor fabrication process, is not required to increase additional process, example
Such as additional epitaxial growth or photo-mask process.
In order to further enhance the stress that the contact etch stop layer acts on the channel region of cmos device, this field
Technical staff's generally use stress closely face technology, that is, reduce the thickness for the side wall for being formed in grid both sides.The stress technique needs
To realize that the reduction of the thickness for the side wall for being formed in grid both sides, the etching to a certain extent can be to grid using etch process
It causes to damage in pole；Due to the reduction of sidewall thickness, it is subsequently formed the probability that etching used by contact hole causes substrate damage
Become larger；Meanwhile the problem of short-channel effect and overlap capacitance, is not resolved.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, including：Semiconductor is provided
Substrate sequentially forms the first sacrificial material layer and the second sacrificial material layer with the first opening on the semiconductor substrate；
Offset side wall is formed on the side wall of first opening；First sacrificial material layer of first opening lower section is etched,
To form the second opening, the offset side wall is removed；The semiconductor substrate of second opening lower section is etched, it is recessed to be formed
Slot；Form gate oxide layers in the groove, and on the gate oxide layers and first opening and described second
Gate material layer is formed in opening；Second sacrificial material layer and first sacrificial material layer are removed successively, to form outer rim
Bottom has jagged grid.
Further, further include being formed to surround the grid and the covering semiconductor substrate after forming the grid
Shielding layer the step of.
Further, further include the steps that forming clearance wall in the both sides of the grid after forming the shielding layer.
Further, further include the steps that executing that ion implanting is lightly doped and anneals before forming the clearance wall, with
It is formed in the semiconductor substrate of the grid both sides and source/drain region is lightly doped.
Further, further include the steps that executing heavy doping ion to inject and anneal after forming the clearance wall, with
Heavy doping source/drain region is formed in the semiconductor substrate of the grid both sides.
Further, first sacrificial material layer is oxide skin(coating)；Second sacrificial material layer is nitride layer.
Further, the step of forming second sacrificial material layer with the first opening include：It is sacrificed described first
The second sacrificial material layer is formed in material layer；The figure with first opening is formed in second sacrificial material layer
Photoresist layer；Using the photoresist layer as mask, second sacrificial material layer is etched, until exposing first expendable material
Until layer；The photoresist layer is removed using cineration technics.
Further, the step of forming the offset side wall include：It is sacrificial to cover described second to deposit offset side wall material layer
The side wall and bottom of the surface of domestic animal material layer and first opening；The offset side wall material layer is etched to form the offset
Side wall.
Further, the material identical of the material of the offset side wall material layer and first sacrificial material layer, is etching
In the step of forming second opening, the offset side wall is removed substantially simultaneously.
Further, the gate oxide layers and the shielding layer are formed using thermal oxidation technology.
Further, second sacrificial material layer is removed using wet etching process.
Further, the step of removal first sacrificial material layer includes：First use anisotropic dry method etch technology
Implement the etching to first sacrificial material layer, until exposing the semiconductor substrate；Wet etching process is used again
Remove the first sacrificial material layer below the gate material layer.
The present invention also provides a kind of semiconductor devices, including：Semiconductor substrate；Form in the semiconductor substrate recessed
Slot；Gate oxide layers in the groove；The gate material layer being formed on the gate oxide layers, the gate material layer
There is recess between outer rim bottom and the semiconductor substrate.
Further, the semiconductor devices further includes：Surround the screening of the gate material layer and the covering semiconductor substrate
Cover layer and the clearance wall positioned at the gate material layer both sides.
Further, along the upper end of the recess to the lower end of the recess, the width of the gate material layer gradually reduces.
Further, the bottom width of the gate material layer and the gate oxide layers is of same size.
According to the present invention it is possible to which forming outer rim bottom on a semiconductor substrate has jagged grid, to reduce grid
With the overlap capacitance between the source/drain region in substrate, the effective width of the offset side wall of grid both sides, enhancing covering grid are reduced
High stress contact etch stop layer act on the stress of the channel region below grid, promote channel carrier mobility.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A-Fig. 1 M are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view；
Fig. 2 is that the method for exemplary embodiment of the present forms the flow chart that outer rim bottom has jagged grid.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Formation outer rim bottom have the method for jagged grid.Obviously, execution of the invention is not limited to the skill of semiconductor applications
The specific details that art personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions,
The present invention can also have other embodiment.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[exemplary embodiment]
In the following, A- Fig. 1 M and Fig. 2 forms outer rim bottom to describe method according to an exemplary embodiment of the present invention referring to Fig.1
Has the detailed step of jagged grid.
A- Fig. 1 M referring to Fig.1 are shown method according to an exemplary embodiment of the present invention and implement the step of institute successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 1A, semiconductor substrate 100 is provided, the constituent material of semiconductor substrate 100, which may be used, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）Deng.As an example, in the present embodiment, semiconductor
The constituent material of substrate 100 selects monocrystalline silicon.Isolation structure, various traps (well) structure etc. are formed in semiconductor substrate 100,
To put it more simply, being omitted in diagram.
Next, sequentially forming the first sacrificial material layer 101 and the second sacrificial material layer 102 on a semiconductor substrate 100.
The formation of first sacrificial material layer 101 and the second sacrificial material layer 102 may be used those skilled in the art be familiar with it is various
Suitable technique, such as chemical vapor deposition method.First sacrificial material layer 101 is oxide skin(coating), preferably silicon oxide layer；Second
Sacrificial material layer 102 is nitride layer, preferably silicon nitride layer.
Then, as shown in Figure 1B, the first opening 103 is formed in the second sacrificial material layer 102, sacrifices material to expose first
The bed of material 101.Formed first opening 103 processing step include：Being formed in the second sacrificial material layer 102 has the first opening
The photoresist layer of 103 figure；Using the photoresist layer as mask, the second sacrificial material layer 102 is etched, until it is sacrificial to expose first
Until domestic animal material layer 101；The photoresist layer is removed using cineration technics.To the etching gas of the second sacrificial material layer 102 etching
Body includes CF4、CHF3、CH2F2、CH3F etc..
Then, as shown in Figure 1 C, offset side wall 104 is formed on the side wall of the first opening 103.Form offset side wall 104
Processing step include：Deposition offset side wall material layer is to cover surface and the first opening 103 of second sacrificial material layer 102
Side wall and bottom；The offset side wall material layer is etched to form offset side wall 104.The material of the offset side wall material layer is excellent
The material identical of choosing and the first sacrificial material layer 101, in the present embodiment, the material of the offset side wall material layer is oxidation
Silicon.Etching gas to offset side wall material layer etching includes CF4、CHF3、C2F6、C4F8、C5F8Deng.
Then, as shown in figure iD, the first sacrificial material layer 101 of 103 lower section of the first opening of etching, to sacrifice material first
The second opening 105 is formed in the bed of material 101.It is described be etched through expose semiconductor substrate 100 when terminate, offset side wall 104 is same
When remove, the top width of the second opening 105 of formation is of same size with the first opening 103, and the second of formation is open 105
Bottom width is less than the width of the first opening 103.Etching to the first sacrificial material layer 101 etching of 103 lower section of the first opening
Gas includes CF4、CHF3、C2F6、C4F8、C5F8Deng.
Then, as referring to figure 1E, the semiconductor substrate 100 of 105 lower section of the second opening of etching, in semiconductor substrate 100
Middle formation groove 107 '.The etching gas etched to the semiconductor substrate 100 of 105 lower section of the second opening includes CF4、HBr、Cl2、
CHF3、O2Deng.
Then, as shown in fig. 1F, gate oxide layers 107 are formed in groove 107 '.The formation of gate oxide layers 107 can be with
The various suitable techniques being familiar with using those skilled in the art, such as thermal oxidation technology.
Next, forming gate material layer on gate oxide layers 107 and in the first opening 103 and the second opening 105
106.The various suitable techniques that those skilled in the art are familiar with, such as chemical gas may be used in the formation of gate material layer 106
Phase depositing operation and the chemical mechanical milling tech then implemented.106 preferred polysilicon layer of gate material layer.
Then, as shown in Figure 1 G, the second sacrificial material layer 102 is removed.The removal of second sacrificial material layer 102 may be used
The various suitable techniques that those skilled in the art are familiar with, such as wet etching process.
Then, as shown in fig. 1H, the first sacrificial material layer 101 is etched, until exposing semiconductor substrate 100.Using
Anisotropic dry method etch technology implements the etching to the first sacrificial material layer 101 and is located at grid material after the etching terminates
First sacrificial material layer 101 of 106 lower section of the bed of material is not removed.
Then, as shown in Figure 1 I, the first sacrificial material layer 101 of 106 lower section of removal gate material layer, in gate material layer
106 form recess 108 ' close to the bottom of outer rim.Implement to sacrifice to the first of 106 lower section of gate material layer using wet etching process
The removal of material layer 101.So far, outer rim bottom is formed on a semiconductor substrate 100 have jagged grid 106 '.
It should be noted that the above-mentioned removal to the first sacrificial material layer 101 can also be lost by the wet method that a step is completed
Carving technology is implemented.
Then, as shown in figure iJ, the shielding layer 108 for surrounding grid 106 ' and covering semiconductor substrate 100 is formed.Using heat
Oxidation technology forms shielding layer 108.
Then, as shown in figure iK, execute and ion implanting is lightly doped and anneals, in the semiconductor substrate of 106 ' both sides of grid
It is formed in 100 and source/drain region 109 is lightly doped.For NMOS transistor, the Doped ions that ion implanting is lightly doped can be phosphorus
Ion or arsenic ion etc.；For PMOS transistor, the Doped ions that ion implanting is lightly doped can be boron ion or
Indium ion etc..
Then, as can be seen in 1L, clearance wall 110 is formed in the both sides of grid 106 '.The material of clearance wall 110 preferably nitrogenizes
Silicon.
Then, as depicted in figure iM, execute heavy doping ion to inject and anneal, in the semiconductor substrate of 106 ' both sides of grid
Heavy doping source/drain region 111 is formed in 100.
So far, whole processing steps that method according to an exemplary embodiment of the present invention is implemented are completed, next, can be with
The making of entire semiconductor devices is completed by subsequent technique.According to the present invention it is possible to form outer rim bottom on a semiconductor substrate
Portion has jagged grid, to reduce the overlap capacitance between the source/drain region in grid and substrate, reduces the inclined of grid both sides
The effective width of side wall is moved, the high stress contact etch stop layer of enhancing covering grid acts on the channel region below grid
Stress promotes channel carrier mobility.
With reference to Fig. 2, it is jagged that method formation outer rim according to an exemplary embodiment of the present invention bottom tool is shown
The flow chart of grid, the flow for schematically illustrating entire manufacturing process.
In step 201, semiconductor substrate is provided, sequentially form the first sacrificial material layer on a semiconductor substrate and is had
Second sacrificial material layer of the first opening；
In step 202, offset side wall is formed on the side wall of the first opening；
In step 203, the first sacrificial material layer of the first opening of etching lower section, to form the second opening, removal offset
Side wall；
In step 204, the semiconductor substrate of the second opening of etching lower section, to form groove；
In step 205, gate oxide layers are formed in a groove, and on gate oxide layers and the first opening and second
Gate material layer is formed in opening；
In step 206, the second sacrificial material layer and the first sacrificial material layer are removed successively, are had to form outer rim bottom
The grid of recess.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of manufacturing method of semiconductor devices, including：
Semiconductor substrate is provided, sequentially form on the semiconductor substrate the first sacrificial material layer and with the first opening the
Two sacrificial material layers；
Offset side wall is formed on the side wall of first opening；
First sacrificial material layer for etching first opening lower section removes the offset to be formed while the second opening
Side wall；
The semiconductor substrate for etching second opening lower section, to form groove；
Form gate oxide layers in the groove, and on the gate oxide layers and first opening and described second
Gate material layer is formed in opening；
Second sacrificial material layer and first sacrificial material layer are removed successively, have jagged grid to form outer rim bottom
Pole.
Further include being formed to surround institute 2. according to the method described in claim 1, it is characterized in that, after forming the grid
The step of stating grid and the shielding layer of the covering semiconductor substrate.
Further include in the grid 3. according to the method described in claim 2, it is characterized in that, after forming the shielding layer
The both sides of pole form the step of clearance wall.
Further include executing gently to mix 4. according to the method described in claim 3, it is characterized in that, before forming the clearance wall
Source/drain region is lightly doped to be formed in the semiconductor substrate of the grid both sides in the step of heteroion is injected and annealed.
Further include that execution is heavily doped 5. according to the method described in claim 4, it is characterized in that, after forming the clearance wall
The step of heteroion is injected and is annealed, to form heavy doping source/drain region in the semiconductor substrate of the grid both sides.
6. according to the method described in claim 1, it is characterized in that, first sacrificial material layer is oxide skin(coating)；Described
Two sacrificial material layers are nitride layer.
7. according to the method described in claim 1, it is characterized in that, forming second sacrificial material layer with the first opening
The step of include：The second sacrificial material layer is formed in first sacrificial material layer；The shape in second sacrificial material layer
At the photoresist layer of the figure with first opening；Using the photoresist layer as mask, second expendable material is etched
Layer, until exposing first sacrificial material layer；The photoresist layer is removed using cineration technics.
8. according to the method described in claim 1, it is characterized in that, the step of forming the offset side wall includes：Deposition offset
Spacer material layer is to cover the surface of second sacrificial material layer and side wall and the bottom of first opening；It etches described inclined
Spacer material layer is moved to form the offset side wall.
9. according to the method described in claim 8, it is characterized in that, the material of the offset side wall material layer and described first sacrificial
The material identical of domestic animal material layer.
10. according to the method described in claim 2, it is characterized in that, using thermal oxidation technology formed the gate oxide layers and
The shielding layer.
11. according to the method described in claim 1, it is characterized in that, sacrificing material using wet etching process removal described second
The bed of material.
12. according to the method described in claim 1, it is characterized in that, the step of removing first sacrificial material layer includes：First
Etching to first sacrificial material layer is implemented using anisotropic dry method etch technology, until exposing the semiconductor lining
Until bottom；The first sacrificial material layer below the gate material layer is removed using wet etching process again.
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| US6133606A (en) * | 1999-05-12 | 2000-10-17 | United Microelectronics Corp. | High voltage complementary semiconductor device (HV-CMOS) with gradient doping electrodes |
| TW200428537A (en) * | 2003-01-08 | 2004-12-16 | Ibm | Improved MOS transistor |
| CN1983532A (en) * | 2005-12-14 | 2007-06-20 | 东部电子股份有限公司 | Method of manufacturing semiconductor device |
| CN1992341A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Semiconductor device and method for manufacturing the same |
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| KR20070087728A (en) * | 2005-08-29 | 2007-08-29 | 동부일렉트로닉스 주식회사 | Method for forming gate of semiconductor device by polymer |
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| US6133606A (en) * | 1999-05-12 | 2000-10-17 | United Microelectronics Corp. | High voltage complementary semiconductor device (HV-CMOS) with gradient doping electrodes |
| TW200428537A (en) * | 2003-01-08 | 2004-12-16 | Ibm | Improved MOS transistor |
| CN1983532A (en) * | 2005-12-14 | 2007-06-20 | 东部电子股份有限公司 | Method of manufacturing semiconductor device |
| CN1992341A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Semiconductor device and method for manufacturing the same |
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