AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
Jul 31, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
AXI4 and AXI4-Lite interface definitions
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
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