#
axi4-lite-interface
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This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
vivado
system-verilog
verilator
axi4
axi4-lite
axi4-protocol
axi4-lite-interface
axi4-lite-system-verilog
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Updated
May 4, 2024 - SystemVerilog
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
systemverilog
hardware-designs
verilator
axi4-lite
axi4-protocol
vivado-simulator
axi4-lite-interface
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Updated
May 4, 2024 - SystemVerilog
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
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Updated
Apr 7, 2024 - Verilog
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