dpretet / svut Sponsor Star 67 Code Issues Pull requests SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests! python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator svut Updated Sep 24, 2024 Python
dpretet / bster Sponsor Star 13 Code Issues Pull requests Implementation of a binary search tree algorithm in a FPGA/ASIC IP asic fpga ip verilog binary-tree systemverilog binary-trees bst fpga-accelerator bstree asic-design svut Updated Sep 5, 2021 SystemVerilog
dpretet / meduram Sponsor Star 11 Code Issues Pull requests Multi-port BRAM IP for ASIC and FPGA block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface Updated Apr 21, 2021 SystemVerilog