SKILL Package Manager
-
Updated
Apr 17, 2019
SKILL Package Manager
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Quasar 2.0: Chisel equivalent of SweRV-EL2
Implementation (VHDL) and verification of the accelerator proposed in the paper "Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification", from May 2020
Laboratories of 'Microelectronic Systems' course at PoliTo
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
E&D Skill Application Manager (SAM)
MATLAB code for the lab sessions in the "ASIC for DSP" course at LiU-ISY
Resources accompanying my talk at NLUUG 2022
Wolf sheep cabbage river crossing puzzle ASIC design (🐺🐐🥬🚣)
300 baud 8N1 UART transmitter with limited character set (0x40..0x5F) loading as ASIC design
This repository contains the work done during learning LinuxFoundationX LFD111x Building a RISC-V CPU Core
A simple Recap for different Digital Design topics from different references and books.
Some simple examples for the Magic VLSI physical chip layout tool using Google Skywater130 PDK.
Moore.io Demo Project
Add a description, image, and links to the asic-design topic page so that developers can more easily learn about it.
To associate your repository with the asic-design topic, visit your repo's landing page and select "manage topics."