chipsalliance / Cores-VeeR-EH1 Star 823 Code Issues Pull requests VeeR EH1 core fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer Updated May 29, 2023 SystemVerilog
chipsalliance / Cores-VeeR-EL2 Star 250 Code Issues Pull requests VeeR EL2 Core fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2 Updated Nov 27, 2024 SystemVerilog
Lampro-Mellon / Quasar Star 28 Code Issues Pull requests Quasar 2.0: Chisel equivalent of SweRV-EL2 scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2 Updated Apr 13, 2021 Scala
TILhub / AMBA-3-AHB-Lite-Protocol Star 13 Code Issues Pull requests This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol arm cplusplus protocol emulation stl systemc lite testbenches testbench amba ahb-lite Updated Jul 11, 2018 C++
shalan / MS_DMAC_AHBL Star 10 Code Issues Pull requests A Direct Memory Access Controller (DMAC) with AHB-lite bus interface asic fpga verilog dma dmac ahb-lite Updated Oct 6, 2024 Verilog
shalan / MS_QSPI_XIP_CACHE Star 8 Code Issues Pull requests AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP asic ip verilog ahb-lite qspi qspi-flash sky130 Updated Nov 9, 2023 Verilog
vicharak-in / vaaman-ahb-verilog Star 1 Code Issues Pull requests Verilog AHB Bus implementation for VAAMAN verilog verilog-hdl ahb3-lite ahb ahb-lite Updated Dec 30, 2023 Verilog