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[wb_trigger] Add enable input in each logical trigger
enhancement
#74
opened Aug 18, 2018 by
danielot
[flash_loader] Implement Flash Loader via PCIe/Wishbone
enhancement
#55
opened Apr 27, 2016 by
lerwys
[vivado_project] AXI Interconnect BPM is not generated as VHDL and simulation fails
bug
#51
opened Dec 18, 2015 by
lerwys
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