[wb_fmc130m_4ch] ADC clock current delay value not used

[lerwys]

Problem: The current ADC clock delay used in the Delay primitive is not used. We only output the current delay for the data channels. This can cause confusion for the software, as the value read in the registers will not be the same as the value just written. This does not produce wrong results, but is confusing on readback tests, for instance.

Possible solution: Output the current ADC clock delay in another Wishbone register.