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[Interlock] Improvements #83

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5 tasks done
lerwys opened this issue Apr 28, 2021 · 1 comment
Closed
5 tasks done

[Interlock] Improvements #83

lerwys opened this issue Apr 28, 2021 · 1 comment

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@lerwys
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lerwys commented Apr 28, 2021 •
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Suggestions from operations:

  • Fix current interlock status. This is not readable as the FPGA generates a shot pulse. We need to stretch it so a software can read.
  • Check angular interlock calculation. We need to use downstream position - upstream position
  • Add calculated translation/angular register so we can better debug what is being done inside the FPGA
  • Add MONIT1 data rate to Post-Mortem acquisition #84
  • Check what interlocks are actually being maskedby the `enable bits
@danielot
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Should we close this issue? All tasks have been done.

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@lerwys @danielot @augustofg