[vivado_project] AXI Interconnect BPM is not generated as VHDL and simulation fails

[lerwys]

Problem: Even though the target language VHDL it is explicitly set in the .xci file, Vivado insists in inheriting the target language from the project, which is Verilog. The Verilog model, for some reason, causes problems in simulation with AXI interconnect BPM.

Workaround: To be able to run the simulation correctly, we have to open the Vivado project, set the project language as VHDL and regenrate ONLY the AXI interconnect BPM core. After that, it is safe to go back to target language Verilog.