WO2016192799A1 - Parallel-coupled switching devices and switch-mode power converter - Google Patents

Parallel-coupled switching devices and switch-mode power converter Download PDF

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Publication number
WO2016192799A1
WO2016192799A1 PCT/EP2015/062481 EP2015062481W WO2016192799A1 WO 2016192799 A1 WO2016192799 A1 WO 2016192799A1 EP 2015062481 W EP2015062481 W EP 2015062481W WO 2016192799 A1 WO2016192799 A1 WO 2016192799A1
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WIPO (PCT)
Prior art keywords
switching device
turn
circuit
power converter
mode power
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PCT/EP2015/062481
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French (fr)
Inventor
Ahmet Berkant ECEVIT
Reyhan Turk
Hakan Suleyman YARDIBI
Original Assignee
Arcelik Anonim Sirketi
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Priority to PCT/EP2015/062481 priority Critical patent/WO2016192799A1/en
Priority to TR2016/06371A priority patent/TR201606371A2/en
Publication of WO2016192799A1 publication Critical patent/WO2016192799A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to an electrical power switching circuit and more particularly to parallel-coupled switching devices and an associated switch-mode power converter.
  • Switching devices such as IGBTs (Insulated Gate Bipolar Transistor) are capable of high switching speeds needed for certain loads such as electrical motors. Instantaneous power dissipation occurs in a switching device during the turn-on and turn-off intervals. Since the switching power loss is linearly dependent on the switching frequency, a switching device with shorter switching times will substantially limit the switching power loss.
  • IGBTs Insulated Gate Bipolar Transistor
  • the power loss of the switching device during conduction also adds to the power dissipation during the on-state.
  • the on-state voltage is decisive in determining conduction losses.
  • US4532443 discloses a power switching circuit for switching power from a DC supply to a regenerative load, comprising: a plurality of power MOSFETs each having source, drain and gate elements with the source-drain circuits parallel connected between the DC supply and the regenerative load, each of the MOSFETs having an inherent reverse diode junction between the source and drain elements; a control signal source having a switching control signal output connected with the gate element of each MOSFET, switching the MOSFET source-drain circuits on and off at a selected rate; a first diode connected in parallel with the source-drain circuits of the power MOSFETs and poled to conduct reverse current from the load; and a second diode connected in series with the source-drain circuits of the power MOSFETs and poled to block current flow through the reverse diode junctions of the MOSFETs, the series combination of the second diode and the source-drain
  • the present invention provides a switched-mode power converter having parallel-coupled switching devices operable so as to feature decreased switching and conduction losses as provided by the characterizing features defined in Claim 1.
  • Primary object of the present invention is to provide a switched-mode power converter having parallel-coupled switching devices operable so as to feature decreased switching and conduction losses.
  • the present invention proposes a switched-mode power converter comprising parallel switching devices such that a first delaying circuit in electrical connection with a gate driving circuit and a first switching device delays turn-off of the first switching device. Further a second delaying circuit in electrical connection with the gate driving circuit and a second switching device delays turn-on of the second switching device.
  • the first switching device is faster than the second switching device in the sense that it has shorter turn-on and turn-off crossover intervals in comparison to the second switching device.
  • the first faster switching device with lower turn-on power loss starts conducting prior to the second switching device so that it conducts a greater proportion of the current being shared.
  • it continues to conduct current while the second switching device is being turned off as a result of which a greater proportion of the switching off current switches to the faster switching device.
  • Fig. 1 demonstrates a simplified block diagram of a switched-mode power converter driving circuit according to the present invention.
  • Fig. 2 demonstrates a circuit diagram of a switched-mode power converter driving signal adjustment circuit according to the present invention.
  • the present invention proposes a switched-mode power converter designated generally by the numeral 1.
  • the switched-mode power converter (1) comprises parallel-coupled first and second switching devices (9 and 10) such as for instance IGBTs (Insulated Gate Bipolar Transistor).
  • IGBTs Insulated Gate Bipolar Transistor
  • a switching device causes Instantaneous power dissipation during the turn-on and turn-off intervals.
  • a switching device When a switching device is turned on, the current flows through the switching device while a parallel diode remains reverse biased.
  • the switching device When the switching device is turned off, an input voltage appears across the switching device.
  • a delay time will be followed by a current rise time upon which the voltage across the terminals of the switching device falls to a certain on-state value.
  • the energy losses during the conduction time will be dependent on the on-state voltage and current.
  • a first switching device (9) with shorter turn-on and turn-off crossover intervals in comparison to a second switching device (10) is connected in parallel to the first switching device (9).
  • the second switching device (10) has larger turn-on and turn-off transition times compared to the first switching device (9). Therefore, the first switching device (9) according to the invention is faster compared to the second switching device (10) connected in parallel.
  • first turn-on circuit (4) effectuates turning on of the first switching device (9)
  • a first turn-off circuit (6) accordingly turns off the first switching device (9).
  • second turn-on and turn-off circuits (5, 7) function so as to initiate and terminate the conduction state of the second switching device (10).
  • first and second delay circuits (2, 3) provide that the first and second switching devices (9, 10) are biased to conduction and non-conduction modes.
  • the first and second delay circuits (2, 3) serve to the purpose of lowering power losses and increasing power conversion efficiency by way of delaying turning-on and turning-off of the first and second switching devices (9, 10) as will be delineated hereinafter.
  • the first delay circuit (2) serves to the purpose of delaying turning-off of the first switching device (9). Therefore, the first switching device (9) continues to conduct current while the second switching device (9) is being turned off and therefore transitions between conduction and non-conduction modes of the switched-mode power converter (1) is substantially effectuated by the first switching device (9), which is faster and thereby incurring lower switching losses.
  • the faster switching device (the first switching device, 9) with lower turn on power loss switches a greater proportion of the current on and off
  • the slower parallel switching device (the second switching device, 10) having lower on-state loss characteristics shares the conduction current during the on-state duration so that a lower overall conduction loss occurs compared to the situation where the faster switching device (the first switching device, 9) operates alone.
  • the circuit arrangement according to the present invention advantageously lowers conduction losses by the second switching device (10) while at the same time lowering switching losses thanks to the first switching device (9).
  • the circuit topology with the first and second switching devices (9, 10) being in parallel offers increased efficiency by 2,5% compared to the faster switching device (the first switching device, 9) operating alone and by 8,1 percent compared to the slower switching device (the second switching device, 10) if operated alone. It is to be noted that the efficiency of the converter will increase even further depending on the switching frequency of the switched-mode power converter (1) since the switching power loss is linearly dependent on the switching frequency and a switching device with shorter switching times will substantially limit switching losses.
  • the first delay circuit (2) generating the “faster switch” output can be realized by way of changing the values of the resistor R 4 and capacitor C 1 so as to adjust the turn-on time of the transistor Q 2 so that the turn-off time of the first switching device (9) connected to the “faster switch” output can be delayed.
  • the second delay circuit (3) generating the “slower switch” output can be realized by way of changing the values of the resistor R 1 and capacitor C 2 so as to adjust the turn-on time of the transistor Q 1 so that the turn-on time of the second switching device (10) connected to the “slower switch” output can be delayed. Therefore, the first and second delay circuits (2, 3) respectively delay turn-off of the first switching device (9) and turn-on of the second switching device (10).
  • a first delaying circuit (2) is connected between a gate driving circuit (8) and the first switching device (9) in the manner that the first delaying circuit (2) delays turn-off of the first switching device (9) and a second delaying circuit (3) is connected between the gate driving circuit (8) and the second switching device (10) in the manner that the second delaying circuit (3) delays turn-on of the second switching device (10).
  • the present invention proposes a switched-mode power converter (1) comprising a first switching device (9) connected electrically in parallel to a second switching device (10), the first and second switching devices (9 and 10) being driven by a gate driving circuit (8).
  • a first delaying circuit (2) is connected between the gate driving circuit (8) and the first switching device (9) in the manner that the first delaying circuit (2) delays turn-off of the first switching device (9) and a second delaying circuit (3) is connected between the gate driving circuit (8) and the second switching device (10) in the manner that the second delaying circuit (3) delays turn-on of the second switching device (10).
  • the first switching device (9) has shorter turn-on and turn-off crossover intervals in comparison to the second switching device (10).
  • a first turn-on circuit (4) provides that the first switching device (9) is biased to conduction and a first turn-off circuit (6) provides that the first switching device (9) is biased to non-conduction modes.
  • a second turn-on circuit (5) provides that the second switching device (10) is biased to conduction and a second turn-off circuit (7) provides that the second switching device (10) is biased to non-conduction modes.
  • the first switching device (9) with lower turn-on and turn-off power loss starts conducting prior to the second switching device (10) and by the time the second switching device (10) is turned on, the first switching device (9) conducts a greater proportion of the current being shared.
  • the first switching device (9) continues to conduct current while the second switching device (9) is being turned off.
  • transitions between conduction and non-conduction modes of the switched-mode power converter (1) is substantially effectuated by the first switching device (9).
  • the present invention therefore provides a switched-mode power converter (1) having parallel-coupled first and second switching devices (9, 10) operable so as to feature decreased switching and conduction losses. While the first switching device (9) provides lowering of the switching losses, the second switching device (10) is advantageous in lowering on-state losses.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)

Abstract

The present invention relates to a power electrical switching circuit and more particularly to parallel-coupled switching devices and an associated switched-mode power converter (1). The present invention more particularly relates to a switched-mode power converter (1) comprising a first switching device (9) connected electrically in parallel to a second switching device (9), the first and second switching devices (9 and 10) being driven by a gate driving circuit (8).

Description

PARALLEL-COUPLED SWITCHING DEVICES AND SWITCH-MODE POWER CONVERTER
The present invention relates to an electrical power switching circuit and more particularly to parallel-coupled switching devices and an associated switch-mode power converter.

Switching devices such as IGBTs (Insulated Gate Bipolar Transistor) are capable of high switching speeds needed for certain loads such as electrical motors. Instantaneous power dissipation occurs in a switching device during the turn-on and turn-off intervals. Since the switching power loss is linearly dependent on the switching frequency, a switching device with shorter switching times will substantially limit the switching power loss.
On the other hand, it is also to be noted that the power loss of the switching device during conduction also adds to the power dissipation during the on-state. The on-state voltage is decisive in determining conduction losses.
Among others, a prior art publication in the technical field of the invention may be referred to as US4532443, which discloses a power switching circuit for switching power from a DC supply to a regenerative load, comprising: a plurality of power MOSFETs each having source, drain and gate elements with the source-drain circuits parallel connected between the DC supply and the regenerative load, each of the MOSFETs having an inherent reverse diode junction between the source and drain elements; a control signal source having a switching control signal output connected with the gate element of each MOSFET, switching the MOSFET source-drain circuits on and off at a selected rate; a first diode connected in parallel with the source-drain circuits of the power MOSFETs and poled to conduct reverse current from the load; and a second diode connected in series with the source-drain circuits of the power MOSFETs and poled to block current flow through the reverse diode junctions of the MOSFETs, the series combination of the second diode and the source-drain circuits of the power MOSFETs being shunted by the first diode.
The present invention provides a switched-mode power converter having parallel-coupled switching devices operable so as to feature decreased switching and conduction losses as provided by the characterizing features defined in Claim 1.
Primary object of the present invention is to provide a switched-mode power converter having parallel-coupled switching devices operable so as to feature decreased switching and conduction losses.
The present invention proposes a switched-mode power converter comprising parallel switching devices such that a first delaying circuit in electrical connection with a gate driving circuit and a first switching device delays turn-off of the first switching device. Further a second delaying circuit in electrical connection with the gate driving circuit and a second switching device delays turn-on of the second switching device.
The first switching device is faster than the second switching device in the sense that it has shorter turn-on and turn-off crossover intervals in comparison to the second switching device.
In sum, the first faster switching device with lower turn-on power loss starts conducting prior to the second switching device so that it conducts a greater proportion of the current being shared. On the other hand, it continues to conduct current while the second switching device is being turned off as a result of which a greater proportion of the switching off current switches to the faster switching device.
Accompanying drawings are given solely for the purpose of exemplifying a switch-mode power converter whose advantages over prior art were outlined above and will be explained in brief hereinafter.
The drawings are not meant to delimit the scope of protection as identified in the claims nor should they be referred to alone in an effort to interpret the scope identified in the claims without recourse to the technical disclosure in the description of the present invention.
Fig. 1 demonstrates a simplified block diagram of a switched-mode power converter driving circuit according to the present invention.
Fig. 2 demonstrates a circuit diagram of a switched-mode power converter driving signal adjustment circuit according to the present invention.
The following numerals are assigned to different parts being referred to in the detailed description:
  1. Switched-mode power converter
  2. First delay circuit
  3. Second delay circuit
  4. First turn-on circuit
  5. Second turn-on circuit
  6. First turn-off circuit
  7. Second turn-off circuit
  8. Gate driving circuit
  9. First switching device
  10. Second switching device
The present invention proposes a switched-mode power converter designated generally by the numeral 1. The switched-mode power converter (1) comprises parallel-coupled first and second switching devices (9 and 10) such as for instance IGBTs (Insulated Gate Bipolar Transistor).
A switching device causes Instantaneous power dissipation during the turn-on and turn-off intervals. When a switching device is turned on, the current flows through the switching device while a parallel diode remains reverse biased. On the other hand, when the switching device is turned off, an input voltage appears across the switching device.
During the turn-on transition of the switching device, a delay time will be followed by a current rise time upon which the voltage across the terminals of the switching device falls to a certain on-state value. As the switching device will remain in conduction during a conduction time, which can typically be larger than the turn-on and turn-off transition times, the energy losses during the conduction time will be dependent on the on-state voltage and current.
Likewise, during the turn-off transition of the switching device, a turn-off delay will be followed by a voltage rise upon which the parallel diode becomes forward biased and conducts current.
According to the present invention, a first switching device (9) with shorter turn-on and turn-off crossover intervals in comparison to a second switching device (10) is connected in parallel to the first switching device (9). In other words, the second switching device (10) has larger turn-on and turn-off transition times compared to the first switching device (9). Therefore, the first switching device (9) according to the invention is faster compared to the second switching device (10) connected in parallel.
While a first turn-on circuit (4) effectuates turning on of the first switching device (9), a first turn-off circuit (6) accordingly turns off the first switching device (9). Likewise, second turn-on and turn-off circuits (5, 7) function so as to initiate and terminate the conduction state of the second switching device (10). According to the present invention, first and second delay circuits (2, 3) provide that the first and second switching devices (9, 10) are biased to conduction and non-conduction modes.
The first and second delay circuits (2, 3) serve to the purpose of lowering power losses and increasing power conversion efficiency by way of delaying turning-on and turning-off of the first and second switching devices (9, 10) as will be delineated hereinafter.
Turn-on of the second switching device (10), which is slower compared to the first switching device (9), is delayed by the second delay circuit (3). Therefore, the first switching device (9) with lower turn-on power loss starts conducting prior to the second switching device (10) and by the time the second switching device (10) is turned on, the first switching device (9) conducts a greater proportion of the current, thereby contributing to lowering overall switching power losses.
Likewise, the first delay circuit (2) serves to the purpose of delaying turning-off of the first switching device (9). Therefore, the first switching device (9) continues to conduct current while the second switching device (9) is being turned off and therefore transitions between conduction and non-conduction modes of the switched-mode power converter (1) is substantially effectuated by the first switching device (9), which is faster and thereby incurring lower switching losses.
According to the present invention, while the faster switching device (the first switching device, 9) with lower turn on power loss switches a greater proportion of the current on and off, the slower parallel switching device (the second switching device, 10) having lower on-state loss characteristics shares the conduction current during the on-state duration so that a lower overall conduction loss occurs compared to the situation where the faster switching device (the first switching device, 9) operates alone.
As the power loss of the switching devices during the on-state also adds to the overall power dissipation, the on-state voltage drop of the switching devices is decisive in determining conduction losses. Therefore, the circuit arrangement according to the present invention advantageously lowers conduction losses by the second switching device (10) while at the same time lowering switching losses thanks to the first switching device (9).
It is established that the circuit topology with the first and second switching devices (9, 10) being in parallel offers increased efficiency by 2,5% compared to the faster switching device (the first switching device, 9) operating alone and by 8,1 percent compared to the slower switching device (the second switching device, 10) if operated alone. It is to be noted that the efficiency of the converter will increase even further depending on the switching frequency of the switched-mode power converter (1) since the switching power loss is linearly dependent on the switching frequency and a switching device with shorter switching times will substantially limit switching losses.
Referring to Fig. 2 depicting an exemplary embodiment according to the present invention, the first delay circuit (2) generating the “faster switch” output can be realized by way of changing the values of the resistor R4 and capacitor C1 so as to adjust the turn-on time of the transistor Q2 so that the turn-off time of the first switching device (9) connected to the “faster switch” output can be delayed.
Likewise, the second delay circuit (3) generating the “slower switch” output can be realized by way of changing the values of the resistor R1 and capacitor C2 so as to adjust the turn-on time of the transistor Q1 so that the turn-on time of the second switching device (10) connected to the “slower switch” output can be delayed. Therefore, the first and second delay circuits (2, 3) respectively delay turn-off of the first switching device (9) and turn-on of the second switching device (10).
According to the invention, a first delaying circuit (2) is connected between a gate driving circuit (8) and the first switching device (9) in the manner that the first delaying circuit (2) delays turn-off of the first switching device (9) and a second delaying circuit (3) is connected between the gate driving circuit (8) and the second switching device (10) in the manner that the second delaying circuit (3) delays turn-on of the second switching device (10).
In summary, the present invention proposes a switched-mode power converter (1) comprising a first switching device (9) connected electrically in parallel to a second switching device (10), the first and second switching devices (9 and 10) being driven by a gate driving circuit (8).
In one embodiment of the present invention, a first delaying circuit (2) is connected between the gate driving circuit (8) and the first switching device (9) in the manner that the first delaying circuit (2) delays turn-off of the first switching device (9) and a second delaying circuit (3) is connected between the gate driving circuit (8) and the second switching device (10) in the manner that the second delaying circuit (3) delays turn-on of the second switching device (10).
In a further embodiment of the present invention, the first switching device (9) has shorter turn-on and turn-off crossover intervals in comparison to the second switching device (10).
In a further embodiment of the present invention, a first turn-on circuit (4) provides that the first switching device (9) is biased to conduction and a first turn-off circuit (6) provides that the first switching device (9) is biased to non-conduction modes.
In a further embodiment of the present invention, a second turn-on circuit (5) provides that the second switching device (10) is biased to conduction and a second turn-off circuit (7) provides that the second switching device (10) is biased to non-conduction modes.
In a further embodiment of the present invention, the first switching device (9) with lower turn-on and turn-off power loss starts conducting prior to the second switching device (10) and by the time the second switching device (10) is turned on, the first switching device (9) conducts a greater proportion of the current being shared.
In a further embodiment of the present invention, the first switching device (9) continues to conduct current while the second switching device (9) is being turned off.
In a further embodiment of the present invention, transitions between conduction and non-conduction modes of the switched-mode power converter (1) is substantially effectuated by the first switching device (9).
The present invention therefore provides a switched-mode power converter (1) having parallel-coupled first and second switching devices (9, 10) operable so as to feature decreased switching and conduction losses. While the first switching device (9) provides lowering of the switching losses, the second switching device (10) is advantageous in lowering on-state losses.

Claims (7)

  1. A switched-mode power converter (1) comprising a first switching device (9) connected electrically in parallel to a second switching device (9), the first and second switching devices (9 and 10) being driven by a gate driving circuit (8), characterized in that
    a first delaying circuit (2) is connected between the gate driving circuit (8) and the first switching device (9) in the manner that the first delaying circuit (2) delays turn-off of the first switching device (9) and a second delaying circuit (3) is connected between the gate driving circuit (8) and the second switching device (10) in the manner that the second delaying circuit (3) delays turn-on of the second switching device (10).
  2. A switched-mode power converter (1) as in Claim 1, characterized in that the first switching device (9) has shorter turn-on and turn-off crossover intervals in comparison to the second switching device (10).
  3. A switched-mode power converter (1) as in Claim 1 or 2, characterized in that a first turn-on circuit (4) provides that the first switching device (9) is biased to conduction and a first turn-off circuit (6) provides that the first switching device (9) is biased to non-conduction modes.
  4. A switched-mode power converter (1) as in Claim 1 or 2, characterized in that a second turn-on circuit (5) provides that the second switching device (10) is biased to conduction and a second turn-off circuit (7) provides that the second switching device (10) is biased to non-conduction modes.
  5. A switched-mode power converter (1) as in Claim 2, characterized in that the first switching device (9) with lower turn-on power loss starts conducting prior to the second switching device (10) and by the time the second switching device (10) is turned on, the first switching device (9) conducts a greater proportion of the current being shared.
  6. A switched-mode power converter (1) as in Claim 2 or 5, characterized in that the first switching device (9) continues to conduct current while the second switching device (9) is being turned off.
  7. A switched-mode power converter (1) as in Claim 6, characterized in that transitions between conduction and non-conduction modes of the switched-mode power converter (1) is substantially effectuated by the first switching device (9).
PCT/EP2015/062481 2015-06-04 2015-06-04 Parallel-coupled switching devices and switch-mode power converter WO2016192799A1 (en)

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PCT/EP2015/062481 WO2016192799A1 (en) 2015-06-04 2015-06-04 Parallel-coupled switching devices and switch-mode power converter
TR2016/06371A TR201606371A2 (en) 2015-06-04 2016-05-13 Parallel Connected Switches and Switched Power Inverter

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108768144A (en) * 2018-05-25 2018-11-06 Tcl空调器(中山)有限公司 Driving circuit and electric power variable flow device
DE102022211207A1 (en) 2022-10-21 2024-05-02 Zf Friedrichshafen Ag Power electronics module and method for controlling

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Publication number Priority date Publication date Assignee Title
US4532443A (en) 1983-06-27 1985-07-30 Sundstrand Corporation Parallel MOSFET power switch circuit
EP0581016A1 (en) * 1992-06-26 1994-02-02 Kollmorgen Corporation Apparatus and method for forced sharing of parallel MOSFET switching losses
US20080265851A1 (en) * 2007-04-24 2008-10-30 Jason Zhang Power switch-mode circuit with devices of different threshold voltages
EP2117121A1 (en) * 2008-05-06 2009-11-11 Schleifring und Apparatebau GmbH Semiconductor power switch
WO2015022860A1 (en) * 2013-08-12 2015-02-19 日産自動車株式会社 Switching device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532443A (en) 1983-06-27 1985-07-30 Sundstrand Corporation Parallel MOSFET power switch circuit
EP0581016A1 (en) * 1992-06-26 1994-02-02 Kollmorgen Corporation Apparatus and method for forced sharing of parallel MOSFET switching losses
US20080265851A1 (en) * 2007-04-24 2008-10-30 Jason Zhang Power switch-mode circuit with devices of different threshold voltages
EP2117121A1 (en) * 2008-05-06 2009-11-11 Schleifring und Apparatebau GmbH Semiconductor power switch
WO2015022860A1 (en) * 2013-08-12 2015-02-19 日産自動車株式会社 Switching device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108768144A (en) * 2018-05-25 2018-11-06 Tcl空调器(中山)有限公司 Driving circuit and electric power variable flow device
DE102022211207A1 (en) 2022-10-21 2024-05-02 Zf Friedrichshafen Ag Power electronics module and method for controlling

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