TWI504119B - Apparatus and method for avoiding conduction of parasitic devices - Google Patents

Description

Device for preventing parasitic element conduction and method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an apparatus and method for preventing parasitic elements from being turned on, and more particularly to an apparatus and method for applying a voltage conversion circuit to prevent parasitic elements of a power switch from being turned on.

A switching power converting circuit is a type of voltage converting circuit that adjusts the energy stored in a storage inductor to supply an output load and converts an input voltage into an output by switching a power switch. The voltage is at an output to maintain a fixed output voltage value and to provide the load current required for the output load. The advantage is that the conversion efficiency is high, so that unnecessary heat generation can be reduced, thereby reducing the complexity of the heat dissipation design.

Figure 1 is an output stage 100 of a conventional voltage conversion circuit in the form of a buck switching power supply conversion circuit. The output stage 100 utilizes switching of the switching element 150 and the switching element 130 to adjust the energy stored on the storage inductor 110 to convert an input voltage source 170 to an output voltage value and provide an output current. The switching element 150 and the channel of the switching element 130 are connected in series and coupled between the input voltage source 170 and another voltage reference point. For example, another voltage reference point in FIG. 1 is the ground terminal 180. The connection point 140 of the switching element 150 and the switching element 130 is coupled to the energy storage inductor 110. In actual operation, the channels of the switching element 150 and the switching element 130 are not turned on at the same time, otherwise an unnecessary waste of shoot-through current will be generated between the input voltage source 170 and the ground terminal 180. Not only the conversion efficiency is lowered, but the switching element 150 and the switching element 130 may even be burnt due to the conduction of a large current. Therefore, in terms of control, it is necessary to ensure that the channel of the switching element 150 is turned on and then the channel of the switching element 130 is turned on. However, since the channel of the switching element 130 is turned on immediately after the channel of the switching element 150 is turned off in actual control, there is a dead time at which the channel of the switching element 150 and the switching element 130 are simultaneously turned off. At this time, the output current flows through the switching element 150 or the parasitic element of the switching element 130 to form a current back. road.

As shown in FIG. 1, when the output current flows through the storage inductor 110 in the direction of the current path 136 or the current path 137, when the channels of the switching element 150 and the switching element 130 are simultaneously turned off, the output current is utilized by the switching element 130. A parasitic element such as a parasitic diode 131 or a parasitic transistor 132 forms a current loop. The switching element 130 in FIG. 1 is an N-type metal-oxide-semiconductor-field-effect-transistor (MOSFET) device. In application, the base 135 of the P-type of the switching element 130 is connected to the source, and a parasitic diode 131 is formed between the base end and the drain, and is in no-load. The time is turned on to form a portion of the current path 136. In addition, when the switching element 130 is a component applied to a high voltage, a separate P-well is formed in the process by using a barrier layer as a P-type of the switching element 130. The extreme 135, at this time, represents the parasitic transistor 132 of the barrier layer end 134, the base terminal 135 and the drain of the barrier layer contact, and is turned on at the dead time to form a portion of the current path 137.

However, in general applications, whether the parasitic diode 131 is turned on to form the current path 136, or the parasitic transistor 132 is turned on to form the current path 137, the power loss is greater than the current path formed by the channel that turns on the switching element 130. This is because the forward-biasing voltage generated by the PN junction of the semiconductor is greater than the voltage across the channel of the switching element 130. In addition, when the switching element 130 is integrated in an integrated circuit, the parasitic diode 131 or the conducting electrode of the parasitic transistor 132 may form a current conducting path in the substrate, resulting in a pair. The current noise of the adjacent components interferes, and in severe cases, even the adjacent components are not working properly. Therefore, in design, it is only necessary to reduce the conduction time of the parasitic element under the premise that the penetration current does not occur, that is, reduce the dead time, to optimize the conversion efficiency, and avoid the above-mentioned possible problems. However, since the switching element 130 has a certain size, that is, its control terminal has a parasitic capacitance of a certain size, the parasitic capacitance of the current-stage driving switching element 130 must be charged when the control terminal of the switching element 130 is turned on or off. Or the action of discharging causes the switching element 130 to fail to react immediately to turn on or off the channel. In addition, considering the parameter variation range of the component, the operating temperature range, and the operating voltage variation range, etc., and finally compromised in design, the conventional voltage conversion circuit still has a certain amount of dead time in operation, and Unable to achieve design optimization.

In addition, when the channel of the switching element 130 is to be turned off and then the channel of the switching element 150 is turned on, it is also necessary to consider reducing the dead time. Therefore, the operation tends to control the channel of the switching element 150 as soon as the channel of the switching element 130 is turned off. . At this time, the voltage at the connection point 140 starts to rise, but at the same time, the control terminal of the switching element 130 often does not reach the voltage of the destination, but at a voltage threshold of a channel that can just turn off the switching element 130. At this time, due to the coupling of the voltage change of the connection point 140, the voltage of the control terminal of the switching element 130 is increased, causing the channel of the switching element 130 to be turned on again, and a penetration current is generated. The solution to this phenomenon is still to increase the dead time or to reduce the voltage rise of the connection point 140. However, these methods still cause an increase in the on-time of the parasitic element, which causes the aforementioned possible problems.

In view of the above problems, the present invention provides an apparatus for preventing conduction of a parasitic element and a method thereof, which are suitable for use in a voltage conversion circuit for preventing conduction of a parasitic element of a power switch.

The invention provides a device for preventing conduction of a parasitic element, which is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on. The voltage conversion circuit regulates the energy stored on the energy storage inductor to supply to the output load and converts the input voltage to an output voltage at the output. Devices that prevent parasitic elements from conducting include a lower bridge power switch and a power switch drive stage.

The lower bridge power switch has a first lower bridge power switch and a second lower bridge power switch, and the channel of the lower bridge power switch is formed by connecting the channel of the first lower bridge power switch and the channel of the second lower bridge power switch in parallel. The conduction equivalent impedance of the channel of the first lower bridge power switch is greater than the conduction equivalent impedance of the channel of the second lower bridge power switch, and one end of the channel of the lower bridge power switch is coupled to the energy storage inductor. The power switch driving stages are respectively coupled to the control end of the first lower bridge power switch and the control end of the second lower bridge power switch for controlling the channel of turning on or off the power switch of the lower bridge.

Wherein, when the power switch driver stage controls the channel of the lower bridge power switch, the channel of the first lower bridge power switch is first turned on and then the channel of the second lower bridge power switch is turned on, and when the power switch driver stage controls the off-bridge power When the channel of the switch is turned off, the channel of the second lower bridge power switch is turned off first and then the second Next to the channel of the bridge power switch.

The invention further proposes a method for preventing the parasitic element from being turned on, which is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on. The method includes the steps of first determining whether the power switch driver stage is signaling to turn on the lower bridge power switch, and if so, proceeding to the next step. Then, the first lower bridge power switch is turned on first, and then the second lower bridge power switch is turned on. Then it is judged whether the power switch drive stage sends a signal to turn off the lower bridge power switch, and if so, the next step is performed. Finally, the second lower bridge power switch is turned off, then the first lower bridge power switch is turned off, and the step of determining whether the power switch driver stage sends a signal to turn on the lower bridge power switch is returned.

The invention further provides a method for preventing the parasitic element from being turned on, which is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on. The method comprises the following steps: first determining whether the power switch driver stage emits a signal to turn on the lower bridge power switch. If yes, proceed to the next step. Then turn off the second upper bridge power switch, then turn off the first upper bridge power switch. Then, the first lower bridge power switch is turned on first, and then the second lower bridge power switch is turned on. Next, it is determined whether the power switch drive stage sends a signal to turn on the upper bridge power switch, and if so, proceeds to the next step. Then, the second lower bridge power switch is turned off first, and then the first lower bridge power switch is turned off. Finally, the first upper bridge power switch is turned on, then the second upper bridge power switch is turned on, and the step of determining whether the power switch driver stage sends a signal to turn on the lower bridge power switch is returned.

The invention has the advantages that the device for preventing parasitic element conduction and the method thereof disclosed in the invention can effectively reduce the operation dead time of the applied voltage conversion circuit to prevent the parasitic component of the power switch from being turned on, and At the same time, the occurrence of the penetration current is avoided, thereby increasing the conversion efficiency of the voltage conversion circuit and reducing the current noise in the substrate.

The features, implementations, and utilities of the present invention are described in detail below with reference to the drawings.

100‧‧‧Output

110, 210, 310, 410, 510, 610, 710, 810 ‧ ‧ energy storage inductance

130, 150‧‧‧Switching elements

131‧‧‧ Parasitic diode

132‧‧‧ Parasitic crystal

134‧‧ ‧ barrier end

135‧‧ ‧ base extreme

136, 137, 670, 715, 815‧‧‧ current paths

140, 260, 360, 490, 595, 690, 735, 835 ‧ ‧ connection points

170‧‧‧Input voltage source

180‧‧‧ Grounding terminal

200, 300, 400, 500, 600, 700, 800‧‧‧ Devices for preventing parasitic components from conducting

220, 420, 520, 620, 720, 820‧‧‧ first lower bridge power switch

230, 430, 530, 630, 730, 830‧‧‧ second lower bridge power switch

240, 340, 440, 540, 640, 740, 840‧‧‧ power switch driver stage

250, 350, 460, 560, 660, 760, 860‧‧‧ voltage conversion circuits

320‧‧‧First power switch

330‧‧‧second power switch

370, 470, 770, 870 ‧ ‧ inputs

380, 480, 780, 880‧‧‧ output

450‧‧‧Upper bridge power switch

550, 750, 850‧‧‧Second upper bridge power switch

590, 790, 890‧‧‧ first upper bridge power switch

641, 741‧‧‧ first lower bridge voltage end

642, 742‧‧‧ second lower bridge voltage end

643, 743, 843‧‧‧ first transistor

644, 744, 844‧‧‧second transistor

645, 745, 845‧‧‧ third transistor

646, 746, 846‧‧‧ transmission gate

647, 747, 847‧‧‧ fourth transistor

648, 748, 848‧‧‧ reverse brake

649, 749, 849‧‧‧ first lower bridge driver stage

650, 751, 851‧‧‧ second lower bridge driver stage

651, 752, 852‧‧‧ power switch control circuit

753, 853‧‧‧ first upper bridge driver stage

754, 854‧‧‧Second upper bridge driver stage

755, 757, 855, 857‧‧‧ lower bridge to upper bridge level regulator

756, 856‧‧‧Upper Bridge to Lower Bridge Level Regulator

841‧‧‧First upper bridge voltage terminal

842‧‧‧Second upper bridge voltage terminal

Figure 1 is an output stage of a voltage conversion circuit of a conventional buck switching power supply conversion circuit.

Fig. 2 is a view showing the apparatus for preventing the conduction of a parasitic element according to the first embodiment of the present invention.

Figure 3 is a view of the second embodiment of the present invention for preventing the parasitic element from being turned on.

Fig. 4 is a view showing a device for preventing conduction of a parasitic element according to a third embodiment of the present invention.

Fig. 5 is a view showing a device for preventing conduction of a parasitic element according to a fourth embodiment of the present invention.

Figure 6 is a view of the fifth embodiment of the present invention for preventing the parasitic element from being turned on.

Figure 7 is a diagram of a sixth embodiment of the present invention for preventing parasitic elements from being turned on.

Figure 8 is a diagram of a seventh embodiment of the present invention for preventing parasitic elements from being turned on.

Figure 9 is a flow chart showing the steps of the method for preventing the conduction of parasitic elements in the eighth embodiment of the present invention.

FIG. 10 is a flow chart showing the steps of a method for preventing conduction of a parasitic element according to a ninth embodiment of the present invention.

FIG. 11 is a flow chart showing the steps of a method for preventing conduction of a parasitic element according to a tenth embodiment of the present invention.

Figure 12 is a flow chart showing the steps of the method for preventing the conduction of parasitic elements in the eleventh embodiment of the present invention.

Figure 13 is a flow chart showing the steps of a method for preventing conduction of a parasitic element according to a twelfth embodiment of the present invention.

In the context of the specification and subsequent patent applications, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

2 is a first embodiment of the present invention, and is a device 200 for preventing parasitic elements from being turned on. The device 200 for preventing the parasitic element from being turned on is applied to the voltage conversion circuit 250 to prevent the parasitic element of the power switch from being turned on. The voltage conversion circuit 250 adjusts the energy stored on the storage inductor 210 to be supplied to the output load, and converts an input voltage into an output voltage at an output. The apparatus 200 for preventing parasitic elements from turning on includes a lower bridge power switch and a power switch drive stage 240.

As shown in FIG. 2, the lower bridge power switch has a first lower bridge power switch 220 and a second lower bridge power switch 230, and the channel of the lower bridge power switch is a channel of the first lower bridge power switch 220 and a second lower bridge. The channel 230 of the power switch is formed in parallel, wherein the conductive equivalent impedance of the channel of the first lower bridge power switch 220 is greater than the conductive equivalent impedance of the channel of the second lower bridge power switch 230, and one end of the channel of the lower bridge power switch is stored The inductor 210 is coupled to the connection point 260. The power switch driver stage 240 is coupled to the control end of the first lower bridge power switch 220 and the control end of the second lower bridge power switch 230 for controlling the channel of turning on or off the power switch of the lower bridge.

As shown in FIG. 2, when the power switch driver stage 240 controls the channel of the lower bridge power switch, the channel of the first lower bridge power switch 220 is turned on, and then the channel of the second lower bridge power switch 230 is turned on. When the power switch driver stage 240 controls the channel of the lower bridge power switch, the channel of the second lower bridge power switch 230 is turned off first, and then the channel of the first lower bridge power switch 220 is turned off.

Further, in the prior art, the power-off relationship of the lower bridge is realized by a single component, and has a certain component size. Therefore, when the current stage drives the parasitic capacitance of the control terminal to perform the channel conduction or cut-off operation, the lower bridge power The switch does not react immediately, so the parasitic element of the power switch conducts to form a current loop. However, in the installation to prevent parasitic components from being turned on In the setting 200, since the conduction equivalent impedance of the channel of the first lower bridge power switch 220 is greater than the conduction equivalent impedance of the channel of the second lower bridge power switch 230, the first lower bridge power switch 220 has a smaller component size. That is, the control end of the first lower bridge power switch 220 has a small parasitic capacitance, and the reaction speed in operation can also be relatively fast. Therefore, if the channel of the lower bridge power switch is to be turned on, the power switch driver stage 240 first sends a control signal to conduct the channel of the first lower bridge power switch 220, so as to turn on the first step before the parasitic component of the lower bridge power switch is turned on. The channel of the bridge power switch 220 increases the conversion efficiency of the voltage conversion circuit and avoids causing unnecessary current noise in the substrate. It is worth noting that, considering the maximum current on the conduction specification, the voltage across the maximum current of the channel of the first lower bridge power switch 220 is designed to be smaller than the forward bias of the parasitic element, otherwise at the maximum current. In this case, the parasitic element may still be turned on.

In addition, when the power switch driving stage 240 controls the channel of the lower bridge power switch, the channel of the second lower bridge power switch 230 is turned off, and then the channel of the first lower bridge power switch 220 is turned off. Since the voltage state of the connection point 260 changes, it occurs after the channel of the lower bridge power switch is turned off, that is, after the channel of the first lower bridge power switch 220 is turned off. At this time, since the channel of the second lower bridge power switch 230 has been cut off first, that is, the voltage of the control terminal of the second lower bridge power switch 230 is reacted one step earlier, the voltage of the control terminal is turned on to turn on the second lower bridge power switch 230. One of the channel voltage thresholds is far away, so it is not easily coupled by the voltage change of the connection point 260 to cause the channel of the second lower bridge power switch 230 to be turned on to form a penetration current. On the one hand, the first lower bridge power switch 220 has a faster response speed, that is, it can cut off its channel more quickly, and is less susceptible to the voltage state change of the connection point 260.

Figure 3 is a second embodiment of the present invention, which is an apparatus 300 for preventing parasitic elements from being turned on. The device 300 for preventing the parasitic element from being turned on is an embodiment of the device 200 for preventing parasitic element conduction shown in FIG. 2, and is applied to the voltage conversion circuit 350 for preventing the parasitic element of the power switch from being turned on. The voltage conversion circuit 350 is a step-up switching power converter, which adjusts the energy stored in the energy storage inductor 310 to be supplied to the output load, and converts the input voltage of the input terminal 370 into an output voltage at an output end. 380. The apparatus 300 for preventing parasitic elements from turning on includes a power switch and a power switch drive stage 340, wherein the power switch further includes a first power switch 320 and a second power switch 330. The operation of the first power switch 320, the second power switch 330, and the power switch driver stage 340 can be referred to the description of FIG. In addition, the first power switch 320 and the second power switch 330 may be P-type metal oxide semiconductor field effect transistors or PNPs. Type of bipolar junction transistor.

Further, since the conductive equivalent impedance of the channel of the first power switch 320 is greater than the conductive equivalent impedance of the channel of the second power switch 330, the first power switch 320 has a smaller component size, that is, the first power switch 320. The control terminal has a small parasitic capacitance, and the reaction speed in operation can also be relatively fast. Therefore, if the channel of the power switch is to be turned on, the power switch driver stage 340 first sends a control signal to turn on the channel of the first power switch 320, so as to turn on the channel of the first power switch 320 before the parasitic component of the power switch reacts to conduct. To increase the conversion efficiency of the voltage conversion circuit and to avoid causing unnecessary current noise in the substrate. After that, the channel of the second power switch 330 is further turned on to further reduce the on-resistance equivalent impedance of the channel and increase the conversion efficiency. It is worth noting that, considering the maximum current on the conduction specification, the voltage across the maximum current of the channel of the first power switch 320 is designed to be less than the forward bias of the parasitic element, otherwise the maximum current is present. Underneath, it is still possible to cause conduction of parasitic elements.

In addition, when the power switch driving stage 340 controls the channel of the cutoff power switch, the channel of the second power switch 330 is turned off first, and then the channel of the first power switch 320 is turned off. Since the point at which the voltage at the connection point 360 begins to drop occurs after the channel of the power switch is turned off, that is, after the channel of the first power switch 320 is turned off. At this time, since the channel of the second power switch 330 has been turned off first, that is, the voltage of the control terminal of the second power switch 330 is reacted one step earlier, the voltage of the control terminal is turned on to turn on the voltage threshold of one of the channels of the second power switch 330. It is far away, so it is not easy to be coupled by the voltage change of the connection point 360 to cause the channel of the second power switch 330 to be turned on again to form a penetration current. On the one hand, the first power switch 320 has a faster response speed, that is, it can cut off its channel more quickly, and is less susceptible to voltage changes at the connection point 360.

Figure 4 is a third embodiment of the present invention, which is a device 400 for preventing parasitic elements from being turned on. The device 400 for preventing the parasitic element from being turned on is another embodiment of the apparatus 200 for preventing parasitic element conduction shown in FIG. 2, and is applied to the voltage conversion circuit 460 for preventing the parasitic element of the power switch from being turned on. The voltage conversion circuit 460 is a buck switching power converter, which adjusts the energy stored in the energy storage inductor 410 to be supplied to the output load, and converts the input voltage of the input terminal 470 into an output voltage at an output end. 480. The apparatus 400 for preventing parasitic elements from turning on includes an upper bridge power switch 450, a lower bridge power switch, and a power switch drive stage 440. The lower bridge power switch further includes a first lower bridge power switch 420 and a second lower bridge power switch 430. The operation of the first lower bridge power switch 420, the second lower bridge power switch 430, and the power switch drive stage 440 can be referred to the description of FIG. In addition, the first lower bridge power switch 420 and the second lower bridge power switch 430 may be an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor.

Further, since the conduction equivalent impedance of the channel of the first lower bridge power switch 420 is greater than the conduction equivalent impedance of the channel of the second lower bridge power switch 430, the first lower bridge power switch 420 has a smaller component size, That is, the control end of the first lower bridge power switch 420 has a small parasitic capacitance, and the reaction speed in operation can also be relatively fast. Therefore, if the channel of the upper bridge power switch 450 is to be turned off and then the channel of the lower bridge power switch is turned on, the power switch driver stage 440 first sends a control signal to conduct the channel of the first lower bridge power switch 420, in order to parasitize the power switch of the lower bridge. Before the component reacts, the channel of the first lower bridge power switch 420 is turned on to increase the conversion efficiency of the voltage conversion circuit and avoid unnecessary current noise in the substrate. After that, the channel of the second lower bridge power switch 430 is further turned on to further reduce the conduction equivalent impedance of the channel and increase the conversion efficiency. It is worth noting that, considering the maximum current on the conduction specification, the voltage across the maximum current of the channel of the first lower-bridge power switch 420 is designed to be smaller than the forward bias of the parasitic element, otherwise at the maximum current. In this case, the parasitic element may still be turned on.

In addition, when the power switch driving stage 440 controls the channel of the lower bridge power switch and then turns on the channel of the upper bridge power switch, the channel of the second lower bridge power switch 430 is turned off first, and then the first lower bridge power switch 420 is turned off. aisle. Since the voltage at the connection point 490 begins to rise, it occurs after the channel of the lower bridge power switch is turned off, that is, after the channel of the first lower bridge power switch 420 is turned off. At this time, since the channel of the second lower bridge power switch 430 has been cut off first, that is, the voltage of the control terminal of the second lower bridge power switch 430 is reacted one step earlier, the voltage of the control terminal is turned on to turn on the second lower bridge power switch 430. One of the channel voltage thresholds is far away, so it is not easily coupled by the voltage change of the connection point 490 to cause the channel of the second lower bridge power switch 430 to be turned on to form a penetration current. On the one hand, the first lower bridge power switch 420 has a faster response speed, that is, it can cut off its channel more quickly, and is less susceptible to voltage changes at the connection point 360.

Figure 5 is a fourth embodiment of the present invention, which is a method for preventing parasitic A device 500 in which the component is turned on. The difference between the device 500 for preventing parasitic element conduction and the device 400 for preventing parasitic element conduction shown in FIG. 4 is that the bridge power switch of the parasitic element conduction device 500 further includes a first upper bridge power switch 590 and a second Upper bridge power switch 550. The channel of the upper bridge power switch is formed by the channel of the first upper bridge power switch 590 and the channel of the second upper bridge power switch 550, and the conduction equivalent impedance of the channel of the first upper bridge power switch 590 is greater than the second upper bridge power. The channel of the switch 550 has an equivalent impedance, and one end of the channel of the upper bridge power switch is coupled to the channel of the lower bridge power switch and the connection point 595 of the energy storage inductor 510, wherein the power switch driver stage 540 is coupled to the first The control terminal of the upper bridge power switch 590 and the control terminal of the second upper bridge power switch 550, and when the power switch drive stage 540 controls the channel of the upper bridge power switch, the channel of the first upper bridge power switch 590 is first turned on. The second upper bridge power switch 550 is turned on again, and when the power switch driving stage 540 turns off the upper bridge power switch, the channel of the second upper bridge power switch 550 is first turned off and then the channel of the first upper bridge power switch 550 is turned off. The operation of the first lower bridge power switch 520, the second lower bridge power switch 530, and the power switch drive stage 540 can be referred to the description of FIG. In addition, the first upper bridge power switch 590 and the second upper bridge power switch 550 may be a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor.

Further, since the conduction equivalent impedance of the channel of the first upper bridge power switch 590 is greater than the conduction equivalent impedance of the channel of the second upper bridge power switch 550, the first upper bridge power switch 590 has a smaller component size, That is, the control end of the first upper bridge power switch 590 has a small parasitic capacitance, and the reaction speed in operation can also be relatively fast. Therefore, if the channel of the power switch of the lower bridge is to be turned off and then the channel of the power switch of the upper bridge is turned on, the power switch driver stage 540 first sends a control signal to conduct the channel of the first upper bridge power switch 590, in order to parasitize the power switch of the upper bridge. Before the component reacts, the channel of the first upper bridge power switch 590 is turned on to increase the conversion efficiency of the voltage conversion circuit and avoid unnecessary current noise in the substrate. After that, the channel of the second upper bridge power switch 550 is further turned on to further reduce the on-resistance equivalent impedance of the channel and increase the conversion efficiency. It is worth noting that, considering the maximum current in the conduction specification, the voltage across the maximum current of the channel of the first upper bridge power switch 590 is designed to be smaller than the forward bias of the parasitic element, otherwise at the maximum current. In this case, the parasitic element may still be turned on.

In addition, when the power switch driving stage 540 controls the channel of the upper bridge power switch to be turned off and then turns on the channel of the lower bridge power switch, the second upper bridge power switch 550 is turned off first. The channel then cuts off the channel of the first upper bridge power switch 590. Since the voltage at the connection point 595 begins to drop, it occurs after the channel of the upper bridge power switch is turned off, that is, after the channel of the first upper bridge power switch 590 is turned off. At this time, since the channel of the second upper bridge power switch 550 has been first cut off, that is, the voltage of the control terminal of the second upper bridge power switch 550 is reacted one step earlier, the voltage of the control terminal is turned on to turn on the second upper bridge power switch 590. One of the channel voltage thresholds is far away, so it is not easily coupled by the voltage change of the connection point 595 to cause the channel of the second upper bridge power switch 550 to be turned on to form a penetration current. On the one hand, the first upper bridge power switch 590 has a faster response speed, that is, it can cut off its channel more quickly, and is less susceptible to the voltage change of the connection point 595.

Figure 6 is a fifth embodiment of the present invention, which is a device 600 for preventing parasitic elements from being turned on. The apparatus 600 for preventing the parasitic element from being turned on is an embodiment of the apparatus 200 for preventing parasitic element conduction shown in FIG. 2, and is applied to the voltage conversion circuit 660 for preventing the parasitic element of the power switch from being turned on. The device 600 for preventing parasitic element conduction includes a lower bridge power switch and a power switch drive stage 640, wherein the lower bridge power switch further includes a first lower bridge power switch 620 and a second lower bridge power switch 630, which may be N-type metal oxide The semiconductor field effect transistor or the NPN type bipolar junction transistor. The power switch driver stage 640 further includes a first lower bridge voltage terminal 641, a second lower bridge voltage terminal 642, a first transistor 643, a second transistor 644, a third transistor 645, a transmission gate 646, a fourth transistor 647. An inverting gate 648, a first lower bridge driver stage 649, a second lower bridge driver stage 650, and a power switch control circuit 651.

As shown in FIG. 6, the first lower bridge voltage terminal 641 has a first lower bridge voltage. The second lower bridge voltage terminal 642 has a second lower bridge voltage and the second lower bridge voltage is less than the first lower bridge voltage. The first transistor 643 is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor. The channel of the first transistor 643 is coupled to the first lower bridge voltage terminal 641 and the first lower bridge power. Between the control terminals of the switch 620. The second transistor 644 is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, and the channel of the second transistor 644 is coupled to the second lower bridge voltage terminal 642 and the first lower bridge power. Between the control terminals of the switch 620. The third transistor 645 is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, and the channel of the third transistor 645 is coupled to the first lower bridge voltage terminal 641 and the first transistor 643. Between the gate or the base.

As shown in FIG. 6, one end of the channel of the transmission gate 646 is coupled to the first transistor. The gate or the base of the gate 643 is coupled to the gate or the base of the third transistor 645, and the inverting control terminal of the transfer gate 646 is coupled to the gate of the second transistor 644. Or base. The fourth transistor 647 is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, and the channel of the fourth transistor 647 is coupled to the other end of the channel of the transmission gate 646 and the lower bridge power switch. Between one end of the channel, the gate or base of the fourth transistor 647 is coupled to the gate or base of the third transistor 645. The input end of the inverting gate 648 is coupled to the gate or the base of the fourth transistor 647, and the output end of the inverting gate 648 is coupled to the inverting control terminal of the transmission gate 646.

As shown in FIG. 6, the first lower bridge driver stage 649 has a first input terminal, a second input terminal, and an output terminal. The output terminal of the first lower bridge driver stage 649 is coupled to the input terminal 648 of the inverting gate. When the signal received by the first input of the first lower bridge driver stage 649 has a negative edge, the output of the first lower bridge driver stage 649 outputs a second lower bridge voltage, when the second input of the first lower bridge driver stage 649 When the received signal has a positive edge, the output of the first lower bridge driver stage 649 outputs the first lower bridge voltage. The second lower bridge driver stage 650 has a first input end, a second input end, and an output end. The output end of the second lower bridge drive stage 650 is coupled to the control end of the second lower bridge power switch 630 and the first lower bridge drive. a first input end of the second stage 649, the second input end of the second lower bridge driving stage 650 is coupled to the control end of the first lower bridge power switch 620, and the first input end of the second lower bridge driving stage 650 and the second When the input terminal is simultaneously the first lower bridge voltage, the output of the second lower bridge driver stage 650 outputs the first lower bridge voltage, otherwise the output terminal of the second lower bridge driver stage 650 outputs the second lower bridge voltage. The power switch control circuit 651 has an output coupled to the second input of the first lower bridge driver stage 649 and a first input of the second lower bridge driver stage 650 for outputting the first lower bridge voltage or the second The bridge voltage is used to control the turn-on or turn-off of the channel of the lower bridge power switch.

Further, the power switch driver stage 640 is applied when the voltage conversion circuit 660 is at no load time, and the current of the energy storage inductor 610 is shown as the direction of the current path 670. At this point, the voltage at junction 690 gradually decreases and tends to turn on the parasitic components of the lower bridge power switch. At this time, the output end of the power switch control circuit 651 is converted from the second lower bridge voltage to the first lower bridge voltage to generate a positive edge, and the output end of the first lower bridge drive stage 649 is reacted to output the first lower bridge voltage. The channel of the third transistor 645 and the second transistor 644 is turned off, and the transfer gate 646 is turned on. Since the gate or the base of the fourth transistor 647 is the first lower bridge voltage at this time, when the voltage of the connection point 690 drops to a certain value, the channel of the fourth transistor 647 is turned on and the connection point 690 is The voltage is coupled to the gate or the base of the first transistor 643, and the first transistor 643 is turned on. The channel is such that the control end of the first lower bridge power switch 620 is coupled to the first lower bridge voltage and turns on the channel of the first lower bridge power switch 620. It should be noted that since the connection voltage 690 is at a higher voltage, the high voltage may exceed the range that the transfer gate 646 can tolerate, and thus the fourth transistor 647 may be a P-type laterally diffused metal oxide semiconductor. , LDMOS) for isolating the high voltage and other components of the power switch driver stage 640 and is compatible with the high voltage.

Then, at this time, since the first input terminal and the second input terminal of the second lower bridge driving stage 650 are simultaneously the first lower bridge voltage, the output end of the second lower bridge driving stage 650 outputs the first lower bridge voltage, and The channel of the second lower bridge power switch 630 is turned on. At this point, the lower bridge power switch completes the conduction procedure of its channel. It can be seen from the above description that one of the functions of the power switch driving stage 640 is that the voltage state of the connection point 690 can be detected, thereby controlling the channel for turning on the power switch of the lower bridge, and realizing the channel of the first lower bridge power switch 620. The spirit of the invention of the passage of the second lower bridge power switch 630 is again turned on.

When the channel of the power switch of the lower bridge is to be cut off, the output end of the power switch control circuit 651 is converted from the first lower bridge voltage to the second lower bridge voltage, and the output end of the second lower bridge drive stage 650 is reacted. The lower bridge voltage transitions to the second lower bridge voltage to turn off the channel of the second lower bridge power switch 630, and the negative edge of the output end of the second lower bridge driver stage 650 and reacts to the first lower bridge driver stage 649 At one input, the output of the first lower bridge driver stage 649 reflects the output of the second lower bridge voltage, turns on the channels of the third transistor 645 and the second transistor 644, and turns off the transfer gate 646. The gate or base of the first transistor 643 is coupled to the first lower bridge voltage through the channel of the third transistor 645 to turn off the channel of the first transistor 643. At this time, the control end of the first lower bridge power switch 620 is coupled to the second lower bridge voltage through the channel of the second transistor 644, and the channel of the first lower bridge power switch 620 is turned off. As can be seen from the above description, the power switch driver stage 640 also implements the spirit of the present invention in which the channel of the second lower bridge power switch 630 is turned off first, and then the channel of the first lower bridge power switch 620 is turned off.

Figure 7 is a sixth embodiment of the present invention, which is a device 700 for preventing parasitic elements from being turned on. The apparatus 700 for preventing the parasitic element from being turned on is an embodiment of the apparatus 500 for preventing parasitic element conduction shown in FIG. 5, and is applied to the voltage conversion circuit 760 for preventing the parasitic element of the power switch from being turned on. The voltage conversion circuit 760 is a buck switching power converter, which adjusts the energy stored in the energy storage inductor 710 to be supplied to the output load, and converts the input voltage of the input terminal 770 into an output voltage at an output end. 780. Prevent parasitic components from turning on Apparatus 700 includes an upper bridge power switch, a lower bridge power switch, and a power switch drive stage 740. The upper bridge power switch further includes a first upper bridge power switch 790 and a second upper bridge power switch 750, which may be a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor. The lower bridge power switch further includes a first lower bridge power switch 720 and a second lower bridge power switch 730, which may be an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor. The power switch driver stage 740 further includes a first lower bridge voltage terminal 741, a second lower bridge voltage terminal 742, a first transistor 743, a second transistor 744, a third transistor 745, a transmission gate 746, and a fourth transistor 747. The inverting gate 748, the first lower bridge driving stage 749, the second lower bridge driving stage 751, the first upper bridge driving stage 753, the second upper bridge driving stage 754, the power switch control circuit 752, and the lower bridge upper bridge The bit regulators 755, 757 and the upper bridge to the lower rail level regulator 756.

As shown in FIG. 7, the first lower bridge voltage terminal 741, the second lower bridge voltage terminal 742, the first transistor 743, the second transistor 744, the third transistor 745, the transmission gate 746, and the fourth transistor are shown. For the functions of the 747, the inverting gate 748, the first lower bridge power switch 720, and the second lower bridge power switch 730, and the connection relationship between them, please refer directly to the relevant description of the corresponding components in FIG. The first lower bridge driver stage 749 has a first input end, a second input end, and an output end. The output end of the first lower bridge drive stage 749 is coupled to the input end of the inverting gate 748, and the first lower bridge driver stage 749 The first input end is coupled to the control end of the second lower bridge power switch 730, and the second input end of the first lower bridge drive stage 749 is coupled to the first upper bridge power switch through the upper bridge to the lower bridge level regulator 756. At the control end of the 790, when the signal received by the first input of the first lower bridge driver stage 749 has a negative edge, the output of the first lower bridge driver stage 749 outputs a second lower bridge voltage, when the first lower bridge driver stage When the signal received by the second input of 749 has a positive edge, the output of the first lower bridge driver stage 749 outputs the first lower bridge voltage. The second lower bridge driving stage 751 has a first input end, a second input end, and an output end. The output end of the second lower bridge driving stage 751 is coupled to the control end of the second lower bridge power switch 730, and the second lower bridge is driven. The second input end of the stage 751 is coupled to the control end of the first lower bridge power switch 720. When the first input end and the second input end of the second lower bridge drive stage 751 are simultaneously the first lower bridge voltage, the second The output of the lower bridge driver stage 751 outputs a first lower bridge voltage, otherwise the output of the second lower bridge driver stage 751 outputs a second lower bridge voltage.

As shown in FIG. 7, the first upper bridge driver stage 753 has a first input terminal, a second input terminal, and an output terminal. The output end of the first upper bridge driver stage 753 is coupled to the control of the first upper bridge power switch 790. The first input end of the first upper bridge driver stage 753 passes through the lower bridge to the upper bridge The node 755 is coupled to the control end of the first lower bridge power switch 720, and the second input end of the first upper bridge driver stage 753 is coupled to the control end of the second upper bridge power switch 750, when the first upper bridge driver stage When the signal received by the first input of the 753 has a negative edge, the output of the first upper bridge driver stage 753 outputs a second upper bridge voltage, and the signal received by the second input of the first upper bridge driver stage 753 occurs positively. At the edge, the output of the first upper bridge driver stage 753 outputs a first upper bridge voltage, and the second upper bridge voltage is less than the first upper bridge voltage. The second upper bridge driving stage 754 has a first input end, a second input end, and an output end. The output end of the second upper bridge driving stage 754 is coupled to the control end of the second upper bridge power switch 750, and the second upper bridge is driven. The first input end of the stage 754 is coupled to the control end of the first upper bridge power switch 790, and when the first input end and the second input end of the second upper bridge drive stage 754 are the first upper bridge voltage The output of the second upper bridge driver stage 754 outputs a first upper bridge voltage, otherwise the output of the second upper bridge driver stage 754 outputs a second upper bridge voltage. The power switch control circuit 752 has an output coupled to the first input of the second lower bridge driver stage 751. The output of the power switch control circuit 752 is coupled to the second bridge through the lower bridge. The second input of the upper bridge driver stage 754 is used to control the on or off of the channel of the upper bridge power switch and the lower bridge power switch.

As shown in Fig. 7, the lower bridge pair upper bridge level adjusters 755, 757 and the upper bridge to the lower bridge level adjuster 756 are used as the control signals between the upper bridge and the control signals associated with the lower bridge. Adjustment function. The lower bridge pair upper bridge level regulators 755, 757 each have an input end and an output end. When the voltage of the input end is the first lower bridge voltage, the output end outputs the first upper bridge voltage; and when the input end is When the voltage is the second lower bridge voltage, the output terminal outputs the second upper bridge voltage. The upper bridge to the lower bridge level regulator 756 has an input end and an output end. When the voltage of the input end is the first upper bridge voltage, the output end outputs the first lower bridge voltage; and when the voltage of the input end is the first When the voltage is on the upper bridge, the output terminal outputs the second lower bridge voltage. The design of the level shifter is well known to those skilled in the art and will not be further described herein. It is worth noting that when the first upper bridge voltage is equal to the first lower bridge voltage and the second upper bridge voltage is equal to the second lower bridge voltage, the lower bridge pair upper bridge level regulators 755, 757 and the upper bridge to the lower bridge The input of the bit adjuster 756 can be directly connected to the output.

Further, the power switch driver stage 740 is applied to the case where the current of the energy storage inductor 710 is as shown by the direction of the current path 715 when the voltage conversion circuit 760 is at no load time. When the channel of the upper bridge power switch is to be turned off and then the channel of the lower bridge power switch is turned on When the output of the power switch control circuit 752 is converted from the second lower bridge voltage to the first lower bridge voltage, the output of the second upper bridge drive stage 754 is reacted to output the first upper bridge voltage to cut off the second upper The channel of the bridge power switch 750, and then the second input end of the first upper bridge driver stage 753 also has a positive edge due to the output transition state of the second upper bridge driver stage 754, so the output of the first upper bridge driver stage 753 is output. A first upper bridge voltage is applied to the channel of the first upper bridge power switch 790. As can be seen from the above description, the power switch driver stage 740 implements the spirit of the present invention in which the channel of the second upper bridge power switch 750 is turned off first, and then the channel of the first upper bridge power switch 790 is turned off.

Then, the dead time is entered. At this time, since the current of the storage inductor 710 is in the direction indicated by the current path 715, the voltage at the connection point 735 gradually decreases. At the same time, the second input end of the first lower bridge driver stage 749 generates a positive edge due to the transition state of the output end of the first upper bridge driver stage 753, and the output end of the first lower bridge driver stage 749 reacts to output the first lower bridge voltage. The channel of the third transistor 745 and the second transistor 744 is cut off, and the transfer gate 746 is turned on. Since the gate or the base of the fourth transistor 747 is the first lower bridge voltage at this time, when the voltage of the connection point 735 drops to a certain value, the channel of the fourth transistor 747 is turned on and the connection point 735 is The voltage is coupled to the gate or the base of the first transistor 743, and the channel of the first transistor 743 is turned on, so that the control end of the first lower-bridge power switch 720 is coupled to the first lower-bridge voltage, and is turned on. The first lower bridge power switch 720 channels and ends the dead time. It should be noted that since the connection voltage 735 is at a higher voltage, the high voltage may exceed the range that the transfer gate 746 can tolerate, the fourth transistor 747 may be a P-type laterally diffused metal oxide semiconductor to isolate the The high voltage and power switches drive the other components in stage 740 and are compatible with the high voltages described.

Then, at this time, since the first input terminal and the second input terminal of the second lower bridge driving stage 751 are simultaneously the first lower bridge voltage, the output end of the second lower bridge driving stage 751 outputs the first lower bridge voltage, and The channel of the second lower bridge power switch 730 is turned on. At this point, the lower bridge power switch completes the conduction procedure of its channel. As can be seen from the above description, one of the functions of the power switch driver stage 740 is that the voltage state of the connection point 735 can be detected, thereby controlling the channel for turning on the power switch of the lower bridge, and realizing the channel of the first lower bridge power switch 720. The spirit of the invention of the passage of the second lower bridge power switch 730 is again turned on.

When the channel of the lower bridge power switch is to be turned off and then the channel of the upper bridge power switch is turned on, the output of the power switch control circuit 752 is converted from the first lower bridge voltage to the second lower bridge voltage, and the second lower bridge driver stage The output of 751 is the reaction and the first lower bridge voltage is transformed into the first Two lower bridge voltages to cut off the channel of the second lower bridge power switch 730, the negative edge of the output end of the second lower bridge driver stage 751 and react to the first input end of the first lower bridge driver stage 749, the first lower bridge The output of the driver stage 749 reacts to output a second lower bridge voltage, turns on the channels of the third transistor 745 and the second transistor 744, and turns off the transfer gate 746. The gate or base of the first transistor 743 is coupled to the first lower bridge voltage through the channel of the third transistor 745 to turn off the channel of the first transistor 743. At this time, the control end of the first lower bridge power switch 720 is coupled to the second lower bridge voltage through the channel of the second transistor 744, and the channel of the first lower bridge power switch 720 is turned off. As can be seen from the above description, the power switch driver stage 740 also implements the spirit of the present invention in which the channel of the second lower bridge power switch 730 is turned off first, and then the channel of the first lower bridge power switch 720 is turned off.

Then, the first input end of the first upper bridge driving stage 753 generates a negative edge due to the control end transition state of the first lower bridge power switch 720, and the output end of the first upper bridge driving stage 753 outputs a second upper bridge voltage. And turning on the channel of the first upper bridge power switch 790. Then, since the first input terminal and the second input terminal of the second upper bridge driver stage 754 are simultaneously the second upper bridge voltage, the output of the second upper bridge driver stage 754 The second upper bridge voltage is output and the channel of the second upper bridge power switch 750 is turned on. As can be seen from the above description, the power switch driver stage 740 achieves the spirit of the present invention by first turning on the channel of the first upper bridge power switch 790 and then turning on the path of the second upper bridge power switch 750.

Figure 8 is a seventh embodiment of the present invention, which is an apparatus 800 for preventing parasitic elements from being turned on. The apparatus 800 for preventing the parasitic element from being turned on is another embodiment of the apparatus 500 for preventing parasitic element conduction shown in FIG. 5, and is applied to the voltage conversion circuit 860 for preventing the parasitic element of the power switch from being turned on. The voltage conversion circuit 860 is a buck switching power converter, which adjusts the energy stored in the energy storage inductor 810 to be supplied to the output load, and converts the input voltage of the input terminal 870 into an output voltage at an output end. 880. The apparatus 800 for preventing parasitic elements from conducting includes an upper bridge power switch, a lower bridge power switch, and a power switch drive stage 840. The upper bridge power switch further includes a first upper bridge power switch 890 and a second upper bridge power switch 850, which may be a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor. The lower bridge power switch further includes a first lower bridge power switch 820 and a second lower bridge power switch 830, which may be an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor. The power switch driver stage 840 further includes a first upper bridge voltage terminal 841, a second upper bridge voltage terminal 842, a first transistor 843, a second transistor 844, a third transistor 845, a transmission gate 846, and a fourth transistor 847. , a reverse brake 848, a first lower bridge drive stage 849, a second lower bridge drive stage 851, The first upper bridge driver stage 853, the second upper bridge driver stage 854, the power switch control circuit 852, the lower bridge pair upper bridge level regulators 855, 857, and the upper bridge to lower bridge level regulator 856.

As shown in FIG. 8, the first upper bridge voltage terminal 841 has a first upper bridge voltage. The second upper bridge voltage terminal 842 has a second upper bridge voltage and the second upper bridge voltage is less than the first upper bridge voltage. The first transistor 843 is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor. The channel of the first transistor 843 is coupled to the second upper bridge voltage terminal 842 and the first upper bridge power. Between the control terminals of the switch 890. The second transistor 844 is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, and the channel of the second transistor 844 is coupled to the first upper bridge voltage terminal 841 and the first upper bridge power. Between the control terminals of the switch 890. The third transistor 845 is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, and the channel of the third transistor 845 is coupled to the second upper voltage terminal 842 and the first transistor 843. Between the gate or base.

As shown in FIG. 8, one end of the channel of the transmission gate 846 is coupled to the gate or the base of the first transistor 843, and the inverting control terminal of the transmission gate 846 is coupled to the gate or the base of the third transistor 845. The positive phase control terminal of the transfer gate 846 is coupled to the gate or base of the second transistor 844. The fourth transistor 847 is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, and the channel of the fourth transistor 847 is coupled to the other end of the channel of the transmission gate 846 and the upper bridge power switch. Between one end of the channel, the gate or base of the fourth transistor 847 is coupled to the gate or base of the third transistor 845. The input end of the inverting gate 848 is coupled to the gate or the base of the fourth transistor 847, and the output end of the inverting gate 848 is coupled to the positive phase control terminal of the transmission gate 846.

As shown in FIG. 8, the first upper bridge driving stage 853 has a first input end, a second input end, and an output end. The output end of the first upper bridge driving stage 853 is coupled to the input end of the inverting gate 848. The first input end of the upper bridge driver stage 853 is coupled to the control terminal of the first lower bridge power switch 820 through the lower bridge, and the second input end of the first upper bridge driver stage 853 is coupled. At the control end of the second upper bridge power switch 850, when the signal received by the first input terminal of the first upper bridge driver stage 853 has a negative edge, the output of the first upper bridge driver stage 853 outputs a second upper bridge voltage. When the signal received by the second input of the first upper bridge driver stage 853 is positive, the output of the first upper bridge driver stage 853 outputs the first upper bridge voltage. The second upper bridge driving stage 854 has a first input end, a second input end, and an output end. The output end of the second upper bridge driving stage 854 is coupled to the control end of the second upper bridge power switch 850, and the second upper bridge is driven. The first input end of the stage 854 is coupled to the first The control terminal of the bridge power switch 890, when one of the first input terminal and the second input terminal of the second upper bridge driver stage 854 is the first upper bridge voltage, the output of the second upper bridge driver stage 854 is output. The first upper bridge voltage, otherwise the output of the second upper bridge driver stage 854 outputs a second upper bridge voltage.

As shown in FIG. 8, the first lower bridge driving stage 849 has a first input end, a second input end, and an output end, and the output end of the first lower bridge driving stage 849 is coupled to the control of the first lower bridge power switch 820. The first input end of the first lower bridge driving stage 849 is coupled to the control end of the second lower bridge power switch 830, and the second input end of the first lower bridge driving stage 849 is transmitted through the upper bridge to the lower bridge level adjusting unit. The 856 is coupled to the control end of the first upper bridge power switch 890. When the signal received by the first input end of the first lower bridge driving stage 849 has a negative edge, the output of the first lower bridge driving stage 849 outputs the second lower output. The bridge voltage, when the signal received by the second input terminal of the first lower bridge driver stage 849 is positive, the output of the first lower bridge driver stage 849 outputs the first lower bridge voltage. The second lower bridge driving stage 851 has a first input end, a second input end, and an output end. The output end of the second lower bridge driving stage 851 is coupled to the control end of the second lower bridge power switch 830, and the second lower bridge is driven. The second input end of the stage 851 is coupled to the control end of the first lower bridge power switch 820. When the first input end and the second input end of the second lower bridge drive stage 851 are simultaneously the first lower bridge voltage, the second The output of the lower bridge driver stage 851 outputs a first lower bridge voltage, otherwise the output of the second lower bridge driver stage 851 outputs a second lower bridge voltage.

As shown in FIG. 8, the power switch control circuit 852 has an output coupled to the first input of the second lower bridge driver stage 851, and the output of the power switch control circuit 852 is also adjusted by the lower bridge to the upper bridge. The device 857 is coupled to the second input end of the second upper bridge driving stage 854 to control the on or off of the channel of the upper bridge power switch and the lower bridge power switch. The lower bridge pair upper bridge level regulators 855, 857 and the upper bridge to lower bridge level adjuster 856 and the lower bridge upper rail level adjusters 755, 757 and the upper bridge to the lower bridge level in Fig. 7 Regulator 756 has the same function and function, please refer to the related instructions above.

Further, the power switch driver stage 840 is applied to the case where the current of the energy storage inductor 810 is as shown by the direction of the current path 815 when the voltage conversion circuit 860 is at no load time. When the channel of the lower bridge power switch is to be turned off and then the channel of the upper bridge power switch is turned on, the output of the power switch control circuit 852 is switched from the first lower bridge voltage to the second lower bridge voltage, and the second lower bridge driver stage 851 The output terminal reacts to output a second lower bridge voltage to turn off the channel of the second lower bridge power switch 830, and then the first input end of the first lower bridge driver stage 849 is also turned by the output of the second upper bridge driver stage 851 The negative edge occurs, so the output of the first lower bridge driver stage 849 A second lower bridge voltage is output to turn off the channel of the first lower bridge power switch 820. As can be seen from the above description, the power switch driver stage 840 implements the spirit of the present invention in which the channel of the second lower bridge power switch 830 is turned off first, and then the channel of the first lower bridge power switch 820 is turned off.

Then, the dead time is entered. At this time, since the current of the storage inductor 810 is in the direction indicated by the current path 815, the voltage at the connection point 835 gradually rises. At the same time, the first input end of the first upper bridge driving stage 853 generates a negative edge due to the transition state of the output end of the first lower bridge driving stage 849, and the output end of the first upper bridge driving stage 853 reacts to output the second upper bridge voltage. The channel of the third transistor 845 and the second transistor 844 is cut off, and the transfer gate 846 is turned on. Since the gate or the base of the fourth transistor 847 is the second upper bridge voltage at this time, when the voltage of the connection point 835 rises to a certain value, the channel of the fourth transistor 847 is turned on and the connection point 835 is The voltage is coupled to the gate or the base of the first transistor 843, and the channel of the first transistor 843 is turned on, so that the control end of the first upper bridge power switch 890 is coupled to the second upper bridge voltage, and is turned on. The first upper bridge power switch 890 channels and ends the dead time. It is noted that the fourth transistor 847 can be a P-type laterally diffused metal oxide semiconductor to isolate the connection points and other components in the power switch driver stage 840 to be compatible with possible high voltage differences.

Then, at this time, since the first input terminal and the second input terminal of the second upper bridge driving stage 854 are simultaneously the second upper bridge voltage, the output end of the second upper bridge driving stage 854 outputs the second upper bridge voltage, and The channel of the second upper bridge power switch 850 is turned on. At this point, the upper bridge power switch completes the conduction procedure of its channel. It can be seen from the above description that one of the functions of the power switch driving stage 840 is that the voltage state of the connection point 835 can be detected, thereby controlling the channel for turning on the power switch of the lower bridge, and realizing the channel of the first upper bridge power switch 890. The spirit of the invention of the passage of the second upper bridge power switch 850 is again turned on.

When the channel of the upper bridge power switch is to be turned off and then the channel of the lower bridge power switch is turned on, the output of the power switch control circuit 852 is converted from the second lower bridge voltage to the first lower bridge voltage, and the second upper bridge driver stage The output of the 854 is reacted and the second upper bridge voltage is converted to the first upper bridge voltage to cut off the channel of the second upper bridge power switch 850, and the positive edge of the output end of the second upper bridge driver stage 854 is reflected to The second input end of the first upper bridge driving stage 853, the output end of the first upper bridge driving stage 853 reacts to output the first upper bridge voltage, turns on the channels of the third transistor 845 and the second transistor 844, and cuts off the transmission. Gate 846. The gate or the base of the first transistor 843 is coupled to the second upper bridge voltage through the channel of the third transistor 845 to turn off the first transistor 843. Road. At this time, the control end of the first upper bridge power switch 890 is coupled to the first upper bridge voltage through the channel of the second transistor 844, and the channel of the first upper bridge power switch 890 is turned off. As can be seen from the above description, the power switch driver stage 840 also implements the spirit of the present invention in which the channel of the second upper bridge power switch 850 is turned off first, and then the channel of the first upper bridge power switch 890 is turned off.

Then, the second input end of the first lower bridge driving stage 849 generates a positive edge due to the control end transition state of the first upper bridge power switch 890, and the output end of the first lower bridge driving stage 849 outputs a first lower bridge voltage. And turning on the channel of the first lower bridge power switch 820. Then, since the first input end and the second input end of the second lower bridge driving stage 851 are simultaneously the first lower bridge voltage, the output end of the second lower bridge driving stage 851 The first lower bridge voltage is output and the channel of the second lower bridge power switch 830 is turned on. As can be seen from the above description, the power switch driver stage 840 achieves the spirit of the present invention by first turning on the channel of the first lower bridge power switch 820 and then turning on the path of the second lower bridge power switch 830.

Figure 9 is a flow chart showing the steps of the method for preventing the conduction of parasitic elements in the eighth embodiment of the present invention. The method of preventing the parasitic element from being turned on is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on, and includes the following steps:

As shown in step 910, it is determined whether the power switch driver stage sends a signal to turn on the lower bridge power switch, and if so, proceeds to the next step.

As shown in step 920, the first lower bridge power switch is turned on first, and then the second lower bridge power switch is turned on.

As shown in step 930, it is determined whether the power switch driver stage issues a signal to turn off the lower bridge power switch, and if so, proceeds to the next step.

As shown in step 940, the second lower bridge power switch is turned off, then the first lower bridge power switch is turned off, and the process returns to step 910.

FIG. 10 is a flow chart showing the steps of a method for preventing conduction of a parasitic element according to a ninth embodiment of the present invention. The method of preventing the parasitic element from being turned on is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on, and includes the following steps:

As shown in step 1010, it is determined whether the power switch driver stage sends a signal to turn on the lower bridge power switch, and if so, proceeds to the next step.

As shown in step 1020, it is determined whether the voltage at one of the channels of the lower bridge power switch is lower than a voltage threshold, and if so, the next step is performed.

As shown in steps 1030, 1040, and 1050, reference may be made to the steps in the eighth embodiment. The operations of steps 920, 930, and 940.

FIG. 11 is a flow chart showing the steps of a method for preventing conduction of a parasitic element according to a tenth embodiment of the present invention. The method of preventing the parasitic element from being turned on is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on, and includes the following steps:

As shown in step 1110, it is determined whether the power switch drive stage signals a signal to turn on the lower bridge power switch, and if so, proceeds to the next step.

As shown in step 1120, the second upper bridge power switch is turned off first, and then the first upper bridge power switch is turned off.

As shown in step 1130, the first lower bridge power switch is turned on first, and then the second lower bridge power switch is turned on.

As shown in step 1140, it is determined whether the power switch driver stage issues a signal to turn off the lower bridge power switch, and if so, proceeds to the next step.

As shown in step 1150, the second lower bridge power switch is turned off first, and then the first lower bridge power switch is turned off.

As shown in step 1160, the first upper bridge power switch is turned on, then the second upper bridge power switch is turned on, and the process returns to step 1110.

Figure 12 is a flow chart showing the steps of the method for preventing the conduction of parasitic elements in the eleventh embodiment of the present invention. The method of preventing the parasitic element from being turned on is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on, and includes the following steps:

As shown in steps 1210 and 1220, reference may be made to the operations of steps 1110 and 1120 in the tenth embodiment.

As shown in step 1230, it is determined whether the voltage at one of the channels of the lower bridge power switch is lower than a voltage threshold, and if so, the next step is performed.

As shown in steps 1240, 1250, 1260, 1270, reference may be made to the operations of steps 1130, 1140, 1150, 1160 in the tenth embodiment.

Figure 13 is a flow chart showing the steps of a method for preventing conduction of a parasitic element according to a twelfth embodiment of the present invention. The method of preventing the parasitic element from being turned on is applied to a voltage conversion circuit for preventing the parasitic element of the power switch from being turned on, and includes the following steps:

As shown in steps 1310, 1320, 1330, 1340, 1350, reference may be made to the operations of steps 1110, 1120, 1130, 1140, 1150 in the tenth embodiment.

As shown in step 1360, it is determined whether the voltage at one of the channels of the upper bridge power switch is higher than a voltage threshold, and if so, the next step is performed.

As shown in step 1370, reference may be made to the operation of step 1160 in the tenth embodiment.

The invention has the advantages that the device for preventing parasitic element conduction and the method thereof disclosed in the invention can effectively reduce the operation dead time of the applied voltage conversion circuit to prevent the parasitic component of the power switch from being turned on, and At the same time, the occurrence of the penetration current is avoided, thereby increasing the conversion efficiency of the voltage conversion circuit and reducing the current noise in the substrate.

Although the embodiments of the present invention are disclosed above, it is not intended to limit the present invention, and those skilled in the art, regardless of the spirit and scope of the present invention, the shapes, structures, and features described in the scope of the present application. And the number of modifications may be made, and the scope of patent protection of the present invention shall be determined by the scope of the patent application attached to the specification.

200‧‧‧A device for preventing the conduction of parasitic elements

210‧‧‧ Storage inductance

220‧‧‧First lower bridge power switch

230‧‧‧Second lower bridge power switch

240‧‧‧Power switch driver stage

250‧‧‧Voltage conversion circuit

260‧‧‧ connection point

Claims (15)

A device for preventing conduction of a parasitic element is applied to a voltage conversion circuit for preventing conduction of a parasitic element of a power switch, wherein the voltage conversion circuit adjusts energy stored in a storage inductor to supply to an output load, and The input voltage is converted into an output voltage at an output end; the device for preventing the parasitic element from being turned on includes: a lower bridge power switch having a first lower bridge power switch and a second lower bridge power switch, the channel of the lower bridge power switch The channel of the first lower bridge power switch and the channel of the second lower bridge power switch are formed in parallel, and the conduction equivalent impedance of the channel of the first lower bridge power switch is greater than the conduction of the channel of the second lower bridge power switch An equivalent impedance, and one end of the channel of the lower bridge power switch is coupled to the energy storage inductor; and a power switch drive stage coupled to the control end of the first lower bridge power switch and the second lower bridge power a control end of the switch, configured to control a channel that turns on or off the power switch of the lower bridge; wherein, when the power switch driver stage controls to turn on the lower bridge function When the channel of the switch is turned on, the channel of the first lower bridge power switch is turned on to turn on the channel of the second lower bridge power switch, and when the power switch drive stage controls to cut off the channel of the lower bridge power switch, the system is first turned off. The channel of the second lower bridge power switch then cuts off the channel of the first lower bridge power switch. The device of claim 1, further comprising an upper bridge power switch having a first upper bridge power switch and a second upper bridge power switch, wherein the upper bridge power switch channel is configured by the first upper bridge a channel of the power switch and a channel of the second upper bridge power switch are formed in parallel, and the first upper bridge power switch The conductive equivalent impedance of the channel is greater than the conductive equivalent impedance of the channel of the second upper bridge power switch, and one end of the channel of the upper bridge power switch is coupled to the channel of the lower bridge power switch and the connection point of the energy storage inductor . The device of claim 2, wherein the power switch driving stage is further coupled to the control end of the first upper bridge power switch and the control end of the second upper bridge power switch, and when the power switch is driven When the stage control turns on the channel of the upper bridge power switch, the channel of the first upper bridge power switch is first turned on and then the channel of the second upper bridge power switch is turned on, and when the power switch drive stage controls the off-bridge power switch When the channel of the second upper bridge power switch is turned off, the channel of the first upper bridge power switch is turned off. The device of claim 1, wherein the first lower bridge power switch and the second lower bridge power open relationship are an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, The power switch driving stage further includes: a first lower bridge voltage terminal having a first lower bridge voltage; a second lower bridge voltage terminal having a second lower bridge voltage, and the second lower bridge voltage is less than the a first lower bridge voltage; a first transistor is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, and the channel of the first transistor is coupled to the first lower bridge voltage Between the terminal and the control end of the first lower bridge power switch; a second transistor is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, the channel of the second transistor Coupled to a second lower bridge voltage terminal and a control end of the first lower bridge power switch; a third transistor is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, a channel of the third transistor is coupled between the voltage of the first lower bridge and the gate or the base of the first transistor; and a transmission gate, one end of the channel of the transmission gate is coupled to the first transistor a gate or a base, the positive phase control end of the transfer gate is coupled to the gate or the base of the third transistor, and the inverting control end of the transfer gate is coupled to the gate of the second transistor or a fourth transistor, which is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, the channel of the fourth transistor being coupled to the other end of the channel of the transmission gate and Between one end of the channel of the lower bridge power switch, the gate or the base of the fourth transistor is coupled to the gate or the base of the third transistor; an inverting gate, the input end of the inverting gate The gate or the base of the fourth transistor is coupled to the output of the reverse gate a first lower bridge driving stage having a first input end, a second input end, and an output end, wherein the output end of the first lower bridge driving stage is coupled to the input end of the inverting gate, when the first When the signal received by the first input end of the lower bridge driver stage has a negative edge, the output of the first lower bridge driver stage outputs the second lower bridge voltage, and the second input terminal of the first lower bridge driver stage receives the second input terminal. When the signal has a positive edge, the output of the first lower bridge driver stage outputs the first lower bridge voltage; a second lower bridge driving stage having a first input end, a second input end, and an output end, wherein the output end of the second lower bridge driving stage is coupled to the control end of the second lower bridge power switch and the first a first input end of the bridge driving stage, a second input end of the second lower bridge driving stage is coupled to the control end of the first lower bridge power switch, when the first input end of the second lower bridge driving stage When the two input terminals are simultaneously the first lower bridge voltage, the output end of the second lower bridge driving stage outputs the first lower bridge voltage, otherwise the output end of the second lower bridge driving stage outputs the second lower bridge voltage; And a power switch control circuit having an output coupled to the second input of the first lower bridge driver stage and the first input of the second lower bridge driver stage for outputting the first lower bridge voltage or The second lower bridge voltage controls the turn-on or turn-off of the channel of the lower bridge power switch. The device of claim 2, wherein the first upper bridge power switch and the second upper bridge power open relationship are a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, The power switch driving stage further includes: a first lower bridge voltage terminal having a first lower bridge voltage; a second lower bridge voltage terminal having a second lower bridge voltage, and the second lower bridge voltage is less than the a first lower bridge voltage; a first transistor is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, and the channel of the first transistor is coupled to the first lower bridge voltage Between the terminal and the control end of the first lower bridge power switch; a second transistor, which is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, the channel of the second transistor is coupled to the second lower bridge voltage terminal and the first Between the control terminals of the bridge power switch; a third transistor is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, and the channel of the third transistor is coupled to the first a voltage of the lower bridge and a gate or a base of the first transistor; a transmission gate, one end of the channel of the transmission gate is coupled to the gate or the base of the first transistor, and the transmission gate is positive The phase control terminal is coupled to the gate or the base of the third transistor, and the inverting control end of the transmission gate is coupled to the gate or the base of the second transistor; a fourth transistor is N a metal-oxide-semiconductor field effect transistor or an NPN-type bipolar junction transistor, the channel of the fourth transistor being coupled between the other end of the channel of the transmission gate and one end of the channel of the lower bridge power switch, a gate or a base of the fourth transistor is coupled to a gate or a base of the third transistor An inverting gate, the input end of the inverting gate is coupled to the gate or the base of the fourth transistor, and the output end of the inverting gate is coupled to the inverting control end of the transmission gate; a bridge driver stage having a first input terminal, a second input terminal, and an output terminal, wherein an output end of the first lower bridge driver stage is coupled to an input end of the inverting gate, and a first input of the first lower bridge driver stage The second input end of the first lower bridge driving stage is coupled to the control end of the first upper bridge power switch, and the first lower bridge driving stage is coupled to the control end of the second lower bridge power switch First When the signal received by an input terminal has a negative edge, the output end of the first lower bridge driver stage outputs the second lower bridge voltage, and when the signal received by the second input end of the first lower bridge driver stage has a positive edge, An output of the first lower bridge driver stage outputs the first lower bridge voltage; a second lower bridge driver stage has a first input terminal, a second input terminal, and an output terminal, and an output end of the second lower bridge driver stage The second input end of the second lower bridge driving stage is coupled to the control end of the first lower bridge power switch, and the second lower bridge driving stage is coupled to the control end of the second lower bridge power switch When an input end and a second input end are simultaneously the first lower bridge voltage, the output end of the second lower bridge driving stage outputs the first lower bridge voltage, otherwise the output end of the second lower bridge driving stage outputs the first a second bridge voltage; a first upper bridge driver stage having a first input terminal, a second input terminal, and an output terminal, wherein the output end of the first upper bridge driver stage is coupled to the control end of the first upper bridge power switch The first input end of the first upper bridge driver stage is coupled to the first lower bridge function a second input end of the first upper bridge driving stage is coupled to the control end of the second upper bridge power switch, and a signal is received at a first input end of the first upper bridge driving stage The output end of the first upper bridge driver stage outputs a second upper bridge voltage, and when the signal received by the second input end of the first upper bridge driver stage has a positive edge, the output of the first upper bridge driver stage The terminal outputs a first upper bridge voltage; a second upper bridge driver stage has a first input end, a second input end, and an output end, and the output end of the second upper bridge drive stage is coupled to the second upper bridge power a first input end of the second upper bridge driving stage is coupled to the control end of the first upper bridge power switch, and the first upper bridge driving stage is first When the input terminal and the second input terminal are both the first upper bridge voltage, the output end of the second upper bridge driver stage outputs the first upper bridge voltage, otherwise the output end of the second upper bridge driver stage Outputting the second upper bridge voltage; and a power switch control circuit having an output end, the output end of the power switch control circuit being coupled to the second input end of the second upper bridge drive stage and the second lower bridge drive The first input of the stage is configured to control whether the upper bridge power switch and the channel of the lower bridge power switch are turned on or off. The device of claim 4, wherein the fourth electro-crystalline system is an N-type laterally diffused metal oxide semiconductor for compatibility with a voltage at one end of the channel of the lower bridge power switch. The device of claim 2, wherein the first upper bridge power switch and the second upper bridge power open relationship are a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, The power switch driving stage further includes: a first upper bridge voltage terminal having a first upper bridge voltage; a second upper bridge voltage terminal having a second upper bridge voltage, and the second upper bridge voltage is less than the a first upper bridge voltage; a first transistor is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, and the channel of the first transistor is coupled to the second upper bridge voltage Between the terminal and the control end of the first upper bridge power switch; a second transistor is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, the channel of the second transistor Coupled to a first upper bridge voltage terminal and a control end of the first upper bridge power switch; a third transistor is an N-type metal oxide semiconductor field effect transistor or an NPN type bipolar junction transistor, a channel of the third transistor is coupled between the voltage terminal of the second upper bridge and the gate or the base of the first transistor; and a transmission gate, one end of the channel of the transmission gate is coupled to the first transistor The gate or the base of the transmission gate is coupled to the gate or the base of the third transistor, and the positive phase control terminal of the transmission gate is coupled to the gate of the second transistor or a fourth transistor, which is a P-type metal oxide semiconductor field effect transistor or a PNP type bipolar junction transistor, the channel of the fourth transistor being coupled to the other end of the channel of the transmission gate and Between one end of the channel of the upper bridge power switch, the gate or the base of the fourth transistor is coupled to the gate or the base of the third transistor; an inverting gate, the input of the inverting gate The end is coupled to the gate or the base of the fourth transistor, and the output end of the inverting gate is coupled to the positive of the transmission gate a first upper bridge driving stage having a first input end, a second input end, and an output end, wherein the output end of the first upper bridge driving stage is coupled to the input end of the inverting gate, the first The first input end of the bridge drive stage is coupled to the control end of the first lower bridge power switch, and the second input end of the first upper bridge drive stage is coupled to the control end of the second upper bridge power switch. When the signal received by the first input end of the first upper bridge driver stage has a negative edge, the output end of the first upper bridge driver stage outputs the second upper bridge voltage, and when the first upper bridge driver stage is the second input When the signal received by the input terminal has a positive edge, the output end of the first upper bridge driver stage outputs the first upper bridge voltage; and the second upper bridge driver stage has a first input end, a second input end, and an output end, The output end of the second upper bridge power stage is coupled to the control end of the second upper bridge power switch, and the first input end of the second upper bridge drive stage is coupled to the control end of the first upper bridge power switch. When the first input terminal and the second input terminal of the second upper bridge driving stage are the first upper bridge voltage, the output end of the second upper bridge driving stage outputs the first upper bridge voltage, Otherwise, the output of the second upper bridge driver stage outputs the second upper bridge voltage; a first lower bridge driver stage has a first input terminal, a second input terminal, and an output terminal, and the output of the first lower bridge driver stage The first input end of the first lower bridge driving stage is coupled to the control end of the second lower bridge power switch, and the first lower bridge driving stage is coupled to the control end of the first lower bridge power switch The second input end is coupled to the control end of the first upper bridge power switch, when the first lower bridge is driven When the signal received by the first input terminal has a negative edge, the output end of the first lower bridge driver stage outputs a second lower bridge voltage, and when the signal received by the second input end of the first lower bridge driver stage occurs, a positive edge occurs. The output terminal of the first lower bridge driver stage outputs a first lower bridge voltage; a second lower bridge driver stage has a first input terminal, a second input terminal, and an output terminal, and the second lower bridge driver stage The output end is coupled to the control end of the second lower bridge power switch, and the second input end of the second lower bridge drive stage is coupled to the control end of the first lower bridge power switch, when the second lower bridge drive stage When the first input end and the second input end are simultaneously the first lower bridge voltage, the second The output of the lower bridge driver stage outputs the first lower bridge voltage, otherwise the output of the second lower bridge driver stage outputs the second lower bridge voltage; and a power switch control circuit having an output terminal, the power switch control The output end of the circuit is coupled to the second input end of the second upper bridge driving stage and the first input end of the second lower bridge driving stage to control the conduction of the upper bridge power switch and the channel of the lower bridge power switch Or deadline. The device of claim 7, wherein the fourth electro-crystalline system is a P-type laterally diffused metal-oxide-semiconductor for compatibility with a voltage at one end of the channel of the upper bridge power switch. The apparatus of any one of clauses 1 to 5, wherein the voltage conversion circuit is a buck switching power converter. The apparatus of any one of clauses 1 to 3, wherein the voltage conversion circuit is in the form of a step-up switching power converter. A method for preventing conduction of a parasitic element is applied to a voltage conversion circuit for preventing conduction of a parasitic element of a power switch, the method comprising the steps of: determining whether a power switch driver stage emits a signal to turn on a bridge power switch, and if so, Then proceeding to the next step; first conducting a first lower bridge power switch, and then conducting a second lower bridge power switch; determining whether the power switch driver stage sends a signal to turn off the lower bridge power switch, and if so, proceeding to the next step Turning off the second lower bridge power switch first, and then turning off the first lower bridge power switch; Returning to the step of determining whether the power switch driver stage signals to turn on the lower bridge power switch. The method of claim 11, further comprising the following steps: if it is determined that the power switch driver stage sends a signal to turn on the lower bridge power switch, the result is that the channel of the lower bridge power switch is first determined. Whether the voltage of one of the terminals is lower than a voltage threshold, and if so, the step of first conducting the first lower bridge power switch and then conducting the second lower bridge power switch. A method for preventing conduction of a parasitic element is applied to a voltage conversion circuit for preventing conduction of a parasitic element of a power switch, the method comprising the steps of: determining whether a power switch driver stage emits a signal to turn on a bridge power switch, and if so, Then proceed to the next step; first turn off a second upper bridge power switch, then turn off a first upper bridge power switch; first turn on a first lower bridge power switch, and then turn on a second lower bridge power switch; determine the power switch Whether the driver stage sends a signal to turn on an upper bridge power switch, and if so, proceeds to the next step; first turns off the second lower bridge power switch, and then turns off the first lower bridge power switch; first turns on the first upper bridge power switch And then turning on the second upper bridge power switch; Returning to the step of determining whether the power switch driver stage signals to turn on the lower bridge power switch. The method of claim 13, further comprising the steps of: first performing the step of turning off the second upper bridge power switch, and then turning off the first upper bridge power switch, first determining the lower bridge power switch Whether the voltage at one of the channels is lower than a voltage threshold, and if so, the step of first conducting the first lower bridge power switch and then conducting the second lower bridge power switch. The method of claim 13, further comprising the steps of: determining the power switch of the upper bridge after performing the step of first turning off the power switch of the second lower bridge and then turning off the power switch of the first lower bridge; Whether the voltage at one end of the channel is higher than a voltage threshold, and if so, the step of first conducting the first upper bridge power switch and then conducting the second upper bridge power switch.