TWI548001B - Method for fabricating metal-oxide-semiconductor field-effect transistor - Google Patents

Description

Gold oxide semi-transistor manufacturing method

The present invention is a method for manufacturing a gold oxide semi-transistor, and more particularly to a method for manufacturing a gold oxide semi-transistor used in a semiconductor process.

As the gate length shrinks to encounter bottlenecks and new materials have not yet been discovered and validated, mobility adjustment engineering has become an important contributor to improving the performance of integrated circuits. For example, the channel lattice strain of MOS transistors has been commonly used to enhance mobility, where the lattice strain enthalpy can provide a hole mobility and electron mobility of approximately no lattice strain. The 矽 is 4 times and 1.8 times.

Therefore, the designer can improve the electron mobility by applying tensile stress to the channel of the N-channel MOS transistor, or apply compression stress to the channel of the P-channel MOS transistor. Improve hole mobility, and Stress Memorization Techniques (SMT) is one of many migration rate adjustment engineering technologies developed. However, semiconductor components formed using existing stress memory technology still fail to achieve satisfactory component performance. Therefore, the use of improved stress memory technology to fabricate gold oxide semi-transistors is the main purpose of the development of this case.

The invention provides a method for manufacturing a gold oxide semi-transistor, the method comprising the following steps Step: providing a substrate, the substrate is completed with at least one gate structure, a first spacer, a second spacer, and a source drain structure, wherein the second spacer comprises an inner layer and an outer layer; The wall is reduced in thickness to leave an inner layer; a stress film is formed on the surface of the inner layer and the source drain structure, and a tempering process is performed; and the stress film is removed.

In an embodiment of the invention, the substrate is a germanium substrate, and the gate structure comprises a gate dielectric layer, a barrier metal, a dummy polysilicon gate, and a hard mask, wherein the first spacer The material may be a multilayer structure of tantalum nitride or tantalum oxide/tantalum nitride. The inner layer material of the second spacer is yttrium oxide, and the outer material of the second spacer is tantalum nitride.

In an embodiment of the invention, the gate dielectric layer comprises an intermediate layer and a high-k dielectric layer, the material of the high-k dielectric layer is yttrium oxide, and the material of the intermediate layer is oxidized. The material of the barrier metal is titanium nitride, and the hard mask comprises a tantalum nitride layer and a tantalum oxide layer.

In one embodiment of the invention, the method of completing the source drain structure includes the steps of performing a source-drain structure dopant implantation process and changing the crystal phase of the germanium substrate to an amorphous phase.

In an embodiment of the invention, the method for thickness reduction of the second spacer comprises the steps of: wet etching the second spacer with hot phosphoric acid to remove the outer layer to leave the inner layer.

In an embodiment of the present invention, after removing the stress film, the method further comprises the steps of: forming a contact etch stop layer and an inner dielectric layer over the substrate; removing a partial contact etch stop layer by a chemical mechanical polishing process And a portion of the inner dielectric layer and the hard mask to expose the dummy polysilicon gate; the exposed dummy polysilicon gate is removed to form a space; and a metal gate structure is filled in the space.

In an embodiment of the invention, a method package for filling in the above metal gate structure The method comprises the steps of: filling in an etch barrier; filling in a work function metal structure; and filling in a metal gate.

In an embodiment of the invention, the material of the etching stopper layer is tantalum nitride (TaN), and the material of the work function metal is titanium nitride (TiN) or titanium aluminide (TiAl), and the material of the metal gate is used. For aluminum.

In an embodiment of the invention, after removing the stress film, the method further comprises the step of forming a metal halide on the surface of the source drain structure.

In an embodiment of the invention, the material of the stress film is tantalum nitride or a buffered hafnium oxide layer and a tantalum nitride film.

In an embodiment of the invention, the MOS transistor is a P-channel MOS transistor, and the stress film is a compressive stress film.

In an embodiment of the invention, the MOS transistor is an N-channel MOS transistor, and the stress film is a tensile stress film.

In one embodiment of the invention, the method of removing the stress film described above comprises the step of subjecting the stress film to a wet etch.

In an embodiment of the invention, the method further includes the steps of: forming a contact hole over the source drain structure to expose the surface of the source drain structure; and forming a surface of the source drain structure exposed by the contact hole Metal telluride.

Please refer to FIG. 1A to FIG. 1G, which are schematic diagrams of a semiconductor process flow developed by the applicant for improving stress memory technology. First, FIG. 1A shows a cross-sectional structure completed after the MOS substrate is fabricated on the ruthenium substrate 1. The gate structure is mainly composed of a gate dielectric layer 10 and a barrier metal ( Barrier metal) 11, a dummy polysilicon 12 and a hard mask 13 are formed. The multilayer structure of the gate dielectric layer 10 is mainly performed by an interfacial layer 100 and a high-k dielectric layer 101. The common high-k dielectric layer 101 is hafnium oxide (HfO 2 ). The material of the dielectric layer 100 may be cerium oxide (SiO2). The barrier metal 11 material may be titanium nitride (TiN), and the hard mask 13 may be composed of a tantalum nitride layer (SiN) 132 and a tantalum oxide 131.

As for the sidewall of the gate structure, the first spacer 15 and the second spacer 16 are formed, and the gate structure and the spacer are used as a mask to lightly doped the drain (LDD) 17 and the source substrate. The dopant of the pole structure 18 is implanted. The material of the first spacer 15 may be a multilayer structure of tantalum nitride or tantalum oxide/tantalum nitride. The second spacer 16 is composed of an inner layer 160 and an outer layer 161. The material of the inner layer 160 The material of the outer layer 161 may be tantalum nitride. When the doping of the light-doped drain (LDD) 17 and the source-drain structure 18 is performed, the crystal phase of the germanium substrate 1 is changed into an amorphous phase, so that the previous work of the stress memory technology can be completed.

Next, as shown in FIG. 1B, the second spacer 16 is reduced in thickness by wet etching, and the material of the outer layer 161 of the second spacer 16 is nitrided, for example, and can be removed by hot phosphoric acid (H ₃ PO ₄ ). Tantalum nitride, while utilizing the high etching selectivity characteristics of phosphoric acid for tantalum nitride and tantalum oxide, thus leaving an "L" type tantalum oxide layer of inner layer 160 of second spacer 16.

Then, as shown in FIG. 1C, the stress film 14 is deposited in a stress memory technique. The common stress film material is tantalum nitride or a buffered oxide oxide layer plus a tantalum nitride layer. Since the tantalum nitride film can be controlled to a tensile stress film or a compressive stress film under different deposition conditions, for example, a compressive stress film for enhancing the hole mobility of the P channel can be transparent chemical vapor deposition. The method (CVD) is performed, and the tensile stress film for enhancing the electron mobility of the N channel needs to be completed by a plurality of deposition-curing process cycles. After the deposition of the stress film 14 is completed, the lightly doped gate 17 and the source drain structure 18 are changed to an amorphous phase. The tempering process is performed such that the lightly doped gates 17 and source drain structures 18 that have undergone the tempering process will revert to the crystalline phase and memorize the stress provided by the stress film 14.

Next, as shown in FIG. 1D, the stress film 14 is removed by wet etching to expose the "L"-type yttrium oxide layer 160, and the stress film 14 completed by yttrium nitride is taken as an example, and can be performed by hot phosphoric acid (H ₃ PO ₄ ). Remove. At this time, the metal germanide 180 can be formed by performing a self-aligned metal deuteration process on the surface of the source drain structure 18. Of course, the metal germanide 180 can also be completed after the previous second spacer 16 is formed.

Then, as shown in FIG. 1E, a contact etch stop layer (CESL) 191 and an inner dielectric layer (ILD) 192 are formed over the entire substrate surface. A chemical mechanical polishing process is then used to open the hard mask over the gate structure to expose the dummy polysilicon gate 12, thereby forming a state as shown in FIG. 1F.

The exposed dummy poly 12 can then be removed by wet etching and then filled into a metal gate structure. The metal gate structure can include the etch barrier 120, the work function metal structure 121 and the The metal gate 122, in turn, completes a gate-last-high-dielectric dielectric metal gate (HKMG) metal oxide half-electrode as shown in FIG. 1G. The etching barrier layer 120 may be tantalum nitride (TaN), the work function metal of the P channel gold oxide semi-transistor may be titanium nitride (TiN), and the work function metal of the N-channel gold oxide semi-transistor may be aluminized. Titanium (TiAl), as for the metal gate, can be completed with aluminum (Al). Since the yttria layer 161 in the second spacer 16 is removed by the etch back in this embodiment, the stress film 14 applies stress to the lightly doped drain 17 and the source drain structure 18 which require memory stress more efficiently. Therefore, the channel of the gold-oxide semi-transistor completed in this case will have better mobility adjustment.

In addition to the above-mentioned gate-gold oxide semi-transistor, the technology of the present invention can also be applied to the fabrication of a gate-first MOS transistor, and the technology itself is not different, but it does not need to be performed. After the dummy polysilicon gate 12 is removed, the work function metal 121 and the metal gate 122 are filled. In addition, the high-k dielectric layer 101 is in addition to The above method may be completed first, or may not be fabricated until the dummy polysilicon gate 12 is removed and the high-k dielectric layer 101 and the etch barrier layer 120, the work function metal 121, and the metal gate 122 are sequentially filled. As for the metal germanide 180 on the surface of the source drain structure 18, in addition to the above steps, as shown in FIG. 2, after the contact hole 20 is completed, the surface of the source drain structure 18 exposed by the contact hole 20 is used. To complete, this will facilitate a better stress memory effect for the lightly doped drain 17 and source drain structure 18.

In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1‧‧‧Substrate

10‧‧‧ gate dielectric layer

100‧‧‧ dielectric layer

101‧‧‧High dielectric constant dielectric layer

11‧‧‧Resistance metal

12‧‧‧Fake polysilicon gate

13‧‧‧hard mask

132‧‧‧矽 nitride layer

131‧‧‧Oxide

14‧‧‧ stress film

15‧‧‧First gap

16‧‧‧Second gap

160‧‧‧ inner layer

161‧‧‧ outer layer

17‧‧‧Lightly doped bungee

18‧‧‧ source 汲 structure

120‧‧‧etch barrier

121‧‧‧Work function metal structure

122‧‧‧Metal gate

180‧‧‧Metal Telluride

191‧‧‧Contact etch stop layer

192‧‧‧ Inner dielectric layer

20‧‧‧Contact hole

FIG. 1A to FIG. 1G are schematic diagrams showing the process flow of a gold-oxygen semi-transistor developed by the applicant for improving stress memory technology.

Figure 2 is a schematic view of a gold oxide semi-transistor of another embodiment developed by the Applicant for improving stress memory technology.

120‧‧‧etch barrier

121‧‧‧Work function metal structure

122‧‧‧Metal gate

Claims (13)

A method for manufacturing a gold oxide semi-transparent crystal, the method comprising the steps of: providing a substrate on which at least a gate structure, a first spacer, a second spacer, and a source drain structure are completed, wherein the The second spacer wall comprises an inner layer and an outer layer; the second spacer wall is reduced in thickness to leave the inner layer; and a stress film is formed on the inner layer and the surface of the source drain structure to perform a tempering process; Removing the stress film; forming a contact etch stop layer and an inner dielectric layer over the substrate; removing a portion of the contact etch stop layer, a portion of the inner dielectric layer, and the hard mask by a chemical mechanical polishing process to expose the a dummy polysilicon gate; removing the exposed polysilicon gate to form a space; and filling a metal gate structure in the space. The method of manufacturing the MOS transistor according to the first aspect of the invention, wherein the substrate is a germanium substrate, the gate structure comprises a gate dielectric layer, a barrier metal, a dummy polysilicon gate, and a gate The hard mask may be made of tantalum nitride or tantalum oxide/tantalum nitride. The inner layer of the second spacer is yttrium oxide, and the outer layer of the second spacer is Tantalum nitride. The method of manufacturing the MOS transistor according to the second aspect of the invention, wherein the gate dielectric layer comprises an intermediate layer and a high-k dielectric layer, and the material of the high-k dielectric layer is The ruthenium oxide, the material of the intermediate layer is ruthenium oxide, the material of the barrier metal is titanium nitride, and the hard mask comprises a layer of tantalum nitride and a layer of ruthenium oxide. The method for manufacturing a gold-oxygen semi-transistor according to claim 2, wherein the method for completing the source-drain structure comprises the steps of: performing a source-drain structure dopant implantation process, and performing the germanium substrate The crystal phase changes to an amorphous phase. The method for manufacturing a gold-oxygen semi-transistor according to claim 2, wherein the method for reducing thickness of the second spacer comprises the steps of: wet etching the second spacer with hot phosphoric acid; The outer layer is removed leaving the inner layer. The method of manufacturing a metal oxide semi-transistor according to claim 1, wherein the method of filling the metal gate structure comprises the steps of: filling an etching barrier layer; filling a work function metal structure; and filling in A metal gate. The method for manufacturing a gold-oxygen semi-transistor according to claim 6, wherein the material of the etching barrier layer is tantalum nitride (TaN), and the material of the work function metal is titanium nitride (TiN) or titanium aluminide. (TiAl), the material of the metal gate is aluminum. The method of manufacturing a gold-oxygen semi-transistor according to claim 1, wherein the removing the stress film further comprises the step of forming a metal halide on the surface of the source drain structure. The method for manufacturing a gold oxide semi-transistor according to claim 1, wherein the material of the stress film is tantalum nitride or a buffered hafnium oxide layer and a tantalum nitride film. The method of manufacturing a gold-oxygen semi-transistor according to claim 1, wherein the MOS transistor is a P-channel MOS transistor, and the stress film is a compressive stress film. The method of manufacturing a gold-oxygen semi-transistor according to claim 1, wherein the MOS transistor is an N-channel MOS transistor, and the stress film is a tensile stress film. The method of manufacturing a gold oxide semiconductor according to claim 1, wherein the method of removing the stress film comprises the step of: performing a wet etching on the stress film. The method for fabricating a gold-oxygen semi-transistor according to claim 1, further comprising the steps of: forming a contact hole over the source drain structure to expose a surface of the source drain structure; and the contact hole A surface of the source drain structure is exposed to form a metal halide.