CN101276758A - Method for preparing semiconductor transistor element - Google Patents
Method for preparing semiconductor transistor element Download PDFInfo
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- CN101276758A CN101276758A CNA2007100897765A CN200710089776A CN101276758A CN 101276758 A CN101276758 A CN 101276758A CN A2007100897765 A CNA2007100897765 A CN A2007100897765A CN 200710089776 A CN200710089776 A CN 200710089776A CN 101276758 A CN101276758 A CN 101276758A
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Abstract
The invention discloses a method for manufacturing metal oxide semiconductor transistor element, comprising the steps of: providing a semiconductor substrate; forming a grid electrode dielectric layer on the semiconductor substrate; forming a grid electrode in the grid electrode dielectric layer; forming a liner layer on sidewall of the grid electrode; forming a silicon nitride gap wall on the liner layer; performing drain/source electrodes iron ejection process to the semiconductor substrate in order to form drain/source electrode areas on both sides of the grid electrode; then removing the silicon nitride gap wall; after that, forming a silicatization metal layer on the drain/source electrode areas; subsequently, depositing a cover layer on the liner layer and the silicatization metal layer; the cover layer is directly contacted with the liner layer and includes special stress state.
Description
Technical field
The present invention is about a kind of manufacture method of semiconductor transistor component, especially the metal-oxide semiconductor (MOS) (metal-oxide-semiconductor, MOS) manufacture method of field effect transistor element that refer to a kind of no silicon nitride gap wall (silicon nitride spacer-less).The invention is characterized in conjunction with having different stress (stress) the effect silicon nitride cap rock of (compression or stretching) down, make N or P-type mos field effect transistor element can have higher saturated drain current (I simultaneously
Dsat), improve the operation usefulness of semiconductor transistor component thus.
Background technology
Known to the sector person, the high-speed metal oxide semiconductor's transistor unit that has strained silicon (strained silicon) at present mainly is the different principles that cause producing strain on the structure when silicon epitaxy is on SiGe with silicon of lattice constant of utilizing germanium-silicon layer.In the strained silicon-field effect transistor element of this type, usually involve the biaxial stretching strain (biaxial tensile strain) of silicon layer, this is because the lattice constant (lattice constant) of germanium-silicon layer is bigger than silicon, this makes the band structure (band structure) of silicon change, and then causes mobility of carrier to increase.Therefore channel region adopt the element of strained silicon structure can obtain 1.5 times in addition up to 8 times about speed gain.
Please refer to Fig. 1 to Fig. 3, what it illustrated is the method generalized section of the making semiconductor N MOS transistor element 10 of prior art.At first, as shown in Figure 1, known semiconductor nmos pass transistor element 10 comprises the semiconductor-based end of containing silicon layer 16, the drain electrode 20 that is formed with source electrode 18 and separates mutually by channel region 22 with source electrode 18 in silicon layer 16.According to prior art, silicon layer 16 can be the strained silicon layer that extension (is schemed not show) on germanium-silicon layer.Usually, semiconductor N MOS transistor element 10 has extension 17 of shallow junction source electrode and shallow junction drain electrode to extend 19 in addition.Be formed with gate dielectric 14 on channel region 22, then be formed with grid 12 on gate dielectric 14, wherein grid 12 generally includes polysilicon.
In Fig. 1, the source electrode 18 of semiconductor N MOS transistor element 10 and 20 the N+ doped regions that drain for injection arsenic, antimony or phosphorus, 22 P type doped regions for injection boron of the channel region of semiconductor N MOS transistor element 10 are formed with silicon nitride gap wall 32 on the sidewall of grid 12.Between the sidewall of silicon nitride gap wall 32 and grid 12 is laying 30, it typically is silicon dioxide and constitutes.The bare silicon surfaces of semiconductor N MOS transistor element 10 comprises the surface of drain/source then being formed with metal silicide layer (silicide layer) 42.Because making as the semiconductor N MOS transistor element 10 among Fig. 1 is that the sector person knows, so its detailed production process repeats no more.
After semiconductor N MOS transistor element 10 structures in finishing Fig. 1, as shown in Figure 2, can continue deposited silicon nitride cap rock 46 on the semiconductor-based end usually.Wherein, silicon nitride cap rock 46 covers on metal silicide layer 42 and the silicon nitride gap wall 32, and the thickness of silicon nitride cap rock 46 is usually between 200 to 400 dusts.The purpose of deposited silicon nitride cap rock 46 is to make follow-up contact etch that tangible etching end point can be arranged, just be used as contact etch stop layer (contact etch stoplayer, CESL).After deposited silicon nitride cap rock 46, then dielectric layer 48, silica layer (silicon oxide layer) etc. for example, dielectric layer 48 is thick many than silicon nitride cap rock 46 usually.
Then, as shown in Figure 3, utilize known photoetching (lithography) and etch process, in dielectric layer 48 and silicon nitride cap rock 46, form contact hole (contact hole) 52.As previously mentioned, in etching contact hole 52 processes, the function of silicon nitride cap rock 46 alleviates the injury of plasma etching composition for source electrode or drain electrode thus at the terminal point that this plasma dry ecthing is provided.
Yet aforementioned prior art still has some shortcomings to be needed further to improve and improve.Because aforesaid prior art is involved in silicon raceway groove below and uses germanium-silicon layer, and this germanium-silicon layer easily causes the generation of silicon layer defective, this kind defective is called helical dislocation (threading dislocation) again, and obviously has influence on rate of finished products.In addition, germanium-silicon layer deposits with whole wafer, makes that the indivedual adjustment of NMOS and PMOS or optimization are comparatively difficult.Another shortcoming then is that germanium-silicon layer has relatively poor thermal conductance.Moreover, because the germanium-silicon layer that is entrained in of part spreads comparatively fast, also cause the dopant profiles in source electrode or the drain region desirable not to the utmost.
Summary of the invention
Therefore, main purpose of the present invention makes it have preferred operation usefulness in that a kind of semiconductor MOS transistor unit manufacture method of making no silicon nitride gap wall is provided.
According to a first advantageous embodiment of the invention, the invention provides the method for a kind of making metal-oxide semiconductor (MOS) (MOS) transistor unit.The semiconductor-based end, at first be provided; On this semiconductor-based end, form gate dielectric; Form grid on this gate dielectric, this grid has sidewall and upper surface; On this sidewall of this grid, form laying; On this laying, form silicon nitride gap wall; Utilize this grid and this silicon nitride gap wall as injecting mask,, form the drain/source zone in these grid both sides thus carrying out the drain/source ion implantation technology in this semiconductor-based end; Remove this silicon nitride gap wall; Then, remove after this silicon nitride gap wall, on this drain/source zone, form metal silicide layer; Next, sedimentary cover on this laying and this metal silicide layer, this cap rock and this laying are directly bordered on, and this cap rock has specific stress state.
According to second preferred embodiment of the present invention, the invention provides the method for a kind of making CMOS (Complementary Metal Oxide Semiconductor) (CMOS) transistor unit.The semiconductor-based end, be provided equally, have nmos area territory and PMOS zone on it; Then, respectively in this nmos area territory, PMOS zone forms first grid and second grid; On the sidewall of this first grid and second grid, form laying; On this laying, form silicon nitride gap wall; Then, respectively ion implantation technology is carried out in this nmos area territory, PMOS zone, the N type is mixed and the P type mixes and injects respectively at this semiconductor-based end in this nmos area territory and this PMOS zone, form the drain/source zone thus; Then, remove this silicon nitride gap wall; After removing this silicon nitride gap wall, just carry out metal silicide technology, on this drain/source zone, form metal silicide layer.
According to the 3rd preferred embodiment of the present invention, the invention provides the method for a kind of making metal-oxide semiconductor (MOS) (MOS) transistor unit.Equally, provide the semiconductor-based end; Then, on this semiconductor-based end, form gate dielectric; Form grid then on this gate dielectric, this grid has sidewall and upper surface; Then on this sidewall of this grid, form laying; Deposited silicon nitride layer on this laying; Carry out dry etching process, this silicon nitride layer of etching and this semiconductor-based end, on this laying, forming silicon nitride gap wall, and at the other formation of this silicon nitride gap wall sunk area; Utilize this sunk area of semiconductor layer backfill; Utilize this grid and this silicon nitride gap wall as injecting mask,, form the drain/source zone in these grid both sides thus carrying out the drain/source ion implantation technology in this semiconductor-based end; Remove this silicon nitride gap wall; Then, remove after this silicon nitride gap wall, on this drain/source zone, form metal silicide layer.
In order to enable a nearlyer step understanding feature of the present invention and a technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 to Fig. 3 illustrated is the method generalized section that prior art is made the semiconductor MOS transistor unit.
Fig. 4 to Fig. 8 illustrates is the generalized section of method of the making semiconductor MOS transistor unit of first preferred embodiment of the invention.
What Fig. 9 to Figure 14 illustrated is a kind of generalized section of making the method for semiconductor CMOS transistors element of second preferred embodiment of the invention.
What Figure 15 to Figure 20 illustrated is a kind of generalized section of making the method for semiconductor CMOS transistors element of third preferred embodiment of the invention.
Description of reference numerals
2PMOS zone, 1NMOS zone
12 grids
14 gate dielectrics, 16 silicon layers
17 shallow junction source electrodes extend 18 source electrodes
20 drain electrodes are extended in the drain electrode of 19 shallow junctions
22 channel regions, 30 layings
32 silicon nitride gap walls, 34 thin oxide layers
42 metal silicide layers
46 silicon nitride cap rock 46a silicon nitride cap rocks
48 dielectric layers, 52 contact holes
60 ion implantation technologies, 68 mask layers
78 mask layers, 88 mask layers
112 grids
114 gate dielectrics, 116 silicon layers
117 shallow junction source electrodes extend 118 source electrodes
120 drain electrodes are extended in the drain electrode of 119 shallow junctions
122 channel regions, 130 layings
132 silicon nitride gap walls, 134 thin oxide layers
210 sunk areas, 220 sunk areas
310 silicon carbide layers, 320 germanium-silicon layers
Embodiment
Please refer to Fig. 4 to Fig. 8, what it illustrated is the generalized section that first preferred embodiment of the invention is made the method for semiconductor MOS transistor unit, wherein components identical or position are still continued to use identical symbol and are represented, are noted that diagram only for the purpose of description, do not map according to life size.In addition, in Fig. 4 to Fig. 8 for the part photoetching relevant and etching step with the present invention owing to be that those skilled in the art is known, so be not illustrated in the diagram especially.
The present invention is about a kind of MOS transistor element in the integrated circuit or method of cmos element of making.Earlier with MOS technology as an illustration, it can be applicable to NMOS technology or PMOS technology field among Fig. 4 to Fig. 8.
As shown in Figure 4, provide the semiconductor-based end earlier, it includes silicon layer 16.The aforesaid semiconductor-based end can be silicon base, epitaxial silicon, the semiconductor-based end of SiGe, silicon carbide substrate or silicon-coated insulated (silicon-on-insulator, SOI) substrate etc.At first, utilize photoetching and etch process, definition forms gate dielectric 14 and grid 12 on silicon layer 16, and wherein gate dielectric 14 can be silica layer, nitrogenize silica layer, silicon nitride layer or other dielectric constant high dielectric constant material greater than silicon dioxide, for example, HfSiNO or ZrO
2Deng.On the sidewall of grid 12, form silica laying 30 then, then carry out ion implantation technology, form the shallow junction source electrode and extend (shallow junction sourceextension) 17 and shallow junction drain electrode extension (shallow junction drain extension) 19 in silicon layer 16, wherein extension 17 of shallow junction source electrode and shallow junction drain electrode are channel region 22 between extending 19.In addition, grid 12 can be polysilicon or metal gates.
Then, deposited silicon nitride layer on silica laying 30 (figure does not show) is then carried out the etch-back step, and this silicon nitride layer of etching forms silicon nitride gap wall 32 thus on grid 12 sidewalls.According to a preferred embodiment of the invention, the thickness of silicon nitride gap wall 32 bottoms is approximately between 300 to 600 dusts.
Then, carry out ion implantation technology 60, inject the silicon layer 16 on silicon nitride gap wall 32 sides, form source electrode 18 and drain electrode 20 mixing.Be noted that the etching step of aforementioned formation silicon nitride gap wall 32 stops at silica laying 30, therefore, have thin oxide layer 34 on the surface of source electrode 18 and drain electrode 20, its thickness is about between 30 to 40 dusts.
In addition, silicon nitride gap wall 32 also can by silicon oxynitride (silicon oxy-nitride, SiON) or carborundum (silicon carbide SiC) replaces, and is not limited only to silicon nitride.
Then, as shown in Figure 5, carry out etch process, it can be wet etching or dry etching process, for example, utilizes diluent hydrofluoric acid solution, etches away at the lip-deep thin oxide layer 34 of source electrode 18 with drain electrode 20, exposes the surface of source electrode 18 and drain electrode 20 thus.
As shown in Figure 6, after removing thin oxide layer 34, then carry out another etch process, it can be wet etching, dry ecthing or gas etch method, for example, utilize hot phosphoric acid solution (hot phosphoricacid solution), the silicon nitride gap wall 32 on grid 12 sidewalls is etched away fully, make only remaining silica laying 30 on grid 12 sidewalls.
Wherein, if etching of silicon nitride clearance wall 32 uses is dry ecthing method, then can utilize be mixed with hydrogen fluoride (hydrogen fluoride, the HF) gas of gas and gaseous oxidizer, aforesaid oxidant, for example, nitric acid (HNO
3), ozone (O
3), hydrogen peroxide (H
2O
2), hypochlorous acid (HClO), chloric acid (HClO
3), nitrous acid (HNO
2), oxygen (O
2), sulfuric acid (H
2SO
4), chlorine (Cl
2) or bromine (Br
2).
If using gases etching method etching of silicon nitride clearance wall 32 then can utilize the hydrogen halides that anhydrates (anhydrous hydrogen halogenide), for example hydrogen fluoride or hydrogen chloride (HCl) gas.
As shown in Figure 7, after etching away silicon nitride gap wall 32, then, carry out metal silicide technology, in the source region and drain region or on grid, form metal silicide layer 42, for example, nickle silicide (NiSi), cobalt silicide (CoSi), titanium silicide (TiSi), molybdenum silicide (SiMo), palladium silicide (SiPd) and platinum silicide (SiPt) or the like.Key character of the present invention is all do not have silicon nitride gap wall on the gate lateral wall, and on step, remove after the silicon nitride gap wall 32 earlier, on the sidewall of grid 12, stay the laying 30 of the rough L of being type, then, just carry out metal silicide technology, form metal silicide layer 42, thus, in the time of promptly can avoiding etching of silicon nitride clearance wall 32, hurt metal silicide layer 42.
As shown in Figure 8, follow deposited silicon nitride cap rock 46a, its thickness is preferably between 30 to 2000 dusts.Because silicon nitride gap wall 32 has been removed, silicon nitride cap rock 46a therefore with grid 12 sidewalls on laying 30 directly border on.According to the present invention, silicon nitride cap rock 46a sets earlier when deposition and is deposited on predetermined stress state, for example, for the NMOS element, this predetermined stress state is elongation strain (tensile-stressed) state, and stress intensity is about between the 0.1Gpa to 3Gpa, and for the PMOS element, this predetermined stress state is compression strain (compressive-stressed) state, and stress intensity is about-and 0.1Gpa is between-the 3Gpa.
Follow dielectric layer 48 on the semiconductor-based end, it covers silicon nitride cap rock 46.Aforesaid dielectric layer 48 can be silica, doped silicon oxide or advanced low-k materials or the like.In addition, according to another embodiment of the present invention, dielectric layer 48 also has different specific stress states, for example, and elongation strain state or compression strain state.According to spirit of the present invention, silicon nitride cap rock 46a also plays the part of the role of etching stopping layer in follow-up contact hole dry ecthing, alleviate the injury of plasma etching composition for source electrode or drain electrode thus.
Next, please refer to Fig. 9 to Figure 14, what it illustrated is a kind of generalized section of making the method for semiconductor CMOS transistors element of second preferred embodiment of the invention, and wherein components identical or position are still continued to use identical symbol and represented.
As shown in Figure 9, preparation earlier includes the semiconductor-based end of silicon layer 16, and wherein nmos area territory 1 is the zone in order to making NMOS element, and PMOS zone 2 is then in order to make the PMOS element.The aforesaid semiconductor-based end can be silicon base, epitaxial silicon, the semiconductor-based end of SiGe, silicon carbide substrate or silicon-coated insulated (SOI) substrate etc.In zone 1, be formed with extension 17 of shallow junction source electrode and shallow junction drain electrode extension 19 in the silicon layer 16, be N raceway groove 22 between extension 17 of shallow junction source electrode and the shallow junction drain electrode extension 19 wherein.Being formed with extension 117 of shallow junction source electrode and shallow junction drain electrode extension 119 in the silicon layer 16 in zone 2, is P raceway groove 122 between extension 117 of shallow junction source electrode and the shallow junction drain electrode extension 119 wherein.
Be formed with grid oxic horizon 14 and 114 and grid 12 and 112 on raceway groove 22 and 122 respectively, wherein grid 12 and 112 includes polysilicon usually.Grid oxic horizon 14 and 114 can be made of silicon dioxide.Yet, in other embodiment of the present invention, grid oxic horizon 14 and 114 is made of other high-k (high-k) material, for example, and the silica layer of via nitride (nitrided oxide), nitride, nitrogen-oxygen-silicon hafnium compound (HfSiNO) or zirconia (ZrO
2) etc.
As shown in figure 10, after forming silicon nitride gap wall 32 and 132, utilize mask layer 68 that zone 2 is covered as materials such as photoresists.Then carry out ion implantation technology,, for example in the silicon layer 16 in the injection zones such as arsenic, antimony or phosphorus 1, form the source region 18 and the drain region 20 of NMOS element thus N type dopant species.Finish after the aforesaid ion implantation technology, mask layer 68 is divested immediately.
As shown in figure 11, with similar method, on zone 1, utilize mask layer 78 as materials such as photoresists with its covering.Then carry out another ion implantation technology,, for example in the silicon layer 16 in the injection zone such as boron 2, form the source region 118 and the drain region 120 of PMOS element thus P type dopant species.Finish after the aforesaid ion implantation technology, mask layer 78 is divested immediately.One skilled in the art should appreciate that aforementioned ion injection order as shown in Figure 10 and Figure 11 can put upside down, in other words, the P types that can carry out earlier in the zone 2 mix, and then the N type that carries out in the zone 1 mixes.
In addition, after the doping of finishing drain-source, can anneal usually (annealing) again or activate the thermal process that (activation) mixes, this step also is that those skilled in the art is known, is no longer stated.
Then, as shown in figure 12, carry out etch process, it can be wet etching or dry etching process, for example, utilizes diluent hydrofluoric acid solution, etches away at the lip-deep thin oxide layer 34 and 134 of source electrode 18 with drain electrode 20, exposes the surface of source electrode and drain electrode thus.
After removing thin oxide layer 34 and 134, then carry out another etch process, it can be wet etching, dry ecthing or gas etch method, for example, utilize hot phosphoric acid solution (hot phosphoric acidsolution), silicon nitride gap wall 32 and 132 on grid 12 sidewalls is etched away fully, make only remaining silica laying 30 and 130 on grid 12 and 112 sidewalls.
Wherein,, then can utilize the gas that is mixed with hydrogen fluoride (HF) gas and gaseous oxidizer if etching of silicon nitride clearance wall 32 and 132 uses is dry ecthing method, aforesaid oxidant, for example, nitric acid (HNO
3), ozone (O
3), hydrogen peroxide (H
2O
2), hypochlorous acid (HClO), chloric acid (HClO
3), nitrous acid (HNO
2), oxygen (O
2), sulfuric acid (H
2SO
4), chlorine (Cl
2) or bromine (Br
2).
If using gases etching method etching of silicon nitride clearance wall 32 and 132 then can utilize the hydrogen halides that anhydrates, for example hydrogen fluoride or hydrogen chloride (HCl) gas.
As shown in figure 13, then carry out metal silicide technology, the source region of nmos pass transistor element and PMOS transistor unit, drain region, and grid on form metal silicide layer 42, for example, nickle silicide (NiSi), cobalt silicide (CoSi), titanium silicide (TiSi), molybdenum silicide (SiMo), palladium silicide (SiPd) and platinum silicide (SiPt) or the like.
The invention is characterized on the gate lateral wall of nmos pass transistor element and PMOS transistor unit and all do not have silicon nitride gap wall, the laying 30 and 130 that the rough L of being type is only arranged on gate lateral wall, and on step, remove earlier after the silicon nitride gap wall 32 and 132, the beginning is carried out metal silicide technology.In addition, laying 30 and 130 not necessarily is the L type, can also carry out relatively mild etch process, omits the microetch laying, to reduce its thickness person.In other embodiments, laying 30 and 130 can be removed fully.
Then, deposited silicon nitride cap rock 46a, its thickness are preferably between 30 to 2000 dusts.Because silicon nitride gap wall 32 and 132 has been removed, therefore silicon nitride cap rock 46a must directly border on the grid 12 of nmos pass transistor element and PMOS transistor unit and the laying 30 and 130 on 112 sidewalls.According to second preferred embodiment of the invention, silicon nitride cap rock 46a sets earlier in when deposition and is deposited on first stress state, and as compression strain (compressive-stressed) state, its stress intensity is about-and 0.1Gpa is between-the 3Gpa.So, make channel region 122 be subjected to the compression stress effect of silicon nitride cap rock 46a.Then, the silicon nitride cap rock 46a that utilizes mask layer 88 will be positioned at zone 2 covers.
Then, the stress state of the silicon nitride cap rock 46a that not masked layer 88 covers change to second stress state, it is opposite with first stress state, that is to say, silicon nitride cap rock 46a in the zone 2 is the compression strain state, then second stress state is elongation strain (tensile-stressed) state, and its stress intensity is about between the 0.1Gpa to 3Gpa.So, make channel region 22 be subjected to the tensile stress effect of silicon nitride cap rock 46a.
According to a preferred embodiment of the invention, the method that changes the stress state of the silicon nitride cap rock 46a in the zone 1 can utilize germanium (Ge) ion to inject.Yet, one skilled in the art should appreciate that changing zone 1 interior silicon nitride cap rock 46a stress state can also utilize other method that can reach identical purpose to carry out.
As shown in figure 14, follow dielectric layer 48 on the semiconductor-based end, it covers the silicon nitride cap rock 46a in zone 1 and the zone 2.Aforesaid dielectric layer 48 can be silica, doped silicon oxide or advanced low-k materials or the like.In addition, according to another embodiment of the present invention, dielectric layer 48 also has different specific stress states, and for example, the dielectric layer 48 in the zone 1 is at the elongation strain state, and the dielectric layer 48 in the zone 2 is at the compression strain state.
Then, carry out known photoetching and etch process, in dielectric layer 48 and silicon nitride cap rock 46a, form contact hole 52, its sensible nmos pass transistor element and drain electrode of PMOS transistor unit or source region.In other embodiments, also can form the contact hole of sensible grid simultaneously, but in diagram, not express.According to spirit of the present invention, silicon nitride cap rock 46a also plays the part of the role of contact etch stop layer except providing the stress in aforesaid contact hole dry ecthing, alleviate the injury of plasma etching composition for source electrode or drain electrode thus.
Next, please refer to Figure 15 to Figure 20, what it illustrated is a kind of generalized section of making the method for semiconductor CMOS transistors element of third preferred embodiment of the invention, and wherein components identical or position are still continued to use identical symbol and represented.
As shown in figure 15, prepare to include the semiconductor-based end of silicon layer 16 earlier, same, zone 1 is in order to make the zone of NMOS element, and zone 2 is then in order to make the PMOS element.The aforesaid semiconductor-based end can be silicon base, epitaxial silicon, the semiconductor-based end of SiGe, silicon carbide substrate or silicon-coated insulated (SOI) substrate etc.In zone 1, be formed with extension 17 of shallow junction source electrode and shallow junction drain electrode extension 19 in the silicon layer 16, be N raceway groove 22 between extension 17 of shallow junction source electrode and the shallow junction drain electrode extension 19 wherein.Being formed with extension 117 of shallow junction source electrode and shallow junction drain electrode extension 119 in the silicon layer 16 in zone 2, is P raceway groove 122 between extension 117 of shallow junction source electrode and the shallow junction drain electrode extension 119 wherein.
Be formed with grid oxic horizon 14 and 114 and grid 12 and 112 on raceway groove 22 and 122 respectively, wherein grid 12 and 112 includes polysilicon usually.Grid oxic horizon 14 and 114 can be made of silicon dioxide.Yet, in other embodiment of the present invention, grid oxic horizon 14 and 114 is made of other high-k (high-k) material, for example, and the silica layer of via nitride (nitrided oxide), nitride, nitrogen-oxygen-silicon hafnium compound (HfSiNO) or zirconia (ZrO
2) etc.
Laying 30 and 130 are arranged between grid and silicon nitride gap wall in addition.Aforesaid laying can be constituted by silica, is generally L type and thickness between 30 to 120 dusts.On the sidewall of grid 12 and 112, then form silicon nitride gap wall 32 and 132.Form the method elder generation deposited silicon nitride layer (figure does not show) of silicon nitride gap wall 32 and 132, then carry out dry etching steps, this silicon nitride layer of etching.Silicon nitride gap wall 32 and 132 dry etching steps eating thrown silica laying 30, and continue etch silicon layer 16 to desired depth, for example between 20 to 300 dusts, the side in silicon nitride gap wall 32 and 132 forms sunk area (recessed area) 210 and 220 thus.
As shown in figure 16, insert semiconductor layers such as silicon carbide layer 310 and germanium-silicon layer 320 in the sunk area 220 in the sunk area 210 and regional 2 of zone in 1 respectively.
As shown in figure 17, utilize mask layer 68 that zone 2 is covered as materials such as photoresists.Then carry out ion implantation technology,, for example in the silicon layer 16 in the injection zones such as arsenic, antimony or phosphorus 1, form the source region 18 and the drain region 20 of NMOS element thus N type dopant species.Finish after the aforesaid ion implantation technology, mask layer 68 is divested immediately.
As shown in figure 18, with similar method, on zone 1, utilize mask layer 78 as materials such as photoresists with its covering.Then carry out another ion implantation technology,, for example in the silicon layer 16 in the injection zone such as boron 2, form the source region 118 and the drain region 120 of PMOS element thus P type dopant species.Finish after the aforesaid ion implantation technology, mask layer 78 is divested immediately.One skilled in the art should appreciate that aforementioned ion injection order as shown in Figure 17 and Figure 18 can put upside down, in other words, the P types that can carry out earlier in the zone 2 mix, and then the N type that carries out in the zone 1 mixes.
In addition, after the doping of finishing drain-source, can anneal or activate the thermal process of doping usually again, this step also is that those skilled in the art is known, is no longer stated.
Then, as shown in figure 19, carry out etch process, it can be wet etching, dry ecthing or gas etch method, for example, utilizes hot phosphoric acid solution, silicon nitride gap wall 32 and 132 on grid 12 sidewalls is etched away fully, make only remaining silica laying 30 and 130 on grid 12 and 112 sidewalls.
Wherein,, then can utilize the gas that is mixed with hydrogen fluoride gas and gaseous oxidizer if etching of silicon nitride clearance wall 32 and 132 uses is dry ecthing method, aforesaid oxidant, for example, nitric acid (HNO
3), ozone (O
3), hydrogen peroxide (H
2O
2), hypochlorous acid (HClO), chloric acid (HClO
3), nitrous acid (HNO
2), oxygen (O
2), sulfuric acid (H
2SO
4), chlorine (Cl
2) or bromine (Br
2).
If using gases etching method etching of silicon nitride clearance wall 32 and 132 then can utilize the hydrogen halides that anhydrates, for example hydrogen fluoride or hydrogen chloride gas.
As shown in figure 20, then carry out metal silicide technology, the source region of nmos pass transistor element and PMOS transistor unit, drain region, and grid on form metal silicide layer 42, for example, nickle silicide, cobalt silicide, titanium silicide, molybdenum silicide, palladium silicide and platinum silicide or the like.
Then, deposited silicon nitride cap rock 46a, its thickness are preferably between 30 to 2000 dusts.Because silicon nitride gap wall 32 and 132 has been removed, therefore silicon nitride cap rock 46a must directly border on the grid 12 of nmos pass transistor element and PMOS transistor unit and the laying 30 and 130 on 112 sidewalls.According to third preferred embodiment of the invention, silicon nitride cap rock 46a the time can set in deposition and be deposited on first stress state, and as the compression strain state, its stress intensity is about-and 0.1Gpa is between-the 3Gpa.So, make P channel region 122 be subjected to the compression stress effect of silicon nitride cap rock 46a.
Then, the stress state of silicon nitride cap rock 46a in the zone 1 is change to second stress state, it is opposite with first stress state, that is to say, silicon nitride cap rock 46a in the zone 2 is the compression strain state, then second stress state is the elongation strain state, and its stress intensity is about between the 0.1Gpa to 3Gpa.So, make N channel region 22 be subjected to the tensile stress effect of silicon nitride cap rock 46a.
Compared to prior art, the invention has the advantages that the nmos pass transistor element covers with the silicon nitride cap rock under the elongation strain state, and the PMOS transistor unit covers with the silicon nitride cap rock under the compression strain state, adjusts the characteristic of NMOS element and PMOS element thus respectively.
In addition, because the present invention removes the silicon nitride gap wall on the gate lateral wall, therefore aforesaid silicon nitride cap rock can cause the saturation current increase and make element operation usefulness obtain obviously to improve comparatively near the raceway groove 22 and 122 of NMOS and PMOS transistor unit.On step, remove after the silicon nitride gap wall earlier, just carry out metal silicide technology, form metal silicide layer, thus, in the time of promptly can avoiding the etching of silicon nitride clearance wall, hurt metal silicide layer.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (31)
1. method of making metal-oxide semiconductor transistor component includes:
The semiconductor-based end, be provided;
On this semiconductor-based end, form gate dielectric;
Form grid on this gate dielectric, this grid has sidewall and upper surface;
On this sidewall of this grid, form laying;
On this laying, form silicon nitride gap wall;
Utilize this grid and this silicon nitride gap wall as injecting mask,, form the drain/source zone in these grid both sides thus carrying out the drain/source ion implantation technology in this semiconductor-based end;
Remove this silicon nitride gap wall; And
Remove after this silicon nitride gap wall, on this drain/source zone, form a metal silicide layer.
2. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein, this method is after carrying out this drain/source ion implantation technology and before removing this silicon nitride gap wall, and other includes following step:
Carry out etch process, remove the silica layer on this drain/source region surface.
3. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein, this method forms after this metal silicide layer on this drain/source zone, and other includes following step:
Sedimentary cover on this laying and this metal silicide layer, this cap rock and this laying are directly bordered on, and this cap rock has specific stress state.
4. the method for making metal-oxide semiconductor transistor component as claimed in claim 3, wherein the thickness of this cap rock is between 30 to 2000 dusts.
5. the method for making metal-oxide semiconductor transistor component as claimed in claim 3, wherein this cap rock when the etching contact hole as etching stopping layer.
6. the method for making metal-oxide semiconductor transistor component as claimed in claim 3, wherein this metal-oxide semiconductor transistor component is a N type metal oxide semiconductor transistor unit, and this cap rock is at the elongation strain state.
7. the method for making metal-oxide semiconductor transistor component as claimed in claim 3, wherein this metal-oxide semiconductor transistor component is the P-type mos transistor unit, and this cover layer is at the compression strain state.
8. the method for making metal-oxide semiconductor transistor component as claimed in claim 3, wherein this cover layer includes silicon nitride.
9. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this laying includes silica.
10. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this method also includes the step of being annealed in this drain/source zone.
11. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this metal silicide layer includes nickle silicide, cobalt silicide, titanium silicide, molybdenum silicide, palladium silicide and platinum silicide.
12. the method for making metal-oxide semiconductor transistor component as claimed in claim 1, wherein this grid includes polysilicon and metal.
13. the method for making metal-oxide semiconductor transistor component as claimed in claim 1 wherein after this silicon nitride gap wall forms, also includes following steps:
Form sunk area by this silicon nitride gap wall; And
Utilize this sunk area of silicon epitaxial layers backfill.
14. the method for making metal-oxide semiconductor transistor component as claimed in claim 13, wherein this metal-oxide semiconductor transistor component is a N type metal oxide semiconductor transistor, and this silicon epitaxial layers is a silicon carbide layer.
15. the method for making metal-oxide semiconductor transistor component as claimed in claim 13, wherein this metal-oxide semiconductor transistor component is the P-type mos transistor, and this silicon epitaxial layers is a germanium-silicon layer.
16. the method for making metal-oxide semiconductor transistor component as claimed in claim 1 is wherein removed this silicon nitride gap wall and is utilized wet etch method, dry ecthing method or gas etch method.
17. the method for making metal-oxide semiconductor transistor component as claimed in claim 16, wherein this wet etch method utilizes hot phosphoric acid solution.
18. the method for making metal-oxide semiconductor transistor component as claimed in claim 16, wherein this dry ecthing method utilization is mixed with the gas of hydrogen fluoride gas and gaseous oxidizer.
19. the method for making metal-oxide semiconductor transistor component as claimed in claim 18, wherein this gaseous oxidizer includes nitric acid, ozone, hydrogen peroxide, hypochlorous acid, chloric acid, nitrous acid, oxygen, sulfuric acid, chlorine or bromine.
20. the method for making metal-oxide semiconductor transistor component as claimed in claim 16, wherein this gas etch method utilization hydrogen halides that anhydrates comprises hydrogen fluoride or hydrogen chloride gas.
21. the method for making metal-oxide semiconductor transistor component as claimed in claim 1 wherein, after this silicon nitride gap wall forms, also is included in the other silicon epitaxial layers that forms of this silicon nitride gap wall.
22. a method of making the CMOS (Complementary Metal Oxide Semiconductor) transistor element includes:
The semiconductor-based end, be provided, have N type metal oxide semiconductor zone and P-type mos zone on it;
Respectively in this N type metal oxide semiconductor zone, P-type mos zone forms first grid and second grid;
On the sidewall of this first grid and second grid, form laying;
On this laying, form silicon nitride gap wall;
Carry out ion implantation technology, with this semiconductor-based end in the doping of N type and this N type metal oxide semiconductor zone of P type doping injection and this P-type mos zone, form the drain/source zone thus respectively;
Remove this silicon nitride gap wall; And
Remove after this silicon nitride gap wall, carry out metal silicide technology, on this drain/source zone, to form metal silicide layer.
23. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22, wherein, this method forms after this metal silicide layer on this drain/source zone, also includes following step:
On this N type metal oxide semiconductor zone, form the elongation strain cap rock, and this elongation strain cap rock and this laying are bordered on directly; And
On this P-type mos zone, form the compression strain cap rock.
24. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 23, wherein this elongation strain cap rock and this compression strain cap rock include silicon nitride.
25. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22, wherein this laying includes silica.
26. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22, wherein this method also includes the step of being annealed in this drain/source zone.
27. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22, wherein this metal silicide layer includes nickle silicide, cobalt silicide, titanium silicide, molybdenum silicide, palladium silicide and platinum silicide.
28. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22, wherein this grid includes polysilicon and metal.
29. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22 is wherein removed this silicon nitride gap wall and is utilized wet etch method, dry ecthing method or gas etch method.
30. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22 wherein, after this silicon nitride gap wall forms, also is included in the other silicon epitaxial layers that forms of this silicon nitride gap wall.
31. the method for making CMOS (Complementary Metal Oxide Semiconductor) transistor element as claimed in claim 22, wherein after this silicon nitride gap wall formed, other included following steps:
Form sunk area by this silicon nitride gap wall; And
Utilize this sunk area of silicon epitaxial layers backfill.
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| CN102136455A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing complementary metallic oxide semiconductor device |
| WO2012088779A1 (en) * | 2010-12-31 | 2012-07-05 | 中国科学院微电子研究所 | Metal oxide semiconductor (mos) transistor and manufacturing method thereof |
| CN103325787A (en) * | 2012-03-21 | 2013-09-25 | 中国科学院微电子研究所 | CMOS device and method for fabricating the same |
| CN103681337A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and forming method thereof |
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| TWI548001B (en) * | 2011-06-22 | 2016-09-01 | 聯華電子股份有限公司 | Method for fabricating metal-oxide-semiconductor field-effect transistor |
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| WO2012088779A1 (en) * | 2010-12-31 | 2012-07-05 | 中国科学院微电子研究所 | Metal oxide semiconductor (mos) transistor and manufacturing method thereof |
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| CN103325787A (en) * | 2012-03-21 | 2013-09-25 | 中国科学院微电子研究所 | CMOS device and method for fabricating the same |
| CN103325787B (en) * | 2012-03-21 | 2017-05-03 | 中国科学院微电子研究所 | CMOS device and method for fabricating the same |
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| CN103681337A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and forming method thereof |
| CN103681337B (en) * | 2012-09-18 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Fin formula field effect transistor and forming method thereof |
| CN104900514A (en) * | 2015-06-29 | 2015-09-09 | 上海华力微电子有限公司 | Side wall forming method |
| CN108231766A (en) * | 2016-12-14 | 2018-06-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN108231766B (en) * | 2016-12-14 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN109427682A (en) * | 2017-08-30 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Semiconductor element and forming method thereof |
| CN109427682B (en) * | 2017-08-30 | 2021-05-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
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