CN103730422B - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- CN103730422B CN103730422B CN201210393777.XA CN201210393777A CN103730422B CN 103730422 B CN103730422 B CN 103730422B CN 201210393777 A CN201210393777 A CN 201210393777A CN 103730422 B CN103730422 B CN 103730422B
- Authority
- CN
- China
- Prior art keywords
- layer
- gate electrode
- dummy gate
- stress layer
- tensile stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 116
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000011241 protective layer Substances 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims abstract description 12
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 230000006835 compression Effects 0.000 claims description 13
- 238000007906 compression Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000011800 void material Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 15
- 230000007797 corrosion Effects 0.000 abstract description 8
- 238000005260 corrosion Methods 0.000 abstract description 8
- 238000001039 wet etching Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a stress semiconductor manufacturing method. Firstly, forming a tensile stress layer in an NMOS region to form a compressive stress layer in a PMOS region, depositing TEOS and carrying out planarization treatment, and then, comprehensively depositing a protective layer; the protective layer is photoetched and etched by adopting a grid line mask, the dummy grid is opened, and the protective layer is completely covered on the tensile stress layer and the pressure stress layer, and the corrosion rate of the protective layer in wet etching liquid is low, so that the tensile stress layer and the pressure stress layer cannot be damaged at all, and the defects in the prior art are overcome; and then, after a grid electrode groove is formed, manufacturing of the high-K grid insulating layer and the metal grid electrode is completed, and process integration of a gate-last process and a double strain stress layer is achieved.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method field, especially, it is related to a kind of applied to grid technique after CMOS
The integrated approach of double strain stress layers.
Background technology
Semiconductor integrated circuit technology maintains or improved transistor after the technology node of 90nm characteristic sizes is entered
Can be more and more challenging.After 90nm nodes, stress technique is gradually used to improve the performance of device.Concurrently,
In terms of manufacturing process, the high-K metal gate technology in rear grid technique (gate last) also is gradually used to tackle with device
The challenge for constantly reducing and bringing.In stress technique, double strain stresses layer (DSL, dual stress liner) technology with often
Advise processing compatibility height, cost relatively low, therefore, used by major semiconductor manufacturers.
DSL technologies, are referred in different types of MOSFET region, and formed has tensile stress and the stress of compression respectively
Layer, generally, in NMOS area formation tensile stress layer, in PMOS area formation compressive stress layer.Referring to accompanying drawing 1, figure is to employ DSL
A step in the CMOS manufacturing process of technology.Wherein, on substrate 1, NMOS 2 and PMOS3, different MOS crystal are formed with
Pipe is kept apart by sti structure 4.NMOS 2 includes NMOS dummy gate electrodes 6 and its dummy gate electrode insulating barrier 5, and PMOS 3 includes PMOS
Dummy gate electrode 8 and its dummy gate electrode insulating barrier 7, dummy gate electrode (dummy gate) and its dummy gate electrode insulating barrier are used for rear grid
Technique, dummy gate electrode is usually polysilicon or non-crystalline silicon grid, and dummy gate electrode insulating barrier is usually silicon oxide layer, completes crystal
After pipe miscellaneous part, dummy gate electrode and its dummy gate electrode insulating barrier are removed, gate recess is formed, then the shape in gate recess
Into high K gate insulation layers and metal gates.On NMOS 2 covered with tensile stress layer 9, PMOS 3 on covered with compressive stress layer 10,
Stress layer material is usually silicon nitride.Both stressor layers provide stress to NMOS and PMOS channel region respectively, to increase
The mobility of channel region carrier, it is ensured that performance of the transistor in deep-submicron field.Then in, thereafter the step of, need
Open dummy gate electrode.Current method is, after stressor layers are formed, deposition TEOS layers 20, and CMP is then carried out again, opens empty
If grid, referring to accompanying drawing 2, dummy gate electrode and dummy gate electrode insulating barrier are then removed, however, using asking that this method is faced
Topic is exactly：Dummy gate electrode insulating barrier is usually silica, and removing method is DHF wet etchings, specifically, and at room temperature (23
Degree Celsius), the speed of 1: 100 DHF corrosion oxidation silicon is 30 ± 1 angstrom mins, but at the same time tensile stress silicon nitride exists
Corrosion rate is 498 angstrom mins in the DHF of this condition, much larger than corrosion rate of the silica in DHF, due to being had after CMP
A part of tensile stress layer 9 is exposed and not covered by TEOS layers 20, referring to position shown in dotted line circle in Fig. 2, so, is removing
When illusory gate insulation layer, the tensile stress layer 9 exposed is corroded to form hole, referring to accompanying drawing 3, if not solving this
Individual problem may result in cause in follow-up high-K metal gate technique hafnium and metal gate material be filled into hole so as to
The deterioration of device performance is caused, simultaneously as stressor layers are lost, the integrated failures of DSL are result in.
Accordingly, it is desirable to provide a kind of integrated approach of the new double strain stresses for being applied to grid technique after CMOS layer, can
Overcome drawbacks described above.
The content of the invention
The present invention provides a kind of manufacture method of transistor, by the use of the material layer being additionally formed as protective layer, and uses
Gate lithography version carries out photoetching, it is to avoid the defect of tensile stress layer loss in the prior art.
According to an aspect of the present invention, the present invention provides a kind of method, semi-conductor device manufacturing method, in rear grid technique
Double strain stresses layer it is integrated, it comprises the following steps：
Semiconductor substrate is provided, sti structure is formed in the Semiconductor substrate, and carries out well region injection, nmos area is formed
Domain and PMOS area；
Nmos pass transistor and PMOS transistor are formed, the nmos pass transistor and the PMOS transistor include dummy gate electrode
With dummy gate electrode insulating barrier, the dummy gate electrode is by grid lines lithography layout case；
Tensile stress layer is formed on the nmos pass transistor, compressive stress layer is formed on the PMOS transistor；
CMP, the upper surface of the exposure dummy gate electrode are carried out, and makes the dummy gate electrode, tensile stress layer, institute
The upper surface for stating compressive stress layer is in same plane；
Comprehensive deposition protective layer；
Photoetching and etching are carried out to the protective layer with grid lines reticle, removes and is located at the dummy gate electrode upper surface
The protective layer, expose the dummy gate electrode upper surface；
The dummy gate electrode and the dummy gate electrode insulating barrier are removed successively, form gate recess；
In the gate recess, the nmos pass transistor and the high K gate insulation layers of the PMOS transistor are formed respectively
And metal gates.
According to an aspect of the present invention, form nmos pass transistor and PMOS transistor is specifically included：
Form the dummy gate electrode and the dummy gate electrode insulating barrier；
Form grid gap wall；
Form the source and drain areas of transistor.
According to an aspect of the present invention, tensile stress layer is formed on the nmos pass transistor to specifically include：
Deposited overall tensile stress silicon nitride film, is located at described in the nmos pass transistor with the photoresist layer protection of patterning
Tensile stress silicon nitride film, removes the tensile stress silicon nitride film positioned at the PMOS transistor, then removes photoresist layer, shape
Into tensile stress layer.
According to an aspect of the present invention, compressive stress layer is formed on the PMOS transistor to specifically include：
Deposited overall compression silicon nitride film, is located at described in the PMOS transistor with the photoresist layer protection of patterning
Compression silicon nitride film, removes the compression silicon nitride film positioned at the nmos pass transistor, then removes photoresist layer, shape
Into the compressive stress layer.
According to an aspect of the present invention, the protective layer is silica, compression silicon nitride or unstressed silicon nitride, thickness
Spend for 100 angstroms.
According to an aspect of the present invention, before CMP, comprehensive deposition TEOS layers.
The advantage of the invention is that：First in NMOS area formation tensile stress layer and in PMOS area formation compression
Layer, deposits TEOS and carries out planarization process, then deposited overall protective layer；Protective layer is carried out using grid lines mask
Photoetching and etching, open dummy gate electrode, due to completely covers protective layer on tensile stress layer and compressive stress layer, and protect
Corrosion rate very little of the layer in wet etching liquid, therefore tensile stress layer and compressive stress layer will not overcome by any damage
Defect of the prior art；Then, formed after gate recess, complete high K gate insulation layers and metal gates manufacture, realize rear grid
Technique and the technique of double strain stress layers are integrated.
Brief description of the drawings
The integrated approach of the double strain stress layers of the existing rear grid techniques of Fig. 1-3；
The integrated approach of the double strain stress layers of rear grid technique of Fig. 4-9 present invention.
Embodiment
Hereinafter, the present invention is described by the specific embodiment shown in accompanying drawing.However, it should be understood that these descriptions are
Exemplary, and it is not intended to limit the scope of the present invention.In addition, in the following description, eliminate to known features and technology
Description, to avoid unnecessarily obscuring idea of the invention.
The present invention provides a kind of method, semi-conductor device manufacturing method, particularly a kind of transistor of utilization gap wall technique
Manufacture method, referring to accompanying drawing 4-9, will be described in detail the method, semi-conductor device manufacturing method that the present invention is provided.
First, referring to accompanying drawing 4, on semiconductor substrate 1, NMOS 2 and PMOS 3, different MOS transistor quilts are formed with
Sti structure 4 is kept apart.Wherein, monocrystalline substrate is employed in the present embodiment, alternatively, also can using germanium substrate or other
Suitable Semiconductor substrate.The method for forming sti structure 4 on semiconductor substrate 1 is specifically included, first in Semiconductor substrate 1
Upper coating photoresist, then makes the figure of sti structure 4 by lithography, and anisotropic etching acquisition shallow ridges is carried out to Semiconductor substrate 1
Groove, such as filled dielectric material in the shallow trench, SiO2, so as to form sti structure.After sti structure 4 is formed, trap is carried out
(being not shown) is injected in area, forms NMOS area and PMOS area.PMOS well region implanted dopant is N-type impurity, and
NMOS well region implanted dopant is p type impurity.
Then, NMOS dummy gate electrodes 6 and its dummy gate electrode insulating barrier 5 are formed, PMOS dummy gate electrodes 8 and its dummy gate electrode are exhausted
Edge layer 7.Specifically include：First one layer of dummy gate electrode insulating layer material, e.g. SiO are deposited on the surface of substrate 12, its thickness is preferred
For 0.5-10nm, depositing operation is, for example, CVD.Afterwards, dummy gate electrode material, after the present invention in grid technique, illusory grid are deposited
Pole material is, for example, polysilicon or non-crystalline silicon.In addition, being also formed with hard mask layer (not shown) on dummy gate electrode material layer.So
Afterwards, photoresist coating is carried out, photoetching is carried out with grid lines reticle, dummy gate electrode figure is defined, to dummy gate electrode material
And dummy gate electrode insulating layer material order is etched, so that the dummy gate electrode and its dummy gate electrode that form NMOS and PMOS simultaneously are exhausted
Edge layer.Dummy gate electrode (dummy gate) and its dummy gate electrode insulating barrier are used for rear grid technique, complete other portions of transistor
After part, dummy gate electrode and its dummy gate electrode insulating barrier are removed, gate recess is formed, high K grid is then formed in gate recess
Insulating barrier and metal gates.
Formed after dummy gate electrode lines, grid gap wall is formed, by the way of depositing and being etched back to.Afterwards, difference shape
Into NMOS and PMOS source and drain areas, it can also can be carried out by the way of ion implanting first by mask of dummy gate electrode
Self aligned source and drain areas etching, forms source and drain areas groove, source and drain areas epitaxial growth is then carried out, so as to form transistor
Source and drain areas.
Afterwards, tensile stress layer 9 is formed on NMOS 2.Specifically include：Deposited overall tensile stress silicon nitride film first, so
The tensile stress silicon nitride film in the regions of NMOS 2 is protected with the photoresist layer of patterning afterwards, the tensile stress nitridation in the regions of PMOS 3 is removed
Silicon fiml, then removes photoresist layer, forms tensile stress layer 9.The thickness of tensile stress layer 9 is h1。
Afterwards, compressive stress layer 10 is formed on PMOS 3.Specifically include：Deposited overall compression silicon nitride film first,
Then the compression silicon nitride film in the regions of PMOS 3 is protected with the photoresist layer of patterning, removes the compression nitrogen in the regions of NMOS 2
SiClx film, then removes photoresist layer, forms compressive stress layer 10.The thickness of compressive stress layer 10 is h2, wherein, h2With h1Preferably
It is equal, can also be unequal, but difference is no more than S0nm.
The formation sequencing of both the above stressor layers can be exchanged, and they are carried to NMOS and PMOS channel region respectively
Power is supplied, to increase the mobility of channel region carrier, it is ensured that performance of the transistor in deep-submicron field.
Then, it is comprehensive deposition TEOS layers (not shown), CMP is carried out, device architecture is planarized, dummy gate electrode is opened
Upper surface, referring to accompanying drawing 5.Also, walked at this in CMP, to make dummy gate electrode, tensile stress layer 9, the upper table of compressive stress layer 10
Face is in same plane.After this step, the upper surface of dummy gate electrode 6 and 8 is exposed.
Then, referring to accompanying drawing 6, comprehensive deposition protective layer 11, the material of protective layer 11 can be the corrosion rate in DHF
Relative to tensile stress 9 relatively low material of layer, specially silica, compression silicon nitride, unstressed silicon nitride etc., thickness is, for example,
100nm.Protective layer 11 is covered on whole device area simultaneously.
Then, referring to accompanying drawing 7, photoetching and etching are carried out to protective layer 11 with grid lines reticle, removed positioned at illusory
The protective layer 11 of gate upper surface.The purpose of this step is to open dummy gate electrode upper surface, because this figure corresponds to gate line
Bar, therefore photoetching can be carried out using grid lines reticle, dummy gate electrode upper surface can be exposed just.
Then, referring to accompanying drawing 8, dummy gate electrode and dummy gate electrode insulating barrier are removed successively, form gate recess 12.Specific bag
Include：First remove dummy gate electrode 6 and 8；Then, dummy gate electrode insulating barrier 5 and 7 is removed, removing method is DHF wet etchings.Due to
Protective layer 11 covers whole tensile stress layers 9 and compressive stress layer 10, due to tensile stress layer 9 and dummy gate electrode insulating barrier 5,7
Compare, DHF is to the corrosion rate of protective layer 11 and little, while the thickness having in view of protective layer 11, illusory removing
During gate insulator 5 and 7, protective layer 11 will not be completely removed, therefore, because the protection of protective layer 11, DHF is to opening
Stress silicon nitride can not be corroded, and tensile stress layer 9 and compressive stress layer 10 will not all have any loss, thus can be to raceway groove
Enough stress is provided.
Then, referring to accompanying drawing 9, NMOS 2 high K gate insulation layers 13 and metal gates is formed respectively in gate recess 12
14, PMOS 3 high K gate insulation layers 15 and metal gates 16.High K gate insulation layers 13 and high K gate insulation layers 15 are selected from following material
One or a combination set of constitute one or more layers：Al2O3, HfO2, including HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、
HfAlSiOxAnd HfLaSiOxAt least one including hafnium base high K dielectric material, including ZrO2、La2O3、LaAlO3、TiO2Or
Y2O3At least one including rare-earth-based high K dielectric material.The thickness of high K gate insulation layers 13 and high K gate insulation layers 15 is 0.5-
100nm, preferably 1-10nm, depositing operation are, for example, CVD.The material of metal gates 14 and metal gates 16 is metal or metal
Compound, such as TiN, TaN, W.NMOS and PMOS grid and high-K gate insulating barrier formation order can be adjusted according to demand
Change.
So, high-K metal gate manufacture is completed, and realizes the rear grid technique and the integrated work of double strain stress layers of the present invention
Skill, can carry out the preparation of interlayer dielectric layer and interconnection line afterwards.
So far, the present invention proposes and rear grid technique is described in detail and the integrated semiconductor devices manufacture of double strain stress layers
Method.In the method for the invention, sunk first in NMOS area formation tensile stress layer and in PMOS area formation compressive stress layer
Product TEOS simultaneously carries out planarization process, then deposited overall protective layer；Photoetching is carried out to protective layer using grid lines mask
And etching, dummy gate electrode is opened, due to completely covers protective layer on tensile stress layer and compressive stress layer, and protective layer exists
Corrosion rate very little in wet etching liquid, thus tensile stress layer and compressive stress layer will not be overcome existing by any damage
Defect in technology；Then, formed after gate recess, complete high K gate insulation layers and metal gates manufacture, realize rear grid technique
Technique with double strain stresses layer is integrated.
The present invention is described above by reference to embodiments of the invention.But, these embodiments are used for the purpose of saying
Bright purpose, and be not intended to limit the scope of the present invention.The scope of the present invention is limited by appended claims and its equivalent.
The scope of the present invention is not departed from, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications should all fall
Within the scope of the present invention.
Claims (6)
1. a kind of method, semi-conductor device manufacturing method, it is characterised in that comprise the following steps：
Semiconductor substrate is provided, sti structure is formed in the Semiconductor substrate, and carries out well region injection, formed NMOS area and
PMOS area；
Nmos pass transistor and PMOS transistor are formed, the nmos pass transistor and the PMOS transistor include dummy gate electrode and void
If gate insulator, the dummy gate electrode is by grid lines lithography layout case；
Tensile stress layer is formed on the nmos pass transistor, compressive stress layer is formed on the PMOS transistor；
CMP, the upper surface of the exposure dummy gate electrode are carried out, and makes the dummy gate electrode, tensile stress layer, the pressure
The upper surface of stressor layers is in same plane；
Comprehensive deposition protective layer；
Photoetching and etching are carried out to the protective layer with grid lines reticle, the institute positioned at the dummy gate electrode upper surface is removed
Protective layer is stated, the dummy gate electrode upper surface is exposed；
The dummy gate electrode and the dummy gate electrode insulating barrier are removed successively, gate recess are formed, due to the guarantor of the protective layer
Shield, the tensile stress layer and the compressive stress layer will not all have any loss, thus enough stress can be provided to raceway groove；
In the gate recess, the nmos pass transistor and the high K gate insulation layers and gold of the PMOS transistor are formed respectively
Belong to grid.
2. according to the method described in claim 1, it is characterised in that form nmos pass transistor and PMOS transistor is specifically included：
Form the dummy gate electrode and the dummy gate electrode insulating barrier；
Form grid gap wall；
Form the source and drain areas of transistor.
3. according to the method described in claim 1, it is characterised in that tensile stress layer is formed on the nmos pass transistor specific
Including：
Deposited overall tensile stress silicon nitride film, is located to open described in the nmos pass transistor and answers with the photoresist layer protection of patterning
Power silicon nitride film, removes the tensile stress silicon nitride film positioned at the PMOS transistor, then removes photoresist layer, forms institute
State tensile stress layer.
4. according to the method described in claim 1, it is characterised in that compressive stress layer is formed on the PMOS transistor specific
Including：
Deposited overall compression silicon nitride film, should positioned at the pressure of the PMOS transistor with the photoresist layer protection of patterning
Power silicon nitride film, removes the compression silicon nitride film positioned at the nmos pass transistor, then removes photoresist layer, forms institute
State compressive stress layer.
5. according to the method described in claim 1, it is characterised in that the protective layer is silica, compression silicon nitride or nothing
Stress silicon nitride, thickness is 100 angstroms.
6. according to the method described in claim 1, it is characterised in that before CMP, comprehensive deposition TEOS layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210393777.XA CN103730422B (en) | 2012-10-16 | 2012-10-16 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210393777.XA CN103730422B (en) | 2012-10-16 | 2012-10-16 | Semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103730422A CN103730422A (en) | 2014-04-16 |
| CN103730422B true CN103730422B (en) | 2017-09-26 |
Family
ID=50454441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210393777.XA Active CN103730422B (en) | 2012-10-16 | 2012-10-16 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103730422B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9368394B1 (en) * | 2015-03-31 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Dry etching gas and method of manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| CN102543872A (en) * | 2010-12-24 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102543739A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101798379B1 (en) * | 2010-10-05 | 2017-11-16 | 삼성전자주식회사 | Method for forming gate in gate last process and gate area formed by the same |
-
2012
- 2012-10-16 CN CN201210393777.XA patent/CN103730422B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| CN102543739A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102543872A (en) * | 2010-12-24 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103730422A (en) | 2014-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10804165B2 (en) | Source and drain isolation for CMOS nanosheet with one block mask | |
| US8367495B2 (en) | Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material | |
| US8008145B2 (en) | High-K metal gate structure fabrication method including hard mask | |
| US9515188B2 (en) | Fin field effect transistors having conformal oxide layers and methods of forming same | |
| US9698269B2 (en) | Conformal nitridation of one or more fin-type transistor layers | |
| US20150084132A1 (en) | Silicon Nitride Layer Deposited at Low Temperature to Prevent Gate Dielectric Regrowth High-K Metal Gate Field Effect Transistors | |
| US10756199B2 (en) | Fin field effect transistors having conformal oxide layers and methods of forming same | |
| US9196475B2 (en) | Methods for fabricating integrated circuits including fluorine incorporation | |
| US10461169B2 (en) | Semiconductor device structure and method for forming the same | |
| US20180374755A9 (en) | Fin field-effect transistor and fabrication method thereof | |
| US8030214B2 (en) | Method of fabricating gate structures | |
| JP2009152342A (en) | Method of manufacturing semiconductor device | |
| CN103094214B (en) | Manufacturing method for semiconductor device | |
| TW202018777A (en) | Method for fabricating semiconductor device | |
| CN103681503B (en) | Semiconductor device manufacturing method | |
| CN103730422B (en) | Semiconductor device manufacturing method | |
| CN103681504B (en) | Semiconductor device manufacturing method | |
| CN104253049B (en) | Semiconductor device manufacturing method | |
| CN103794562B (en) | Semiconductor device manufacturing method | |
| TWI859921B (en) | Semiconductor device and manufacturing method thereof | |
| CN103177944B (en) | Make the method for semiconductor device | |
| CN103187253B (en) | Make the method for semiconductor device | |
| US20240332420A1 (en) | Semiconductor device and manufacturing method thereof | |
| WO2013063728A1 (en) | Transistor, transistor manufacturing method and semiconductor device including such transistor | |
| CN103855092B (en) | Semiconductor device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201217 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 No. 3 Beitucheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220425 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |