KR100827574B1 - Process for producing silicon wafer - Google Patents

Abstract

Sheet-fed etching process (12) in which etching liquid is supplied to the surface of a single thin plate-like silicon wafer obtained by slicing a silicon single crystal ingot by a supply nozzle, and the wafer is spread and etched throughout the wafer surface by rotating the wafer. And a polishing step 14 for polishing the surface of the silicon wafer in this order, wherein the etching liquid used for the single wafer etching is an acid etching liquid, and the acid etching liquid is composed of hydrofluoric acid, nitric acid and phosphoric acid. A process for producing a silicon wafer, wherein nitric acid and phosphoric acid are aqueous solutions contained in a weight ratio of hydrofluoric acid: nitric acid: phosphoric acid = 0.5 to 40%: 5 to 50%: 5 to 70%.

Single wafer etching process, polishing process, chamfering process, silicon wafer manufacturing method

Description

Method for manufacturing silicon wafers {PROCESS FOR PRODUCING SILICON WAFER}

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the manufacturing method of the silicon wafer in this embodiment.

2 shows a sheet type etching apparatus.

3 is a perspective view showing a chamfering step;

4 shows a double-sided simultaneous polishing apparatus;

5 is a diagram showing a wafer surface shape after the slicing step of Example 1. FIG.

FIG. 6 is a diagram showing a wafer surface shape after a single wafer etching step of Example 1. FIG.

The figure which shows the wafer surface shape after the double-sided simultaneous polishing process of Example 1. FIG.

8 is a view showing a wafer surface shape after a slicing step of Comparative Example 1. FIG.

9 is a view showing the wafer surface shape after the DDSG process of Comparative Example 1. FIG.

10 is a view showing the wafer surface shape after the SDSG process of Comparative Example 1. FIG.

11 is a view showing a wafer surface shape after a double-sided simultaneous polishing step of Comparative Example 1. FIG.

12 is a diagram showing a wafer surface shape after a slicing step of Comparative Example 2. FIG.

The figure which shows the wafer surface shape after the DDSG process of the comparative example 2. FIG.

14 is a diagram showing a wafer surface shape after a single wafer etching step of Comparative Example 2. FIG.

15 is a diagram showing a wafer surface shape after a double-sided simultaneous polishing step of Comparative Example 2. FIG.

16 is a view showing a conventional method for manufacturing a silicon wafer.

Patent Document 1: Japanese Patent Application Laid-Open No. 11-135464 (claim 1, Fig. 1)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a silicon wafer capable of achieving high planarization without performing a planarization step using mechanical polishing such as grinding or lapping.

The content of which is hereby incorporated by reference, claims Japanese Patent Application 2005-236255, filed August 17, 2005, the priority.

In general, the manufacturing process of a semiconductor silicon wafer consists of a process of chamfering, mechanical polishing (lapping or grinding), etching, mirror polishing (polishing) and cleaning of wafers obtained by cutting from sliced silicon single crystal ingots and slicing, and with high precision. It is produced as a wafer with a flatness of degrees.

However, in the conventional method, the wafer which has been etched is subjected to a mirror polishing process and the surface thereof is processed to a mirror surface. On the front and back surfaces of the silicon wafer after the etching process, the wafer flatness at the end of the planarization process such as lapping or grinding is finished. In order to improve these wafer flatness and wafer surface roughness, it is necessary to secure a large number of polishing zones in the mirror polishing process because it is not retained and the desired wafer surface roughness is not obtained. .

Here, as a silicon wafer manufacturing process which can efficiently remove the process strain layer produced by mechanical polishing, ensuring flatness, the process of slicing a silicon single crystal ingot as shown in FIG. 16, and of this slicing wafer Step 2 for chamfering the cross section, planarization step 3 for planarizing at least the surface of the wafer obtained by slicing the semiconductor ingot by plane grinding or lapping, and spin etching step 4 for etching the surface of the planarized wafer by spin etching And the manufacturing method of the semiconductor wafer which consists of the grinding | polishing process 5 which polishes the surface of the etched wafer to make a mirror surface is disclosed (for example, refer patent document 1).

However, in the method shown in the said patent document 1, the grinding mark which arises from wafer hold | maintenance at the time of grinding etc. by mechanical polishing in a planarization process, and the relief of the wafer surface generate | occur | produce, and the process deformation layer in the process following this planarization process In addition, in order to remove the grinding marks and undulations, it is necessary to secure a large number of abrasive zones, which also put a heavy load on the polishing process.

An object of the present invention is to provide a method for producing a silicon wafer, which can achieve high flattening and improve productivity without carrying out a planarization step using mechanical polishing such as grinding or lapping, which has been an essential manufacturing process in the past.

The present inventors omit the planarization process by grinding | polishing, such as grinding which was an essential process in the conventional wafer manufacturing process, and performs a sheet-fed etching process and a grinding | polishing process in this order on a sliced wafer in a specific condition, and performs the conventional manufacturing process and It has been found that they have the same degree or higher high flatness and can improve productivity.

As shown in FIG. 1, the invention according to claim 1 supplies an etching solution by a supply nozzle to a surface of a single thin plate-like silicon wafer obtained by slicing a silicon single crystal ingot, and rotates the wafer to supply the etching solution supplied to the entire wafer surface. A single wafer etching step 12 which is diffused and etched into the wafer, and a polishing step 14 of polishing the surface of the silicon wafer, in this order, wherein the etching solution used for the single wafer etching is an acid etching solution, and the acid etching solution is hydrofluoric acid, nitric acid and phosphoric acid. And a hydrofluoric acid, nitric acid, and phosphoric acid in an aqueous solution containing a mixed ratio of hydrofluoric acid: nitric acid: phosphoric acid = 0.5 to 40%: 5 to 50%: 5 to 70% by weight. .

In the invention according to claim 1, the wafer TTV is 1 μm without performing the single wafer etching step 12 and the polishing step 14 under the above conditions, without performing a planarization step using mechanical polishing by grinding or the like, which was an essential step in the conventional wafer manufacturing process. The high leveling which is the following can be achieved.

The invention according to claim 2 is the invention according to claim 1, wherein the single wafer etching step 12 is a step of etching a silicon wafer back surface after etching the silicon wafer surface.

The invention according to claim 3 is the invention according to claim 1, wherein the difference between the maximum value and the minimum value of the obtained silicon wafer thickness is 1 μm or less.

The invention according to claim 4 is the invention according to claim 1, further comprising a chamfering step 13 for chamfering a cross section of the silicon wafer between the single wafer etching step 12 and the polishing step 14.

Next, the best mode for implementing this invention is demonstrated based on drawing. First, the grown silicon single crystal ingot is cut into a block by cutting the front end and the end, and the outer diameter of the ingot is ground to make a block in order to make the diameter of the ingot uniform. Orientation flats or orientation notches are applied to this block to indicate specific crystal orientations. After this process, as shown in FIG. 1, a block body is sliced at a predetermined angle with respect to the rod axial direction (step 11).

In the conventional wafer fabrication process, the uneven layer of the front and back surface of the thin silicon wafer in the slicing or the like was then cut by mechanical polishing such as grinding or lapping to increase the flatness and parallelism of the front and back surfaces of the wafer. In the method, the etching liquid is supplied to the surface of a single silicon wafer by a supply nozzle without performing the planarization process by mechanical polishing, and the etching liquid supplied is diffused to the entire surface of the wafer by spinning the wafer at a predetermined rotational speed, thereby etching. (Step 12). In the single wafer etching step 12 of the present invention, the uneven layer of the front and back surfaces of the silicon wafer generated in the slicing and the like process is flattened by etching to increase the flatness and parallelism of the front and back surfaces of the wafer. In addition, the processing deterioration layer introduced by the machining process such as block cutting, outer diameter grinding and slicing step 11 is completely removed. Moreover, the surface roughness and the texture size of the wafer are controlled by using an acid etching solution as the etching solution used for single wafer etching.

In this single wafer etching step, the silicon wafer 21 is loaded into the single wafer etching apparatus 20 shown in FIG. 2. That is, the wafer 21 is held horizontally so that the surface of the wafer 21 becomes the upper surface by the vacuum suction wafer chuck 23 arranged in the cup 22. Subsequently, the etching liquid supply nozzle 24 formed on the upper side of the wafer 21 is horizontally moved while supplying the etching liquid 26 from the etching liquid supply nozzle 24 to the upper surface of the wafer 21 while moving horizontally. By spinning the wafer 21 by the wafer chuck 23, the wafer surface is etched to remove the processing altered layer on the wafer surface. The horizontal movement of the supply nozzle 24 is a speed of 0.1 to 20 mm / sec, with the end of the supply nozzle 24 as the support point in the radial direction of the wafer from the center of the wafer, and a circular arc drawn by the horizontal drive of the nozzle 24. It is performed by rocking, or by reciprocating in the radial direction of the wafer from the center of the wafer. The etching liquid 26 supplied to the upper surface of the wafer 21 gradually moves while etching the processing altered layer on the wafer surface from the wafer center side to the wafer outer peripheral side by the centrifugal force of the wafer rotation, and the droplet 26 from the outer peripheral edge of the wafer. This is scattered.

The etching liquid 26 used in the sheet type etching process of this invention is an aqueous solution containing hydrofluoric acid, nitric acid, and phosphoric acid, respectively. Moreover, the mixing ratio of hydrofluoric acid, nitric acid, and phosphoric acid contained in aqueous solution is prescribed | regulated by weight% as hydrofluoric acid: nitric acid: phosphoric acid = 0.5-40%: 5-50%: 5-70%. By setting it as the said mixing ratio, since the viscosity of the etching liquid 26 becomes 2-40 mPa * sec, and the surface tension of the etching liquid 26 will be 50-70 dyne / cm, it is preferable to raise the flatness of a wafer front and back, and the parallelism of a wafer. If the viscosity is less than the lower limit, the viscosity of the liquid is so low that the etching liquid dropped on the upper surface of the wafer is blown directly from the surface of the wafer by centrifugal force and cannot take uniform and sufficient contact with the surface of the wafer. Is lowered. If the viscosity exceeds the upper limit, the etching liquid dipped on the wafer surface remains longer than necessary on the upper surface of the wafer, resulting in a problem that the in-plane and outer shape of the wafer cannot be controlled and the wafer flatness is deteriorated. If the surface tension is less than the lower limit, the etching liquid dropped on the upper surface of the wafer is blown directly from the surface of the wafer by centrifugal force and cannot be brought into uniform and sufficient contact with the surface of the wafer. If the surface tension exceeds the upper limit value, the etching liquid dropped onto the wafer surface will remain on the upper surface of the wafer for longer than necessary, resulting in a problem that the in-plane and outer shape of the wafer cannot be controlled and the wafer flatness is deteriorated. The mixing ratio of hydrofluoric acid, nitric acid, phosphoric acid and water contained in the etching solution is preferably 5 to 20%: 20 to 40%: 20 to 40%: 20 to 40%. By setting it as this mixing ratio, the viscosity of etching liquid will be 10-25 mPa * sec, and the surface tension of etching liquid will be 55-60 dyne / cm. As for the supply amount of the etching liquid 26 from the etching liquid supply nozzle 24, 2-30 liter / min is preferable. When the silicon wafer is φ300 mm, the supply amount of the acid etching liquid 26 is preferably 5 to 30 liters / minute, and when the silicon wafer is φ200 mm, the supply amount of the acid etching liquid 26 is preferably 3 to 20 liters / minute.

The rotation speed of the wafer 21 in the single wafer etching process 12 of this invention is prescribed | regulated in the range of 100-2000 rpm. The optimum rotational speed also depends on the diameter of the wafer 21, the viscosity of the etching liquid 26, the supply position of the etching liquid 26 due to the horizontal movement of the supply nozzle 24, and the supply flow rate of the etching liquid 26 to be supplied. Is somewhat back and forth. If the rotational speed is lower than the lower limit, the in-plane and outer circumference of the wafer cannot be controlled, resulting in a problem of deterioration of the wafer flatness. If the rotational speed exceeds the upper limit, the etchant dropped on the surface of the wafer is blown directly from the wafer surface by centrifugal force. Since the surface cannot be uniformly and sufficiently brought into contact with the surface, it takes time to secure a sufficient etching treatment zone and the productivity is lowered. When the silicon wafer is φ300 mm, the rotation speed is preferably 200 to 1500 rpm, more preferably 600 rpm. Moreover, when a silicon wafer is phi 200 mm, 300-2000 rpm is preferable and, as for a rotation speed, 800 rpm is more preferable.

In this single wafer etching step 12, the wafer surface is etched and then the back surface of the wafer is etched to equally etch the front and back surfaces of the wafer, thereby increasing the parallelism of the wafer. After etching the surface of the wafer 21, spin the wafer 21 while supplying a rinse liquid such as pure water to the upper surface of the wafer 21 by means of a rinse liquid supply nozzle (not shown) remains on the surface of the wafer 21. The etching liquid 26 is washed. After cleaning, the wafer 21 is spun by drying the wafer 21 while supplying an inert gas such as nitrogen gas while the supply of the rinse liquid is stopped. Next, the wafer 21 is held upside down, and the wafer 21 is held on the wafer chuck 23 so that the rear surface of the wafer 21 becomes an upper surface, and the etching process, the rinse liquid cleaning process, and the drying process are performed in the same manner.

As for the etching process zone in this single wafer type etching process 12, 10-150 micrometers is preferable as a total processing zone of 5-75 micrometers of single surfaces, and a front and back surface of a wafer. By making an etching process zone into the said range, the flatness of a wafer front and back and the parallelism of a wafer can be raised, and the polishing zone in a subsequent grinding | polishing process can be reduced significantly compared with the conventional wafer manufacturing process. If the etching treatment zone is less than the lower limit, the flatness and the parallelism of the wafer front and back surfaces required as products are not obtained, and the wafer surface roughness is not sufficiently reduced. Therefore, when the load of the polishing process is large and the upper limit is exceeded, the wafer flatness is increased. The degree deteriorates and the productivity in wafer fabrication deteriorates. Since the surface roughness and the texture size of the wafer can be controlled by performing the single wafer etching step 12 under the above conditions, the wafer flatness is maintained while reducing the polishing zones on the front and back surfaces of the wafer in the subsequent polishing step 14. And reduction of wafer surface roughness can be achieved.

Next, returning to FIG. 1, the wafer which has completed the single wafer etching step 12 is chamfered in the wafer end surface in order to prevent defects and chips in the wafer peripheral portion (step 13). By performing this chamfering, for example, when the epitaxial growth is carried out on the chamfered silicon wafer surface, abnormal growth occurs in the cross section and the crown phenomenon which swells in an annular shape can be suppressed. Usually, the wafer chamfering step is performed before the wafer planarization step so that defects or chips do not occur in the wafer periphery by the wafer planarization step such as lapping or planar grinding, but the planarization step is omitted in the present invention. The step can be carried out before or after the single wafer etching step. In particular, by performing the chamfering processing step after the single wafer etching process, the chamfering can be performed while controlling the mold collapse of the wafer cross section by the single wafer etching process without disturbing the chamfer shape of the wafer by the etching action. Specifically, as shown in FIG. 3, the wafer center is sucked by the vacuum chuck 31, and the wafer 21 is held horizontally. The wafer 21 is spun by the rotary drive unit formed integrally with the vacuum chuck 31, and the chamfering process is performed by bringing the grinding wheel 32 into contact with the wafer end face 21a while spinning. In this chamfering step, the polishing tape may be brought into contact with the wafer end face at an arbitrary contact angle.

Next, returning to FIG. 1, polishing of the surface of the silicon wafer is performed (step 14). In this embodiment, double-sided simultaneous polishing for simultaneously polishing the front and back surfaces of the wafer will be described.

As a method of simultaneously double-sided polishing, it is performed by the double-sided simultaneous polishing apparatus 40 shown in FIG. As shown in FIG. 4, first, the carrier plate 41 is engaged with the sun gear 47 and the internal gear 48 of the double-sided simultaneous polishing apparatus 40, and the silicon wafer 21 in the holder of the carrier plate 41. Set. Thereafter, both surfaces of the silicon wafer 21 are interposed between the upper surface plate 42 having the first polishing cloth 42a attached to the polishing surface side and the lower surface plate 43 having the second polishing cloth 43a attached to the polishing surface side. The carrier plate 41 is planetary-moved by the sun gear 47 and the internal gear 48, while the abrasive 46 is supplied from the nozzle 44 while being held in the same manner. Both surfaces of the silicon wafer 21 are mirror-polished simultaneously by rotating the lower surface plate 43 and the lower surface plate 43 in the relative direction. Since the silicon wafer subjected to the single wafer etching step 12 described above maintains the flatness almost the same as the wafer flatness when the flattening step is completed, and has the desired wafer surface roughness, this double-sided simultaneous polishing step 14 In this case, the polishing zone on the front and back surfaces of the wafer can be reduced, and both the maintenance of the wafer flatness and the reduction of the wafer surface roughness can be achieved. In this double-sided simultaneous polishing step 14, the front and back surfaces of the silicon wafer are simultaneously polished while controlling the number of rotations of the upper surface plate 42 and the lower surface plate 43, respectively, so that the front and rear surfaces of the wafer can be visually identified. You can get it. As for the grinding | polishing process zone in this grinding | polishing process 14, 2-30 micrometers is preferable as a total treatment zone of 1-15 micrometers of single surfaces, and the front and back surface of a wafer.

Thus, by implementing the manufacturing method of the silicon wafer of this invention, high planarization can be achieved, without performing the planarization process using mechanical polishing, such as grinding and lapping which were conventionally essential manufacturing processes. Therefore, since grinding marks and undulations caused by mechanical planarization treatment such as conventional grinding do not occur, there is no need to secure a large number of polishing zones in the mirror polishing process, thereby greatly improving the productivity in wafer manufacturing. do. By the manufacturing method of this invention, the silicon wafer whose difference between the maximum value and minimum value of a wafer thickness is 1 micrometer or less is obtained.

Moreover, in this embodiment, although the front and back surfaces of the wafer were polished simultaneously by double-sided simultaneous polishing, it is said that the same effect can be obtained even if the wafer is polished by single-side polishing in which the front and back surfaces of the wafer are polished one by one instead of double-sided simultaneous polishing. There is no need. In addition, in order to improve the microroughness of the main surface of the wafer on which the device is manufactured, single-side polishing may be performed on the main surface of the wafer on which double-sided simultaneous polishing is performed.

(Example)

Next, the Example of this invention is described in detail with a comparative example.

<Example 1>

First, five sheets of φ300 mm silicon wafers cut out from a silicon single crystal ingot were prepared. Subsequently, single wafer etching was performed on the silicon wafer using the single wafer etching apparatus shown in FIG. As the etching solution, an acid etching solution containing a mixture of hydrofluoric acid, nitric acid, phosphoric acid, and water at a weight% of hydrofluoric acid: nitric acid: phosphoric acid: water = 7%: 30%: 35%: 28% was used. Moreover, the wafer rotation speed in etching was controlled at 600 rpm and the flow volume of the etching liquid to supply at 5.6 liter / min, respectively, and etching was performed for 90 second. The etching process zone in single wafer acid etching was 30 micrometers on one side. After etching, pure water was supplied to the wafer surface while the wafer was spun while being washed, and nitrogen was sprayed onto the wafer surface to dry the wafer surface. Subsequently, the wafer was flipped over, and the single wafer type etching was performed on the back surface of the wafer under the same conditions. Next, chamfering was performed to the cross section of the wafer using the apparatus shown in FIG. In addition, by using the double-sided simultaneous polishing apparatus shown in FIG. 5, the rotational speeds of the upper surface plate, the lower surface plate, the internal gear, and the sun gear are adjusted to the front and back surfaces of the wafer so that the polishing zone in double-sided simultaneous polishing becomes 10 µm on one side. Double-sided simultaneous polishing was performed. Five samples were made into the mirror surface wafer by the above process.

Comparative Example 1

First, five sheets of φ300 mm silicon wafers cut out from a silicon single crystal ingot were prepared. Subsequently, double-sided simultaneous grinding (Double Disk Surface Grind; hereinafter referred to as DDSG) was performed on the front and back surfaces of the silicon wafer using a grinding apparatus (not shown) as the planarization step. The process zone in this DDSG process was 30 micrometers on one side. Subsequently, a single-sided grinding step (hereinafter referred to as a SDSG step) was performed using a grinding device (not shown), and the treatment zone in this SDSG step was set to 20 μm on one side. In addition, by using the double-sided simultaneous polishing apparatus shown in FIG. 5, the rotation speeds of the upper surface plate, the lower surface plate, the internal gear, and the sun gear are adjusted so that the polishing zone in double-sided simultaneous polishing becomes 10 µm on one side. Both surfaces were simultaneously polished. Five samples were made into the mirror surface wafer by the above process.

Comparative Example 2

First, five sheets of φ300 mm silicon wafers cut out from a silicon single crystal ingot were prepared. Subsequently, as a planarization process, DDSG was performed to the front and back of a silicon wafer using the lapping apparatus. The process zone in this DDSG process was 30 micrometers on one side. Subsequently, single wafer etching was performed on the silicon wafer which had been planarized using the single wafer etching apparatus shown in FIG. As the etching solution, an acid etching solution containing a mixture of hydrofluoric acid, nitric acid, phosphoric acid, and water in a weight% of hydrofluoric acid: nitric acid: phosphoric acid: water = 7%: 30%: 35%: 28% was used. Moreover, the wafer rotation speed in etching was controlled at 600 rpm and the flow volume of the etching liquid to supply at 5.6 liter / min, respectively, and etching was performed for 60 second. The etching process zone in single wafer etching was 20 micrometers on one side. After etching, pure water was supplied to the wafer surface while the wafer was spun while being washed, and nitrogen was sprayed onto the wafer surface to dry the wafer surface. Subsequently, the wafer was turned upside down, and single wafer etching was performed under the same conditions on the wafer back surface. In addition, by using the double-sided simultaneous polishing apparatus shown in FIG. 5, the rotational speeds of the upper surface plate, the lower surface plate, the internal gear, and the sun gear are adjusted to the front and back surfaces of the wafer so that the polishing zone in double-sided simultaneous polishing becomes 10 µm on one side. Double-sided simultaneous polishing was performed. In the above process, five samples were made into the mirror surface wafer.

Comparative Test 1

TTV after each process in Example 1, Comparative Example 1, and Comparative Example 2, and wafer surface shape were measured. After TTV adsorption-fixed each wafer to the vacuum suction board, the maximum value and minimum value of the wafer thickness were calculated | required, and it was set as the difference of the value. Tables 1 to 3 show TTVs after each step. Moreover, the average value and standard deviation (sigma) of the samples 1-5 are shown in Tables 1-3. Moreover, the surface shape in the sample (1) of Example 1, the comparative example 1, and the comparative example 2 is shown to FIGS. 5-15, respectively.

As is clear from Tables 1 to 3, it can be seen that the TTV value after the double-sided simultaneous polishing step in Example 1 is obtained without comparable with the TTV value after the double-sided simultaneous polishing step in Comparative Examples 1 and 2. have. Moreover, as is clear from FIGS. 5-15, the wafer surface shape after each process of Example 1 is inferior to the wafer surface shape after each process of Comparative Example 1 and Comparative Example 2, Comprising: It is essential in the past It has been found that high flattening can be achieved without performing a flattening step using mechanical polishing such as grinding or lapping which was a manufacturing step.

The manufacturing method of the silicon wafer of this invention has the advantage that high planarization can be achieved, without performing the planarization process using mechanical polishing, such as grinding and lapping, which was the essential manufacturing process conventionally. Therefore, since grinding marks and undulations that have been generated by performing a mechanical planarization treatment such as conventional grinding do not occur, there is no need to secure a large number of polishing zones in the mirror polishing process, thereby improving the productivity of wafer fabrication. .

While preferred embodiments of the present invention have been described and illustrated above, these should be understood as illustrative of the invention and not as a limitation. Additions, omissions, substitutions and other changes may be made without departing from the spirit of the scope of the invention. Accordingly, the invention is not to be understood as limited to the foregoing description, but is only limited by the appended claims.

Claims (5)

A slice process of slicing a silicon wafer on a thin plate from a silicon single crystal ingot, Following the slicing step, an etching solution is supplied to the surface of the single silicon wafer by a supply nozzle, and the wafer is rotated to diffuse the etched liquid onto the entire surface of the wafer to perform etching. Single wafer etching step (12) for removing the uneven layer and the processed altered layer generated on the surface of the wafer by etching; And a polishing step 14 for polishing the surface of the silicon wafer in this order, wherein the etching solution used in the single wafer etching step is an acid etching solution, and the acid etching solution is composed of hydrofluoric acid, nitric acid, and phosphoric acid. And phosphoric acid is an aqueous solution contained in a mixing ratio of hydrofluoric acid: nitric acid: phosphoric acid = 0.5 to 40%: 5 to 50%: 5 to 70% by weight%, In the single wafer etching process, the supply amount of the etching liquid supplied from the supply nozzle is 2 to 30 liters / minute, and the rotation speed of the silicon wafer is defined in the range of 100 to 2000 rpm. . The method of claim 1, The single wafer etching process (12) is a process of etching a silicon wafer back surface after etching the silicon wafer surface, The manufacturing method of a silicon wafer. The method of claim 1, The manufacturing method of a silicon wafer whose difference between the maximum value and minimum value of the silicon wafer thickness obtained is 1 micrometer or less. The method of claim 1, And a chamfering step (13) for chamfering the cross section of the silicon wafer between the single wafer etching step (12) and the polishing step (14). The method of claim 1, The process zone in the single wafer etching step (12) is 5-75 μm on one side of the silicon wafer, wherein the silicon wafer is produced.

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