KR0183764B1 - Landing pad - Google Patents
Landing pad Download PDFInfo
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- KR0183764B1 KR0183764B1 KR1019950046907A KR19950046907A KR0183764B1 KR 0183764 B1 KR0183764 B1 KR 0183764B1 KR 1019950046907 A KR1019950046907 A KR 1019950046907A KR 19950046907 A KR19950046907 A KR 19950046907A KR 0183764 B1 KR0183764 B1 KR 0183764B1
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- forming
- contact hole
- insulating layer
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
본 발명은 랜딩 패드 형성방법에 관한 것으로, 이는, 반도체기판에 정보전달용 트랜지스터를 형성하는 단계, 트랜지스터가 형성된 결과물 전면에 제1절연막 및 제1절연막에 대해 식각율이 큰 제2절연막을 차례로 형성하는 단계, 제1절연막 및 제2절연막의 소정부위를 식각하여 콘택 홀을 형성하되, 그 상부의 사이즈가 하부의 사이즈보다 크도록 형성하는 단계 및 상기 콘택 홀 내부에 도전층을 채우는 공정을 구비하여 이루어진 것을 특징으로 한다. 따라서, 랜딩 패드 형성을 위한 콘택 홀의 형성시에 등방성 식각과 이방성 식각을 함께 실시함으로써 상기 콘택 홀의 상부의 사이즈가 하부의 사이즈 보다 크게 되어, 고집적화에 따른 사진식각공정을 극복할 수 있을 뿐만 아니라, 패드 폴리가 형성될 부위에 절연막을 식각해 낸 후 패드 폴리를 채워넣기 때문에 하부층(즉 게이트전극)토폴로지에 의한 μ-브리지 발생염려가 없는 장점이 있다.The present invention relates to a method of forming a landing pad, which includes forming an information transfer transistor on a semiconductor substrate, and sequentially forming a first insulating layer and a second insulating layer having a large etch rate with respect to the first insulating layer on the entire surface of the resultant transistor. Forming a contact hole by etching predetermined portions of the first insulating film and the second insulating film, wherein the size of the upper portion of the first insulating layer and the second insulating layer is larger than the size of the lower portion of the first insulating layer and the second insulating layer; Characterized in that made. Therefore, by forming isotropic etching and anisotropic etching together at the time of forming the contact hole for forming the landing pad, the size of the upper portion of the contact hole becomes larger than the size of the lower portion, and not only can overcome the photolithography process due to high integration, but also the pad. Since the pad poly is etched after the insulating film is etched in the area where the poly is to be formed, there is an advantage that there is no fear of generating the μ-bridge due to the underlying layer (ie, the gate electrode) topology.
Description
제1a도 및 제1b도는 종래방법에 의해 형성된 랜딩 패드를 나타낸 단면도 및 측면도이다.1A and 1B are sectional views and side views showing landing pads formed by conventional methods.
제2a도 내지 제2d도는 본 발명에 따른 랜딩 패드 형성방법의 일실시예를 나타낸 공정순서도이다.2a to 2d is a process flow diagram showing an embodiment of a landing pad forming method according to the present invention.
제3a도 및 제3b도는 본 발명에 따른 랜딩 패드 형성방법의 다른 실시예를 나타낸 공정순서도이다.3a and 3b is a process flow diagram showing another embodiment of the landing pad forming method according to the present invention.
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 메모리소자의 정보전달용 트랜지스터와 정보저장을 위한 캐패시터의 연결을 위한 랜딩 패드의 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a landing pad for connecting a transistor for transferring information of a memory device and a capacitor for storing information.
고집적 DRAM 제품에서 BC 콘택(Buried Contact)과 워드라인(word line)과의 단락방지 및 DC 콘택(Direct Contact)의 원할한 형성을 위하여 랜딩 패드(landing pad)를 이용하고 있다. 그러나, 다음과 같은 몇가지의 이유 때문에 랜딩 패드 공정 자체가 점점 마아진(margin)이 없는 어려운 공정이 되고 있다.In a highly integrated DRAM product, a landing pad is used to prevent short circuits between BC contacts and word lines and to form a DC contact. However, the landing pad process itself is becoming a difficult process with no margin for several reasons as follows.
첫째, 랜딩 패드 공정의 디자인 룰(design rule)이 가장 엄격한 공정중의 하나이기 때문에 사진식각공정이 어렵다. 액티브 피팅(active pitting)을 방지하고 후속 콘택(BC,DC)과의 오버랩 마이진(overlap margin)을 확보하려면 셀 피치(cell pitch)가 ∼0.6μm인 256M급의 메모리에서 패드 대 패드(pad to pad)의 간격(제1a도에서 ⓐ로 표시된 부분)으르 ∼0.2μm가 필요하기 때문에 현재의 시진공정 기술로 이정도의 간격을 형성하기는 매우 어렵다.First, the photo etching process is difficult because the design rule of the landing pad process is one of the most stringent processes. Pad to pad in 256M class memory with cell pitch of ~ 0.6μm to prevent active pitting and to ensure overlap margin with subsequent contacts (BC, DC) It is very difficult to form this gap with the current test process technology because a space of?) (A portion indicated by ⓐ in Fig. 1a) is required to be 0.2 μm.
둘째, 랜딩 패드의 식각시 하부층(underlayer)인 워드라인 즉 게이트전극의 단차가 높기 때문에 워드라인과 워드라인 사이의 골짜기에 식각의 불완전에 기인하여 발생되는 μ-브리지(bridge)를 제거하기가 어렵다. 예를 들어, 게이트전극으로 금속 실리사이드(silicide)를 사용하는 256M급에서는 워드라인의 단차가 ∼4000Å 이상이기 때문에 워드라인과 워드라인 사이의 골짜기(제1b도에서 ⓑ로 표시된 부분)에 μ-브리지가 발생하기 쉽고 발생하더라도 이를 검출하기도 어렵다.Second, due to the high level of the underline word line, that is, the gate electrode, during etching of the landing pad, it is difficult to remove the μ-bridge caused by the incomplete etching in the valley between the word line and the word line. . For example, in the 256M class using a metal silicide as the gate electrode, since the step of the word line is ˜4000 m or more, the μ-bridge is formed in the valley between the word line and the word line (the part indicated by ⓑ in Fig. 1b). Is easy to occur and difficult to detect even if it occurs.
따라서 본 발명의 목적은 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여 랜딩 패드가 형성될 부분의 절연막의 식각시에 등방성식각과 이방성식각을 함께 실시함으로써 사진식각공정의 디자인룰을 완화시켜줄 수 있는 랜딩 패드의 형성방법을 제공하는데 있다.Accordingly, an object of the present invention can mitigate the design rule of the photolithography process by performing isotropic etching and anisotropic etching at the time of etching the insulating film of the part where the landing pad will be formed to solve the problems of the prior art as described above. A method of forming a landing pad is provided.
상기한 목적을 달성하기 위하여 본 발명의 방법은, 반도체기판에 정보전달용 트랜지스터를 형성하는 공정; 상기 트랜지스터가 형성된 결과물 전면에 제1절연막 및 상기 제1절연막에 대해 식각율이 큰 제2절연막을 차례로 형성하는 공정; 상기 제1절연막 및 제2절연막의 소정부위를 식각하여 콘택 홀을 형성하되, 그 상부의 사이즈가 하부의 사이즈보다 크도록 형성하는 공정; 및 상기 콘택 홀 내부에 도전층을 채우는 공정을 구비하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the method of the present invention comprises the steps of forming a transistor for information transmission on a semiconductor substrate; Sequentially forming a first insulating film and a second insulating film having a large etching rate with respect to the first insulating film on the entire surface of the resultant product in which the transistor is formed; Forming a contact hole by etching predetermined portions of the first insulating layer and the second insulating layer, wherein the size of the upper portion is larger than the size of the lower portion; And filling a conductive layer in the contact hole.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명하기로 한다. 여기서, 상기 제1a도 및 제1b도는 종래방법에 의해 형성된 랜딩 패드를 나타낸 단면도 및 측면도를 각각 나타낸 것으로, 이하 본 발명을 설명할 때 사용되는 도면과 동일한 부분에는 동일 참조부호를 사용하였다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. 1A and 1B are cross-sectional views and side views showing landing pads formed by conventional methods, respectively, and the same reference numerals are used for the same parts as the drawings used to describe the present invention.
제2a도 내지 제2d도는 본 발명에 따른 랜딩 패드 형성방법의 일실시예를 나타낸 공정순서도이다.2a to 2d is a process flow diagram showing an embodiment of a landing pad forming method according to the present invention.
제2a도는 제1절연막(10) 및 제2절연막(20)의 형성공정을 도시한 것으로, 먼저 제1전도형의 반도체기판(100)에 소자형성을 위한 액티브영역과 이 액티브영역을 분리시켜 주기 위한 필드산화막(101)을 통상적인 방법을 이용하여 형성한 후, 상기 액티브영역상에 게이트절연막(도시되지 않음)이 개재된 게이트전극(1), 소오스영역(2) 및 드레인영역(3)으로 이루어지는 정보전달용 트랜지스터를 형성한다. 계속해서 결과물 전면에 제1절연막(10) 및 제2절연막(20)을 차례로 형성한다. 이때 상기 제1절연막(10)은 후속되는 등방성식각에 대해 식각율이 제2절연막(20)에 비해 낮은 특성을 갖도록 한다. 예를 들어 상기 제1절연막은 질화막으로 하고 제2절연막은 산화막으로 하거나, 제1절연막(10)은 고온산화막(HTO : High Temperature Oxide)으로 하고 제2절연막(20)은 BPSG(Boro-Phosphor Silicate Glass) 혹은 PSG(Phosphor Silicate Glass) 등의 불순물이 주입된 산화막으로 할 경우, CHF4+O2혹은 CF4가스 등을 이용한 등방성 플라즈마 식각에 대해 선택비를 갖게 할 수 있으며, 또는 HF 희석용액을 이용한 습식식각 혹은 HF 가스를 이용한 등방성식각에 대해서도 선택비를 갖게 할 수 있다. 통상 질화막과 산화막의 경우 플라즈마 식각의 경우 5 : 1∼10 : 1의 선택비를 갖게 할 수 있으며, HF를 이용한 습식식각의 경우 10 : 1 이상의 높은 선택비를 갖게 할 수 있다. 여기서, 미설명부호 4는 상기 게이트전극을 보호하기 위한 절연막을 나타낸다.FIG. 2A illustrates a process of forming the first insulating film 10 and the second insulating film 20. First, the active region for forming an element and the active region are separated from the first conductive semiconductor substrate 100. FIG. A field oxide film 101 is formed by a conventional method, and then formed into a gate electrode 1, a source region 2, and a drain region 3 having a gate insulating film (not shown) interposed thereon on the active region. An information transfer transistor is formed. Subsequently, the first insulating film 10 and the second insulating film 20 are sequentially formed on the entire surface of the resultant product. In this case, the first insulating layer 10 may have a lower etching rate than that of the second insulating layer 20 with respect to subsequent isotropic etching. For example, the first insulating film is a nitride film, the second insulating film is an oxide film, the first insulating film 10 is a high temperature oxide (HTO), and the second insulating film 20 is a BPSG (Boro-Phosphor Silicate). When the oxide film is implanted with impurities such as glass or PSG (Phosphor Silicate Glass), it is possible to have a selectivity for isotropic plasma etching using CHF 4 + O 2 or CF 4 gas, or HF dilution solution It is possible to have a selectivity for the wet etching used or the isotropic etching using HF gas. In general, the nitride film and the oxide film may have a selectivity of 5: 1 to 10: 1 for plasma etching, and a high selectivity of 10: 1 or more for wet etching using HF. Here, reference numeral 4 denotes an insulating film for protecting the gate electrode.
제2b도는 제1콘택 홀(CH1)의 형성공정을 도시한 것으로, 먼저 상기 제2절연막(20)위에 포토레지스트 도포, 마스크 노광 및 현상등의 공정을 거쳐 랜딩 패드의 도전층이 형성될 부위의 제2절연막이 노출되도록 포토레지스트 패턴(도시되지 않음)을 형성한 후, 이 포토레지스트 패턴을 적용하여 상기 제1절연막(10) 및 제2절연막(20)을 이방성 식각한다. 이때, 상기 제1콘택 홀(CH1)은 후속되는 랜딩 패드의 형성에 문제가 없을 정도로 작게 형성한다.FIG. 2B illustrates a process of forming the first contact hole CH1. First, a process of forming a conductive layer of the landing pad is performed on the second insulating layer 20 through photoresist coating, mask exposure, and development. After forming a photoresist pattern (not shown) to expose the second insulating film, the photoresist pattern is applied to anisotropically etch the first insulating film 10 and the second insulating film 20. In this case, the first contact hole CH1 is formed to be small enough that there is no problem in the subsequent formation of the landing pad.
제2c도는 제2콘택 홀(CH2)의 형성공정을 도시한 것으로, 상기 제2b도 공정후 결과물 전면에 대하여, 상기에서 설명한 바와 같이, 상기 제1절연막(10) 및 제2절연막(20)간에 식각율이 다른 등방성식각을 실시함으로써 도시된 바와 같은 제2콘택 홀(CH2)을 형성한다. 이때, 상기 제1절연막:제2절연막의 식각 선택비가 10 : 1 이상일 경우 상기 제1콘택 홀(CH1)의 크기에 거의 영향을 주지 않으면서 수백∼수천Å이 더 큰 제2콘택 홀(CH2)을 형성할 수 있다.FIG. 2C illustrates a process of forming the second contact hole CH2, and as described above with respect to the entire surface of the resultant after the process of FIG. 2B, as described above, between the first insulating film 10 and the second insulating film 20. By performing isotropic etching with different etching rates, the second contact hole CH2 as shown is formed. In this case, when the etching selectivity ratio of the first insulating film to the second insulating film is 10: 1 or more, the second contact hole CH2 having several hundreds to thousands of kilowatts is larger without affecting the size of the first contact hole CH1. Can be formed.
제2d도는 상기 포토레지스트 패턴의 제거후 결과물 전면에 공정폴리(pad poly)용 도전층 예컨대 불순물이 도우핑된 다결정실리콘을 침적하고, 이 도전층 전면에 대하여 에치 백(etch back) 공정을 실시함으로써 상기 제1 및 제2콘택 홀내에 도전층을 채워 랜딩 패드(LP)를 형성하는 공정을 나타낸다. 이때, 상기 에치 백 공정 대신에 CMP(Chemical Mechanical Polishing) 공정을 적용할 수도 있다.FIG. 2d shows a process layer for removing a photoresist pattern and depositing a polysilicon doped with an impurity-doped polysilicon layer on the entire surface of the resultant material, and performing an etch back process on the entire surface of the conductive layer. A process of forming a landing pad LP by filling a conductive layer in the first and second contact holes is described. In this case, a chemical mechanical polishing (CMP) process may be applied instead of the etch back process.
제3a도 및 제3b도는 본 발명에 따른 랜딩 패드 형성방법의 다른 실시예를 나타낸 공정순서도이다.3a and 3b is a process flow diagram showing another embodiment of the landing pad forming method according to the present invention.
제3a도는 절연막(30), 콘택 홀(CH) 및 포토레지스트 패턴(PR)의 형성공정을 도시한 것으로, 먼저 제1전도형의 반도체기판(100)에 소자형성을 위한 액티브영역과 이 액티브영역을 분리시켜 주기 위한 필드산화막(101)을 통상적인 방법을 이용하여 형성한 후, 상기 액티브영역상에 게이트절연막(도시되지 않음)이 개재된 게이트전극(1), 소오스영역(2) 및 드레인영역(3)으로 이루어지는 정보전달용 트랜지스터를 형성한다. 계속해서 결과물 전면에 소정두께 예컨대 수백Å∼수천Å의 두께로 절연막(30)을 형성하고, 이 절연막(30)위에 포토레지스트 도포, 마스크노광 및 현상 등의 공정을 거쳐 랜딩 패드의 도전층이 형성될 부위의 절연막이 노출되도록 포토레지스트 패턴(PR)을 형성한 후, 이 포토레지스트 패턴(PR)을 적용하여 상기 절연막(30)을 1차로 등방성 식각함으로써 언더컷(undercut)이 되도록 한 후 2차로 이방성 식각을 실시함으로써 언더컷이 된 콘택 홀(CH)을 형성한다. 이와 같이 형성된 콘택 홀(CH)의 상부는 등방성식각에 의해 사이즈(size)가 크고 하부(45)는 이방성식각만 되기 때문에 사이즈를 작게 할 수 있다. 여기서, 상기 등방성 식각전에 약간의 이방성 식각을 할 수도 있다. 미설명부호 4는 상기 게이트전극을 보호하기 위한 절연막을 나타낸다.3A illustrates a process of forming the insulating film 30, the contact hole CH, and the photoresist pattern PR. First, an active region for forming an element in the first conductive semiconductor substrate 100 and the active region are formed. After forming the field oxide film 101 to separate the oxide by a conventional method, the gate electrode 1, the source region 2 and the drain region having a gate insulating film (not shown) interposed on the active region. An information transfer transistor comprising (3) is formed. Subsequently, an insulating film 30 is formed on the entire surface of the resultant at a predetermined thickness, for example, several hundreds to several thousands, and a conductive layer of a landing pad is formed on the insulating film 30 through a process such as photoresist coating, mask exposure, and development. After the photoresist pattern PR is formed to expose the insulating film of the portion to be exposed, the photoresist pattern PR is applied to the undercut by first isotropically etching the insulating film 30 and then anisotropically. The etching is performed to form the undercut contact holes CH. Since the upper portion of the contact hole CH formed as described above is large in size by isotropic etching and the lower portion 45 is only anisotropic etching, the size can be reduced. Here, some anisotropic etching may be performed before the isotropic etching. Reference numeral 4 denotes an insulating film for protecting the gate electrode.
제3b도는 상기 포토레지스트 패턴의 제거후 결과물 전면에 패드 폴리용 도전층 예컨대 불순물이 도우핑된 다결정실리콘을 침적하고, 이 도전층 전면에 대하여 에치 백 공정을 실시함으로써 상기 콘택 홀내에 도전층을 채워 랜딩 패드(LP)를 형성하는 공정을 나타낸다. 이때, 상기 에치 백 공정 대신에 CMP 공정을 적용할 수도 있다.FIG. 3B shows a pad layer conductive layer, for example, polysilicon doped with impurities, is deposited on the entire surface of the resultant after removing the photoresist pattern, and the conductive layer is filled in the contact hole by performing an etch back process on the entire surface of the conductive layer. The process of forming the landing pad LP is shown. In this case, a CMP process may be applied instead of the etch back process.
이상에서 살펴본 바와 같이 본 발명에서는 랜딩 패드 형성을 위한 콘택 홀의 형성시에 등방성 식각과 이방성 식각을 함께 실시함으로써 상기 콘택 홀의 상부의 사이즈가 하부의 사이즈 보다 크게 되어, 고집적화에 따른 사진식각공정울 극복할 수 있을 뿐만 아니라, 패드폴리가 형성될 부위에 절연막을 식각해 낸 후 패드 폴리를 채워넣기 때문에 하부층(즉 게이트전극) 토포그래피(topography)에 의한μ-브리지 발생염려가 없는 장점이 있다.As described above, in the present invention, when the contact hole for forming the landing pad is formed, the isotropic etching and the anisotropic etching are performed together to make the upper part of the contact hole larger than the lower part, thereby overcoming the photolithography process due to the high integration. In addition, since the insulating layer is etched on the site where the pad poly is to be formed and then the pad poly is filled, there is an advantage that there is no fear of generating the mu bridge due to the top layer of the lower layer (ie, the gate electrode).
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950046907A KR0183764B1 (en) | 1995-12-05 | 1995-12-05 | Landing pad |
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| KR1019950046907A KR0183764B1 (en) | 1995-12-05 | 1995-12-05 | Landing pad |
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| KR0183764B1 true KR0183764B1 (en) | 1999-04-15 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000019959A (en) * | 1998-09-16 | 2000-04-15 | 김영환 | Method for forming plug of semiconductor device |
| KR100451987B1 (en) * | 2002-06-29 | 2004-10-08 | 주식회사 하이닉스반도체 | A method for forming a contact hole of a semiconductor device |
| KR100451989B1 (en) * | 2002-06-29 | 2004-10-08 | 주식회사 하이닉스반도체 | A method for forming a metal line of semiconductor device |
| KR100451990B1 (en) * | 2002-06-29 | 2004-10-08 | 주식회사 하이닉스반도체 | Manufacturing Method of Semiconductor Device |
| KR100443522B1 (en) * | 1997-06-26 | 2004-10-26 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device using multilayer oxide patterns |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100477135B1 (en) * | 1997-08-08 | 2005-06-29 | 삼성전자주식회사 | Manufacturing method of semiconductor device |
| KR100458296B1 (en) * | 1997-12-31 | 2005-02-07 | 주식회사 하이닉스반도체 | Method for forming contact hole of semiconductor device to easily form self-aligned contact pattern and enlarge desired plug size |
| KR100505101B1 (en) * | 1998-08-28 | 2005-09-26 | 삼성전자주식회사 | Method of forming contact for semiconductor device |
-
1995
- 1995-12-05 KR KR1019950046907A patent/KR0183764B1/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100443522B1 (en) * | 1997-06-26 | 2004-10-26 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device using multilayer oxide patterns |
| KR20000019959A (en) * | 1998-09-16 | 2000-04-15 | 김영환 | Method for forming plug of semiconductor device |
| KR100451987B1 (en) * | 2002-06-29 | 2004-10-08 | 주식회사 하이닉스반도체 | A method for forming a contact hole of a semiconductor device |
| KR100451989B1 (en) * | 2002-06-29 | 2004-10-08 | 주식회사 하이닉스반도체 | A method for forming a metal line of semiconductor device |
| KR100451990B1 (en) * | 2002-06-29 | 2004-10-08 | 주식회사 하이닉스반도체 | Manufacturing Method of Semiconductor Device |
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| KR970052198A (en) | 1997-07-29 |
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