KR0166491B1 - Capacitor fabrication method of semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a capacitor of a semiconductor device, wherein the bottom insulating layer is partially etched using a photoresist pattern so as not to expose the bottom structure, and the etching process using the same exposes a predetermined portion of the semiconductor substrate. After forming the holes, a predetermined thickness is formed on the entire surface of the first conductive layer, spacers are formed on the sidewalls of the sacrificial film formed using another photoresist pattern, and then anisotropic etching is performed to expose the exposed layer. By removing the insulating film or the sacrificial film to form a storage electrode having an increased surface area, a capacitor capable of securing a sufficient capacitance in a later process can be formed, thereby improving reliability and high integration of semiconductor devices.

Description

Capacitor Manufacturing Method of Semiconductor Device

1 is a cross-sectional view showing a capacitor manufacturing process of a semiconductor device formed in accordance with an embodiment of the prior art.

2A to 2D are cross-sectional views showing a capacitor manufacturing process of the semiconductor device according to the first embodiment of the present invention.

3A to 3D are sectional views showing a capacitor manufacturing process of a semiconductor device according to Embodiment 2 of the present invention.

* Explanation of symbols for main parts of the drawings

11, 31, 51: semiconductor substrate 12, 32, 52: device isolation oxide film

13, 33, 53: gate oxide film 14, 34, 54: gate electrode

15, 35, 55: oxide film spacer

16, 16 ', 36, 36', 56, 56 ': impurity diffusion region

17, 37, 57: lower insulation side 18, 38: silicon nitride film

19, 40: First photosensitive film 20, 39: First oxide film

21, 42, 59: first polysilicon film 22, 41: second oxide film

23, 44, 65: second polycrystalline silicon film

24, 45, 64: dielectric film 25, 46: third polysilicon film

27, 47, 58: contact hole 43: third oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a technique of increasing the surface area of a storage electrode in order to secure sufficient capacitance required as a semiconductor device is highly integrated.

Since the semiconductor device is highly integrated and the cell size is reduced, it is difficult to sufficiently secure a capacitance proportional to the surface area of the storage electrode.

In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip, which is an important factor for high integration of the DRAM device.

Therefore, in order to increase the capacitance of the capacitor, a method of using a material having a high dielectric constant as the dielectric film, forming a thin dielectric film, or increasing the surface area of the capacitor is used.

However, dielectric materials with high dielectric constants. For example, Ta ₂ O ₅ , TiO ₂ , SrTiO ₃ , and the like have not been confirmed with reliability and thin film characteristics. Therefore, it is difficult to apply to the actual device. In addition, reducing the thickness of the dielectric film has a problem in that the dielectric film is destroyed during operation of the device, thereby lowering the reliability of the capacitor, thereby making it difficult to achieve high integration of the semiconductor device.

1 is a cross-sectional view showing a capacitor formed by the prior art.

Referring to FIG. 1, the device isolation oxide film 52, the gate oxide film 53, the gate electrode 54, the oxide spacer 55, and the impurity diffusion regions 56 and 56 ′ are sequentially formed on the semiconductor substrate 51. To form. A lower insulating layer 57 is formed to planarize the entire structure. A contact hole 58 is formed to expose the impurity diffusion region 56 formed on the semiconductor substrate 51 by an etching process using a contact mask (not shown). A first polysilicon film 59 is formed to be connected to the semiconductor substrate 51 through the contact hole 58. The first polysilicon layer 59 is etched using a storage electrode mask. Then, the dielectric film 65 and the second polysilicon film 65 are formed on the entire surface. In this case, the dielectric film 64 has a complex structure of NO or ONO. The second polysilicon film 65 is used as a plate electrode. In addition, the plate electrode may be formed of polyside.

Therefore, in order to solve the problems of the prior art, the surface area is increased by using a partial etching process using a photoresist pattern, a spacer forming process, a process of forming a conductive layer having excellent step coverage ratio, and an insulating film removal process. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device capable of forming an electrode and securing a capacitance sufficient for high integration of the semiconductor device in a later step.

Features of the present invention for achieving the above object,

Forming a first photoresist pattern on the semiconductor substrate including the lower insulating layer and the first insulating layer, the first photoresist layer pattern exposing a predetermined portion of the storage electrode contact portion;

Etching the first insulating layer and the lower insulating layer having a predetermined thickness using the first photoresist pattern as a mask;

Forming a second insulating film spacer on an etched surface of the first insulating film and the lower insulating layer and on sidewalls of the first photoresist film pattern;

Forming a contact hole exposing a predetermined portion to the storage electrode contact portion using the first photoresist pattern and the second insulating layer spacer as a mask;

Removing the first photoresist pattern;

Forming a first thickness on the entire surface of the first conductive layer connected to the semiconductor substrate;

Forming a sacrificial insulating film to planarize the entire upper surface thereof;

Forming a second photoresist pattern on the sacrificial insulating layer and etching the sacrificial insulating layer using the mask as a mask;

Forming a second thickness on the entire surface of the second conductive layer,

Forming a second conductive layer spacer on the sidewall of the sacrificial insulating layer by anisotropically etching the second conductive layer, but overetching the thickness of the first and second conductive layers;

And removing the sacrificial insulating film to form a storage electrode having an increased surface area.

Other features of the present invention for achieving the above object,

Forming a first photoresist layer pattern on the semiconductor substrate on which the lower insulating layer, the first insulating layer, and the second insulating layer are stacked to expose a predetermined portion as a storage electrode contact portion;

Etching the second insulating film, the first insulating film, and a lower insulating layer having a predetermined thickness using the first photoresist pattern as a mask;

Forming a third insulating film spacer on an etched surface of the second insulating film, the first insulating film and the lower insulating layer, and a sidewall of the first photoresist film pattern;

Forming a contact hole exposing a predetermined portion to the storage electrode contact portion using the first photoresist pattern and the third insulating layer spacer as a mask;

Removing the first photoresist pattern;

Forming a first thickness on the entire surface of the first conductive layer connected to the semiconductor substrate;

Forming a sacrificial insulating film to planarize the entire upper surface thereof;

Forming a second photoresist pattern on the sacrificial insulating layer and etching the sacrificial insulating layer using the mask as a mask;

Forming a second thickness on the entire surface of the second conductive layer,

Forming a second conductive layer spacer on the sidewall of the sacrificial insulating layer by anisotropically etching the second conductive layer, but overetching the thickness of the first and second conductive layers;

And removing the third insulating film, the second insulating film, and the sacrificial insulating film to form a storage electrode having an increased surface area.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a capacitor manufacturing process of the semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 2A, the device isolation oxide film 12, the gate oxide film 13, the gate electrode 14, the oxide spacer 15, and the impurity diffusion regions 16 and 16 ′ are sequentially formed on the semiconductor substrate 11. To form. A lower insulating layer 17 is formed to planarize the entire upper surface. A silicon nitride film 18 is formed on the lower insulating layer 17.

A first photoresist layer 19 pattern is formed on the silicon nitride layer 18, and the silicon nitride layer 18 and the lower insulating layer 17 having a predetermined thickness are sequentially etched using the mask. In this case, the etching process using the first photoresist layer 19 pattern is performed so that the gate electrode 14 is not exposed.

Next, a spacer of the first oxide film 20 is formed on sidewalls of the lower photosensitive layer 19 and the lower insulating layer 17 etched. At this time, the first oxide film 20 spacer is formed by forming a first oxide film 20 with a predetermined thickness on the entire surface and performing an anisotropic etching process.

Referring to FIG. 2B, the storage electrode contact hole 27 exposing the impurity diffusion region 16 of the semiconductor substrate 11 using the first photoresist layer 19 pattern and the first oxide layer 20 spacer as a mask. To form. Then, the first photosensitive film 19 pattern is removed.

Then, a first thickness polycrystalline silicon film 21 is formed on the entire surface. In this case, the first polysilicon layer 21 may be formed of a conductive material having a polyside or similar properties as a conductive layer. Next, a second oxide film 22 is formed to planarize the entire upper surface portion.

Referring to FIG. 2C, the second oxide layer 22 is etched using a second photoresist pattern (not shown). In this case, the second photoresist layer pattern is formed smaller than the storage electrode to be formed, and is formed in consideration of the thickness of the second polysilicon layer spacer formed in a later step.

Next, a second polycrystalline silicon film 23 is formed over the entire surface. In this case, the second polysilicon layer 23 may be formed of a polyside or a similar conductive material as a conductor. Thereafter, anisotropic etching is performed to the thickness of the first polysilicon film 21 and the second polysilicon film 23 to form a spacer of the second polysilicon film 23 on the sidewall of the second oxide film 22. Form.

Referring to FIG. 2D, the storage electrodes 21 and 23 having an increased surface area are formed by removing the second oxide layer 22. At this time, the second oxide film 22 is used as an auxiliary material for forming a structure having a different shape and is called a sacrificial film. The sacrificial film may be formed using an SOG, a CVD oxide film, or a polyimide.

Then, by forming the dielectric film 24 and the third polycrystalline silicon film 25 on the entire surface, sufficient capacitance required by the highly integrated semiconductor element can be ensured. In this case, the dielectric film 24 is formed of a material having excellent dielectric properties. Here, the dielectric film 24 is formed of a NO or ONO composite structure. The third polysilicon film 25 is used as a plate electrode. Here, the plate electrode may be formed of a polyside or a similar conductive material.

3A to 3D are cross-sectional views showing a capacitor manufacturing process of the semiconductor device according to the second embodiment of the present invention.

Referring to FIG. 3A, the device isolation oxide film 32, the gate oxide film 33, the gate electrode 34, the oxide spacer 35, and the impurity diffusion regions 36 and 36 ′ are sequentially formed on the semiconductor substrate 31. To form. A lower insulating layer 37 is formed to planarize the entire upper surface. The silicon nitride film 38 and the first oxide film 39 are sequentially formed on the lower insulating layer 37.

In addition, a first photoresist layer 40 pattern is formed on the first oxide layer 39. In this case, the first photoresist layer 40 pattern is formed to expose the contact portion of the semiconductor substrate 31.

Next, the first oxide layer 39, the silicon nitride layer 38, and the lower insulating layer 37 having a predetermined thickness are sequentially etched by an etching process using the first photoresist layer 40 pattern. At this time, the etching process of the lower insulating layer 37 is performed so that the gate electrode 34 is not exposed.

A spacer of the second oxide layer 41 is formed on sidewalls of the first photoresist layer 40, the first oxide layer 39, the silicon nitride layer 38, and the etched lower insulating layer 37. At this time, the second oxide film 41 spacers are formed by forming a predetermined thickness of the second oxide film 41 on the entire surface and anisotropically etching them.

Referring to FIG. 3B, the first photoresist film 40 pattern is removed. Then, a first polycrystalline silicon film 42 is formed over the entire surface so as to be connected to the semiconductor substrate 31. In this case, the first polysilicon layer 42 may be formed of a polyside or a similar conductive material as a conductor.

Next, a third oxide film 43 is formed to planarize the entire upper surface portion. In this case, the third oxide layer 43 is called a sacrificial layer by forming and removing the structure of the capacitor to be formed in a later process. The sacrificial film may be formed of SOG, CVD oxide film or polyimide.

Referring to FIG. 3C, the third oxide layer 43 is etched by using a second photoresist layer pattern (not shown) on the third oxide layer 43. In this case, the second photoresist layer pattern is formed smaller than the storage electrode, and is formed in consideration of the thickness of the second conductive layer spacer formed in a later process.

Then, a second polycrystalline silicon film 44 is formed on the entire surface at a constant thickness. The first polysilicon layer 42 and the second polysilicon layer 44 are etched by a thickness to form a second polysilicon layer 44 spacer on the sidewall of the third oxide layer 43. In this case, the etching process uses the first oxide layer 39 as an etching barrier.

Referring to FIG. 3D, the storage electrodes 41 and 44 having an increased surface area are formed by removing the first oxide film 39, the second oxide film 41 spacer, and the third oxide film 43. In this case, the first, second, and third insulating layers 39, 41, and 43 may be removed by a wet method using a difference in etching selectivity from the first and second polysilicon layers 41 and 44.

Then, by forming the dielectric film 45 and the third polysilicon film 46 on the entire surface, it is possible to ensure a sufficient capacitance for the operation of highly integrated semiconductor devices. In this case, the dielectric film 45 is formed of a material having excellent dielectric properties. Here, the dielectric film 45 is formed of a NO or ONO composite structure. The third polysilicon film 46 is used as a plate electrode. Here, the plate electrode may be formed of a polyside or a similar conductive material.

As described above, the method of manufacturing a capacitor of a semiconductor device according to the present invention includes an insulating film spacer forming process using a photosensitive film pattern, a conductive layer spacer process using a sacrificial film, a conductive layer forming process having excellent step coverage ratio, and an etching selectivity. Advantages of enabling high integration of semiconductor devices and improving reliability by forming storage electrodes with increased surface area through the insulating film removal process using the difference and forming capacitors having a capacitance sufficient for high integration of semiconductor devices in subsequent processes. There is this.

Claims (16)

Forming a first photoresist pattern on the semiconductor substrate including the lower insulating layer and the first insulating layer to expose a predetermined portion of the storage electrode contact; and using the first photoresist pattern as a mask, the first photoresist layer has a predetermined thickness. Etching the lower insulating layer, forming a second insulating film spacer on an etched surface of the first insulating film and the lower insulating layer and sidewalls of the first photosensitive film pattern, masking the first photosensitive film pattern and the second insulating film spacer Forming a contact hole exposing a predetermined portion to the storage electrode contact portion, removing the first photoresist pattern, and forming a first conductive layer connected to the semiconductor substrate at a predetermined thickness on an entire surface thereof. Forming a sacrificial insulating film to planarize the entire upper surface, and forming a second photoresist pattern on the sacrificial insulating film and using the mask as a mask. Etching the sacrificial insulating film, forming a second conductive layer on the entire surface of the sacrificial insulating film, and etching the second conductive layer anisotropically by overetching the second conductive layer by the thickness of the first and second conductive layers. And forming a storage electrode having a surface area increased by removing the sacrificial insulating film. The method of claim 1, wherein the first insulating layer is formed of a silicon nitride film. The method of claim 1, wherein the etching of the lower insulating layer is performed so as not to expose the structure formed on the lower insulating layer. The method of claim 1, wherein the size of the contact hole is determined according to a thickness of the second insulating layer spacer. The method of claim 1, wherein the first conductive layer and the second conductive layer are formed of a polycrystalline silicon film. The method of claim 1, wherein the second photoresist layer pattern is smaller than a predetermined storage electrode. The method of claim 1, wherein the anisotropic etching process of the second conductive layer is performed using the first insulating layer as an etch barrier. The method of claim 1, wherein the sacrificial insulating layer is removed by a wet method using a difference in etching selectivity from the first and second conductive layers. The method of claim 1 or 8, wherein the sacrificial insulating film is formed of SOG, CVD oxide film or polyimide. Forming a first photoresist pattern on the semiconductor substrate on which the lower insulating layer, the first insulation film, and the second insulation film are stacked; exposing a portion intended as a storage electrode contact portion; and using the first photoresist pattern as a mask, the second insulation film Etching a first insulating film and a lower insulating layer having a predetermined thickness, forming a third insulating film spacer on an etch surface of the second insulating film, the first insulating film and the lower insulating layer, and sidewalls of the first photoresist pattern; Forming a contact hole exposing a predetermined portion to the storage electrode contact portion using the first photoresist pattern and the third insulating layer spacer as a mask, removing the first photoresist pattern, and a second connection to the semiconductor substrate (1) forming a conductive layer on the entire surface with a predetermined thickness, forming a sacrificial insulating film to planarize the entire surface, and forming a second photoresist pattern on the sacrificial insulating film. And etching the sacrificial insulating film using the mask, forming a second conductive layer on the entire surface of the sacrificial layer, and anisotropically etching the second conductive layer, the thickness of the first and second conductive layers. A process of forming a second conductive layer spacer on the sidewalls of the sacrificial insulating layer by transient etching, and forming a storage electrode having an increased surface area by removing the third insulating layer, the second insulating layer, and the sacrificial insulating layer. Manufacturing method. The method of claim 10, wherein the first insulating layer is formed of a silicon nitride layer. The method of claim 10, wherein a size of the contact hole is determined according to a thickness of the second insulating layer spacer. The method of claim 10, wherein the first conductive layer and the second conductive layer are formed of a polycrystalline silicon film. The method of claim 10, wherein the second photoresist pattern is smaller than a predetermined storage electrode. The method of claim 10, wherein the anisotropic etching of the second conductive layer is performed by using the second insulating layer as an etch barrier. The method of claim 10, wherein the second insulating layer, the third insulating layer, and the sacrificial layer are removed by a wet method using an etch selectivity difference between the first and second conductive layers.