JPS57157567A - Vertical type p-n-p transistor - Google Patents

Vertical type p-n-p transistor

Info

Publication number
JPS57157567A
JPS57157567A JP4359381A JP4359381A JPS57157567A JP S57157567 A JPS57157567 A JP S57157567A JP 4359381 A JP4359381 A JP 4359381A JP 4359381 A JP4359381 A JP 4359381A JP S57157567 A JPS57157567 A JP S57157567A
Authority
JP
Japan
Prior art keywords
region
type
layer
epitaxial layer
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4359381A
Other languages
Japanese (ja)
Inventor
Kazuo Takeda
Teruo Tabata
Kunio Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP4359381A priority Critical patent/JPS57157567A/en
Publication of JPS57157567A publication Critical patent/JPS57157567A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the current capacity of a vertical type P-N-P transistor by diffusing and forming a buried region in a semiconductor substrate, laminating and growing the first thin epitaxial layer ad the second thick epitaxial layer on the overall surface including the buried layer and forming a collector region in the first epitaxial layer on the buried layer. CONSTITUTION:An N<+> type buried region 24 is diffused and formed in a P type Si substrate 21, a thin N type layer 22 is epitaxially grown on the overall surface including the region 24, and a P<+> type collector region 26 smaller than the region 24 is diffused and formed in the layer 22 on the region 24. Then, an N type base layer 23 of the same N type thicker than the layer 22 is epitaxially grown on the overall surface, the volumn of the region 26 is simultaneously increased by the heat treatment at this time, is floated into the layer 23, the epitaxial layer is formed insularly while containing the region 26 by a P<+> type isolation region 25 reaching the substrate 21, and an annular P<+> type collector leading region 27 contacted with the end of the region 26, an N type base contacting region 30 disposed in the region 27 and a P<+> type emitter region 29 are respectively diffused and formed in the epitaxial layer.
JP4359381A 1981-03-24 1981-03-24 Vertical type p-n-p transistor Pending JPS57157567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4359381A JPS57157567A (en) 1981-03-24 1981-03-24 Vertical type p-n-p transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4359381A JPS57157567A (en) 1981-03-24 1981-03-24 Vertical type p-n-p transistor

Publications (1)

Publication Number Publication Date
JPS57157567A true JPS57157567A (en) 1982-09-29

Family

ID=12668090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4359381A Pending JPS57157567A (en) 1981-03-24 1981-03-24 Vertical type p-n-p transistor

Country Status (1)

Country Link
JP (1) JPS57157567A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172738A (en) * 1983-03-22 1984-09-29 Sanyo Electric Co Ltd Vertical type p-n-p transistor
JP2014203851A (en) * 2013-04-01 2014-10-27 株式会社東芝 Semiconductor device and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172738A (en) * 1983-03-22 1984-09-29 Sanyo Electric Co Ltd Vertical type p-n-p transistor
JP2014203851A (en) * 2013-04-01 2014-10-27 株式会社東芝 Semiconductor device and manufacturing method of the same

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