JP3911268B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit used for a class D amplifier or the like.

  In recent years, class D amplifiers have been developed that incorporate higher-precision protection circuits in place of class AB amplifiers that have been widely used so far. As means for realizing this highly accurate protection circuit, a level shift circuit for the purpose of preventing malfunction and erroneous detection is necessary.

  The operation of the conventional level shift circuit will be described below. FIG. 3 is a circuit diagram showing a configuration of a conventional level shift circuit, and FIG. 4 is a timing chart showing each voltage waveform of the conventional level shift circuit.

In FIG. 3, 1 is a detection circuit, 2 is an inverter, 3 is a transistor, 4 is a transistor, 5 is a resistor, 6 is an inverter, 13 is a resistor, and 15 is a cutoff circuit that shuts off the drive circuit by a signal of an abnormal operation detection terminal, 16 is an abnormal operation detection terminal (Vdet), 17 is an input terminal (Vin) of a class D amplifier, 18 is a bootstrap, 19 is a power supply of a lower circuit, 20 is a power supply voltage terminal (Vcc), and 21 is a class D amplifier. Output terminal (Vout), 22 is a negative power supply voltage terminal (VL), 23 is an upper output transistor, 24 is a lower output transistor, 25 is a drive circuit for driving the upper output transistor 23, and 26 is a lower output transistor 24. driving driving circuit, a signal level shift circuit for transmitting a signal of the lower circuit to the upper circuit 27, the upper circuit to power the bootstrap 18 51, 52 power supply 19 A lower circuit for the power supply.

  In FIG. 4, 101 is a voltage waveform of the bootstrap 18, 102 is an output voltage waveform of the drive circuit 25, 103 is a voltage waveform of the output terminal 21, 104 is an output voltage waveform of the detection circuit 1, and 105 is a base (gate) of the transistor 4. ) Is a voltage waveform at the abnormal operation detection terminal 16.

  As shown in FIG. 3, the conventional level shift circuit includes a detection circuit 1, inverters 2 and 6, transistors 3 and 4, resistors 5 and 13, a bootstrap 18, and a power supply 19. The operation of the level shift circuit configured as described above will be described below.

  First, when an abnormal operation is detected in the upper circuit 51 by the detection circuit 1, the inverter 2 receives the high (H) signal and the transistor 3 becomes conductive, and the voltage generated by the resistor 5 becomes the threshold voltage of the transistor 4. If it exceeds, a signal is transmitted, and when an abnormal operation occurs by the inverter 6, a high (H) signal is output to the abnormal operation detection terminal (Vdet) 16 (level shift operation). By receiving the detection signal and operating the cutoff circuit 15, it is possible to prevent destruction and deterioration of the class D amplifier.

  However, the output signal of the class D amplifier using the level shift circuit having such a configuration is a signal like a waveform 103 that repeats between VL and Vcc, and the output of the drive circuit 25 that drives the upper output transistor 23 has a waveform 102. It becomes like this. As means for realizing this waveform, a voltage higher by Vdd than Vcc is supplied to the upper circuit 51 using the bootstrap 18. Therefore, the output waveform of the bootstrap 18 is as shown by the waveform 101.

  If the output voltage of the detection circuit 1 shown in FIG. 3 has a waveform 104 shown in FIG. 4, the base voltage of the transistor 3 is fixed by the parasitic capacitance 28 formed between the base (gate) and the collector (drain) of the transistor 3. When the bootstrap 18 that is a power supply changes suddenly, the base-emitter voltage is opened, and the threshold voltage of the transistor 3 is exceeded, and the transistor 3 becomes conductive. The conduction of the transistor 3 causes a current to flow into the resistor 5, the transistor 4 is turned on as in the waveform 105 (C), and the output of the abnormal operation detection terminal 16 is output as in the waveform 106 (D). There was a problem that the state of existed.

  The present invention is directed to solving the above-described problems of the prior art. The detection signal is not generated due to the influence of the parasitic capacitance, and the abnormality detection signal of the upper circuit is transmitted to the lower circuit, and erroneous detection is performed. An object is to provide an improved level shift circuit.

To achieve this object, a level shift circuit according to the present invention receives a signal from an input terminal to drive a lower output transistor, and receives the signal from the input terminal to drive an upper output transistor. A level shift circuit of an amplifier circuit comprising an upper circuit, one end connected to a bootstrap that supplies power to the upper circuit, a detection circuit that detects an abnormality in the upper circuit, and a ground of the lower circuit One end is connected to the ground of the lower circuit, and first detection means for outputting a signal generated by converting the signal at the output terminal of the detection circuit into a current and the other end of the first resistor. Second detection means for outputting a signal generated by converting the signal of the output terminal of the amplifier circuit into a current at the other end of the second resistor, and output signals of the first and second detection means Output the logical product of And a detection circuit using the output difference between the first and second detection means set by the difference in resistance value between the first and second resistors to prevent erroneous detection of the detection circuit. .
A level shift circuit of an amplifier circuit comprising: a lower circuit that receives a signal from an input terminal and drives a lower output transistor; and an upper circuit that receives a signal from the input terminal and drives an upper output transistor. a bootstrap supply power to the upper circuit, a detection circuit for detecting an abnormality of the upper circuit, a first inverter connected to the input end to the output terminal of the detection circuit, the output of the first inverter connect one end and a base or gate, the connects the output portion and the emitter or source of bootstrapping, a first transistor connected to the ground via the collector or drain of the first resistor, the collector of said first transistor or by connecting the drain and the base or gate, a second transistor the emitter or source connected to the ground When, a second inverter connected to the collector or drain and the input terminal of said second transistor, said output terminal of the amplifier circuit and the third inverter connected to the input terminal, the output terminal of said third inverter A third transistor connected to a base or gate; an output unit of the bootstrap; an emitter or a source; a collector or drain; and a ground connected via a first resistor; and a collector or drain of the third transistor And a base or gate, and an emitter or source connected to the ground, a collector or drain of the fourth transistor, a first input terminal, an output terminal of the second inverter , and a second transistor connects the input end, an output end and interruption circuit for interrupting the driving of the upper and lower circuit And a NAND gate connected said first, said second caused by the difference in the resistance value set by the second resistor, and configured to prevent erroneous detection of the detection circuit with a conduction time difference of the fourth transistor It is characterized by that.

  According to the above configuration, it is possible to improve the false detection during the level shift operation by canceling the false detection signal caused by the influence of the parasitic capacitance and operating the detection circuit.

  As described above, according to the present invention, when the abnormality detection signal of the upper circuit is transmitted to the lower circuit, the false detection caused by the parasitic capacitance is improved, and a level shift circuit free from malfunction and false detection is realized. There is an effect that can be done.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a level shift circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing respective voltage waveforms of the level shift circuit according to the present embodiment. Here, components having substantially the same functions corresponding to the components described in FIG. 3 showing the conventional example are denoted by the same reference numerals.

  In FIG. 1, 1 is a detection circuit for detecting an abnormality in the upper circuit 53 supplied with power from the upper output transistor 23 and the bootstrap 18, and 2, 6, 10, and 12 are first, second, third, and fourth. Inverter, 3 is a first transistor controlled by receiving a signal from detection circuit 1, 4 is a second transistor that performs a level shift operation on the signal from transistor 3, 5, 8 are first and second resistors, and 7 is A third transistor for level-shifting the signal of the fourth transistor 9 controlled by receiving the signal at the output terminal 21 of the class D amplifier, 11 is a NAND gate, and 13 and 14 are resistors.

Further, 15 is a shut-off circuit that shuts off the drive circuit by a signal from the abnormal operation detection terminal (Vdet) 16, 17 is an input terminal (Vin) of the class D amplifier, 19 is a power supply for the lower circuit 54, and 20 is a power supply voltage terminal ( Vcc), 22 is a negative power supply voltage terminal (VL), 24 is a lower output transistor, 25 is a drive circuit for the upper output transistor 23, 26 is a drive circuit for the lower output transistor 24, and 27 is an upper drive for the input signal. A signal level shift circuit for converting the signal of the circuit 25, 28 is a parasitic capacitance formed between the base (gate) and collector (drain) of the transistor 3, and 29 is a parasitic capacitance formed between the base (gate) and collector (drain) of the transistor 9 Capacitors 30 and 31 are inverters.

  2, 101 is a voltage waveform of the bootstrap 18, 102 is an output voltage waveform of the drive circuit 25, 103 is a voltage waveform of the output terminal 21, 104 is an output voltage waveform of the detection circuit 1, and 105 is a base of the transistor 4. 1 is a voltage waveform at point A in FIG. 1, 201 is a voltage waveform at the base (gate) of the transistor 7, 202 is a voltage waveform at point B in FIG. 1, and 203 is an abnormal operation detection terminal 16. This is a voltage waveform.

  The level shift circuit of the present embodiment includes a detection circuit 1, resistors 5, 8, 13, and 14, inverters 2, 6, 10, 12, 30, and 31, transistors 3, 4, 7, and 9, NAND A gate 11, a bootstrap 18, and a power source 19 are included.

  The operation of the level shift circuit of the present embodiment configured as described above will be described below with reference to FIGS.

  The output signal of the class D amplifier is a signal having a waveform 103 shown in FIG. 2 that repeats between VL and Vcc, and the output of the drive circuit 25 that drives the upper output transistor 23 has a waveform 102. As means for realizing this waveform, a voltage higher than Vcc by Vdd is supplied to the upper circuit 53 using the bootstrap 18. Therefore, the voltage waveform of the bootstrap 18 is as shown by the waveform 101.

  If the output voltage of the detection circuit 1 has a waveform 104, the base voltage is fixed by the parasitic capacitance 28 formed between the base (gate) and the collector (drain) of the transistor 3, and the bootstrap 18 as a power source By sudden change, the base-emitter (gate-source) voltage is opened, and the transistor 3 is turned on by exceeding the threshold voltage of the transistor 3. Due to the conduction of the transistor 3, a current is supplied to the resistor 5, the transistor 4 is turned on as in the waveform 105 (E), and the output of the abnormal operation detection terminal 16 is output as in the waveform 106 '(F).

  When the abnormal operation in the upper circuit 53 is detected by the detection circuit 1, the inverter 2 receives the detection signal of the waveform 104 (G), the transistor 3 becomes conductive, and the voltage generated by the resistor 5 is the threshold value of the transistor 4. When the voltage exceeds the voltage, a signal is transmitted, and when an abnormal operation occurs by the inverter 6, a high (H) signal is output as shown by a waveform 106 '(J).

  Next, the inverter 10 and the transistor 9 that have received a signal from the output terminal 21 of the class D amplifier have a base voltage fixed by a parasitic capacitance 29 formed between the base (gate) and the collector (drain) of the transistor 9 and are power sources. When the bootstrap 18 changes suddenly, the base-emitter voltage (gate-source) is opened, and the threshold voltage of the transistor 9 is exceeded, and the transistor 9 becomes conductive. The conduction of the transistor 9 causes a current to flow through the resistor 8, exceeding the threshold voltage of the transistor 7, thereby turning on the transistor 7.

  At this time, the resistance value R1 of the resistor 5 and the opposite value R2 of the resistor 8 are set as R1 <R2, and the waveform 201 of the base voltage of the transistor 7 has a threshold voltage that is longer than the base voltage of the transistor 4. It will exceed. That is, the conduction time of the transistor 7 is longer than the conduction time of the transistor 4.

  The conduction signal of the transistor 7 takes an inverted signal and has a waveform 202. Since the erroneous detection signal is the waveform 106 ′ (F), the logical product of the waveform 106 ′ (point A in FIG. 1) and the waveform 202 (point B in FIG. 1) is taken to obtain the erroneous detection signal as in the waveform 203. Waveform 106 '(F) can be deleted.

  As a result, the abnormality detection signal of the upper circuit 53 is transmitted to the lower circuit 54, and a level shift circuit with improved erroneous detection can be realized.

  The level shift circuit according to the present invention improves the erroneous detection caused by the parasitic capacitance when transmitting the abnormality detection signal of the upper circuit to the lower circuit, and can eliminate malfunction and erroneous detection. It is useful for level shift circuits.

The circuit diagram which shows the structure of the level shift circuit in embodiment of this invention Timing chart showing each voltage waveform of the level shift circuit in the embodiment of the present invention Circuit diagram showing the configuration of a conventional level shift circuit Timing chart showing voltage waveforms of conventional level shift circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Detection circuit 2,6,10,12,30,31 Inverter 3,4,7,9 Transistor 5,8,13,14 Resistance 11 NAND gate 15 Cutoff circuit 16 Abnormal operation detection terminal 17 Input terminal 18 Bootstrap 19 Power supply 20 power supply voltage terminal 21 output terminal 22 negative power supply voltage terminal 23 upper output transistor 24 lower output transistor 25, 26 drive circuit 27 signal level shift circuit 28, 29 parasitic capacitance 51, 53 upper circuit 52, 54 lower circuit 101 boot Voltage waveform 102 of the strap 18 Output voltage waveform 103 of the drive circuit 25 Voltage waveform 104 of the output terminal 21 Output voltage waveform 105 of the detection circuit 1 Voltage waveform 106, 203 of the base (gate) of the transistor 4 Voltage waveform of the abnormal operation detection terminal 16 106 'Voltage waveform 201 at point A in FIG. Voltage waveform 202 of source (gate) Voltage waveform 203 at point B in FIG. 1 Output voltage waveform of inverter 12

Claims (2)

A level shift circuit of an amplifier circuit comprising: a lower circuit that receives a signal from an input terminal and drives a lower output transistor; and an upper circuit that receives a signal from the input terminal and drives an upper output transistor,
A bootstrap for supplying power to the upper circuit;
A detection circuit for detecting an abnormality in the upper circuit ;
First detection means for outputting a signal generated by converting the signal at the output terminal of the detection circuit into a current at the other end of the first resistor having one end connected to the ground of the lower circuit ;
Second detection means for outputting a signal generated by converting a signal at the output terminal of the amplifier circuit into a current at the other end of a second resistor having one end connected to the ground of the lower circuit ;
A logic circuit that outputs a logical product signal of the output signals of the first and second detection means,
A level shift circuit characterized in that erroneous detection of the detection circuit is prevented by using an output difference between the first and second detection means set by a resistance value difference between the first and second resistors . A level shift circuit of an amplifier circuit comprising: a lower circuit that receives a signal from an input terminal and drives a lower output transistor; and an upper circuit that receives a signal from the input terminal and drives an upper output transistor,
A bootstrap for supplying power to the upper circuit;
A detection circuit for detecting an abnormality in the upper circuit;
A first inverter having an input terminal connected to an output terminal of the detection circuit;
A first transistor connected to an output terminal of the first inverter and a base or a gate, connected to an output part of the bootstrap and an emitter or a source, and connected to a ground via a collector or a drain and a first resistor;
A second transistor having a collector or drain and a base or gate of the first transistor connected to each other and an emitter or source connected to the ground;
A second inverter connecting the collector or drain of the second transistor and an input terminal;
A third inverter connecting the output terminal and the input terminal of the amplifier circuit;
A third transistor connected to an output terminal of the third inverter and a base or gate, connected to an output part of the bootstrap and an emitter or source, and connected to a ground via a collector or drain and a first resistor;
A fourth transistor in which the collector or drain of the third transistor is connected to the base or gate, and the emitter or source is connected to the ground;
A cutoff circuit and an output terminal for connecting the collector or drain of the fourth transistor and the first input terminal, the output terminal of the second inverter and the second input terminal, and blocking the driving of the upper and lower circuits. A connected NAND gate,
A level shift circuit characterized in that erroneous detection of the detection circuit is prevented using a conduction time difference between the second and fourth transistors caused by a difference between resistance values set by the first and second resistors.

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