JPH06291640A - Level converting circuit - Google Patents

Abstract

PURPOSE:To convert a level at high speed by detecting the change of the level with a capacitor and applying a detection signal to a converting means in the state of clamping it at a certain level to enable operation with high sensitivity by using a means to convert it to a CMOS level. CONSTITUTION:A signal at an ECL level is outputted from an output terminal 10 of an ECL chip 1 and inputted to a capacitor 4. With this capacitor 4, the signal at the ECL level is prevented from being directly impressed to the CMOS gate of a CMOS chip 2. When the ECL signal is inputted to the capacitor 4, it is outputted to an inverter 5 as an AC signal detecting the change of the level. Concerning the inverter 5, the input side and the output side are short- circuited, and the level is clamped to high sensitivity so as to most provide the driving ability of the MOS transistor of an inverter 6. Since the signal clamped to the high-sensitivity level is inputted to the gate of the inverter 6, the level can be converted into CMOS logical level at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit suitable for converting between a CMOS logic level and another logic level in an input / output section of an integrated circuit device.

[0002]

2. Description of the Related Art As a circuit for converting between an ECL logic level and a CMOS logic level, a circuit as shown in FIG. 7 has been conventionally used. This level conversion circuit
It has a bipolar current switching circuit 11, a CMOS level conversion circuit 12, and a Bi CMOS driver 13,
The ECL level signal input to the bipolar current switching circuit 11 is amplified by the emitter follower circuit, received by the CMOS type current mirror circuit and converted to the CMOS level, and then the current driving capability is enhanced and output to the outside.

In the level conversion circuit shown in FIG. 8, a signal output from the bipolar current switching circuit 21 is converted into a CMOS level by a CMOS level conversion circuit 22 having a latch function and externally supplied via a Bi CMOS driver 23. A CMOS level signal is output to.

In any of the circuits, the ECL level signal input and the CMOS level signal to be converted have a direct current-corresponding relationship, and the conversion operation is stable. However, these circuits have a problem that the conversion speed is slow. The ECL level signals output from the bipolar current switching circuits 11 and 21 are directly input to the gates of the MOS transistors of the CMOS level conversion circuits 12 and 22. It is difficult to set the signal input to the gate of this MOS transistor to the highest level of sensitivity at which this MOS transistor exhibits its maximum driving capability, which causes a reduction in speed.

Generally, it is considered that the ECL level signal is level-shifted by using a diode or the like to be converted to a level preferable for the CMOS gate to exert its driving capability. However, the use of the diode naturally causes a delay in operating speed. Alternatively, it is conceivable to bring the signal level on the CMOS side closer to the ECL level. However, in this case, it is necessary to reset the power supply voltage on the CMOS side, two power supplies must be prepared, and there is a problem that wiring becomes complicated.

[0006]

As described above, the conventional level conversion circuit has a problem that the operation speed is slow.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a level conversion circuit capable of performing level conversion at high speed.

[0008]

The level conversion circuit of the present invention includes a capacitor which receives a first signal from the outside, detects a change in the first signal, and outputs a second signal, and the capacitor. The output second signal is input,
Clamping means for clamping at a predetermined level and outputting a third signal, and converting means for receiving the third signal output from the clamping means, converting it to a CMOS logic level and outputting a fourth signal. A conversion unit that operates so as to obtain the highest driving capability at the predetermined level; and a latch unit that receives the fourth signal output from the conversion unit and holds and outputs the fourth signal. It is characterized by having.

[0009]

The first signal is input to the capacitor, its change is detected and output as the second signal, and this second signal is input to the clamp means. By the clamping means,
The second signal is clamped to a predetermined level at which the converting means exerts the highest driving capability, and is input to the converting means as a third signal. As a result, the level conversion operation of the conversion means is performed at high speed. Although the level of the fourth signal output from the converting means is not stable in terms of direct current, it can be converted to a stable level by being latched and output by the latch means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a level conversion circuit according to the first embodiment of the present invention. EC with ECL circuit
The output side 10 of the L chip 1 is connected to the input side of a CMOS chip 2 having a CMOS circuit formed therein.

At the output of the ECL chip 1, a differential amplifier composed of resistors R1 and R2, npn-type bipolar transistors BT1 and BT2, and a constant current source IS1, and an output signal of this differential amplifier are externally output. An npn-type bipolar transistor BT3 and a constant current source IS2 which form an emitter follower circuit for outputting to

On the input side of the CMOS chip 2, the level converter according to this embodiment is formed. In this level converter, a capacitor 4 is connected between an output terminal of the ECL chip 1 and an internal input terminal 11 on the side of the CMOS chip 2, and a P-channel transistor P1 and an N-channel transistor N1 are provided on the output side of the capacitor 4. 2 and an inverter 6 composed of a P-channel transistor P2 and an N-channel transistor N2 are connected in two stages, and the output terminal 12 of the inverter 6 has an NA
A latch circuit 8 including ND circuits NA1 and NA2 is provided. Here, an inverter 7 that inverts the level of the output terminal 12 is connected between the output terminal 12 and one input terminal of the NAND circuit NA2. The output terminal 13 of the latch circuit 8 is connected to an internal circuit (not shown). The inverter 5 has an input terminal and an output terminal short-circuited.

From the output terminal 10 of the ECL chip 1, the ECL level (-0.8 to-) as shown in FIG.
A signal of −1.6 V) is output and input to the capacitor 4. The capacitor 4 prevents an ECL level signal from being directly applied to the CMOS gate of the CMOS chip 2. When the ECL signal is input to the capacitor 4, the ECL signal is output to the inverter 5 as an AC signal that detects a change in level. The input side and the output side of the inverter 5 are short-circuited as described above, and the M
The OS transistor is clamped to the level of the sensitivity with which the drive capability is most exerted. This clamp level is shown in Figure 2.
As shown in (b), generally, the power supply voltage VDD and the ground voltage Vss
It is located almost in the middle of. FIG. 3 shows the relationship between the input voltage Vin and the output voltage Vout of the inverter 5 and the clamp level C1. When the input terminal and the output terminal of the inverter 5 are not short-circuited, the input voltage Vin and the output voltage Vout
And have a relationship as indicated by line L1. The intersection of this line L1 and the straight line (Vin = Vout) is set to the clamp level C1.

The output clamped by the inverter 5 is input to the gate of the inverter 6. Here, the transistors P2 and N2 of the inverter 6 are
The transistors P1 and N1 have the same dimensions. By inputting a signal clamped to a level of high sensitivity to the gate of the inverter 6, the inverter 6
Allows high speed conversion to CMOS logic levels. Here, as shown in FIG. 2C, the case where the power supply voltage VDD is 3.3V is illustrated, but it may be another level such as 5V.

Here, the signal output from the capacitor 4 detects a change in the ECL level signal as described above and dynamically forms a high level or a low level, and forms a DC stable logic level. There is nothing to do. Therefore, the signal is transmitted to the internal logic circuit after the fluctuation of the signal is prevented by the latch circuit 8.

Conventionally, the ECL level is set to C as described above.
When converting to the MOS level, a stable DC logic level is determined and applied to the CMOS gate. On the other hand, in the present embodiment, the level is not fixed by direct current, and the inverter 5 is used to clamp near the logical threshold value at which the sensitivity of the MOS transistor is maximized. The converted signal to the inverter 6
By applying to the gate of, the level can be rapidly converted. Further, since the output from the inverter 6 is latched by the latch circuit 8, it is possible to transfer the output to the circuit in the subsequent stage while preventing the signal level from changing.

In the present embodiment, the ECL level signal is first received by the capacitor 4. However, it is possible to convert a signal having an arbitrary logic level to the CMOS level, not limited to the ECL level, and various signals can be converted. It can be used for various purposes. For example, the pseudo ECL level (2.9 to 3.
Even if a 7V) signal or a TTL level signal is input, it is possible to convert the signal to the CMOS level at a high speed in the same manner according to this embodiment.

Regarding the required capacity of the capacitor 4, it is generally considered desirable to have several pF in order to maintain the moment when the input ECL level signal is at high level or low level for a certain period of time. . Also,
Forming the capacitor 4 does not reduce the degree of integration. For example, it is possible to prevent an increase in the element area by, for example, forming it directly under the bonding pad connected to the input terminal 11 of the CMOS chip 2. Specifically, a MOS capacitor or a capacitance between two layers of polysilicon may be used.

FIG. 4 shows the configuration of the second embodiment of the present invention. In this embodiment, in the level conversion circuit included in the CMOS chip 2a of the first embodiment, the diodes 14a and 1 are provided between the output side of the capacitor 4 and the internal input terminal 11.
It is characterized in that a clamp element composed of 4b is provided.

In the first embodiment, as described above, not only ECL level signals but also signals having various logic levels can be input to the capacitor 4. However, if the amplitude of the input signal is too large, the level of the input terminal 11 becomes C
The range from the power supply voltage VDD to the ground voltage Vss of the MOS chip 2a may be exceeded. In such a case, by using the diodes 14a and 14b as in the second embodiment, it is possible to prevent the voltage range from VDD to Vss. Here, although the diodes 14a and 14b are provided between the input terminal 11 and the power supply voltage Vcc terminal and the ground voltage Vss terminal, the operation when the change in the output from the capacitor 4 is applied to the gate of the inverter 5 is There is no fear of a drop.

Here, the clamp means is not limited to the diode. For example, as shown in FIG. 9, it is possible to provide N-channel transistors N11 and N12 at the input terminal 11.

A third embodiment of the present invention will be described with reference to FIG. This embodiment is characterized in that an N-channel transistor N3 is connected between the source of the N-channel transistor N11 of the inverter 5 of the first embodiment and the ground voltage Vss terminal. This transistor N3
The voltage V1 is input to the gate of the.

As described above, the inverters 5 and 6 in the first embodiment are each composed of the transistor P.
The dimensions of 1 and N1, P2 and N2 are set to be the same. On the other hand, in the third embodiment, the transistors P1 and N1 of the inverter 15 and the transistors P2 and N2 of the inverter 6 are not set to have the same size. Instead, the inverter 15 is provided with a transistor N3 so that the clamp level is adjusted so that the sensitivity of the inverter 6 is maximized. This fine adjustment of the level can be easily performed by changing the conduction resistance by changing the voltage V1 applied to the gate of the transistor N3 from the outside. With this configuration, according to the third embodiment, it is possible to eliminate the dimensional restrictions of the transistors that form the inverters 15 and 16.

Next, FIG. 6 shows the configuration of a level adjusting circuit according to a fourth embodiment of the present invention. In this embodiment, the CMOS
It is characterized in that a P-channel transistor P3 and an N-channel transistor N4 are added to the inverter 16 in the chip 2c. The P-channel transistor P3 is connected between the source of the P-channel transistor P2 and the power supply voltage VDD terminal, and the P-channel transistor P3 is connected to the N-channel transistor N3.
4 is connected between the N-channel transistor N2 and the ground voltage Vss terminal. The voltage V2 is input to the gate of the P-channel transistor P3, and the voltage V3 is input to the gate of the N-channel transistor N4.

The fourth embodiment, like the third embodiment, is not restricted by the same size of the transistors forming the inverters 5 and 16. In the third embodiment, the clamp level of the inverter 15 is adjusted to the level where the sensitivity of the inverter 6 is maximized. On the other hand, the fourth
In the embodiment, the clamp level of the inverter 5 is fixed,
The transistors P3 and N4 are used for adjustment so that the operation threshold of the inverter 16 matches this level. By controlling the conduction resistance by changing the voltages V2 and V3 applied to the gates of the transistors P3 and N4, the inverter 1
It is possible to easily finely adjust the operation threshold value of 6 from the outside.

Although the first to fourth embodiments of the present invention have been described above, all of the ECLs output from the ECL circuit are described.
The level signal is received by the capacitor, the level change is detected, and the signal is converted into the CMOS level while being clamped to the level at which the operational sensitivity of the inverter is maximum. Therefore, the CMOS level conversion circuits 12 and 22 required in the conventional level conversion circuits shown in FIGS. 7 and 8 are unnecessary. Therefore, according to the embodiment, it is possible to configure with a smaller number of elements than the conventional one.

The above-mentioned embodiments are merely examples, and do not limit the present invention. For example, the circuit that latches the signal converted into the CMOS level signal is not limited to the NAND latch circuit as shown in the figure, and may be any circuit that can hold a predetermined logic level.

Various modifications can be made to the first to fourth embodiments. For example, the inverter 6 in the first embodiment shown in FIG. 1 may be replaced by a P-channel transistor P11 and an N-channel transistor N1 as shown in FIG.
Alternatively, the clocked inverter CI having 1 may be used. In this case, the clocked inverter CI is supplied with a low-level clock pulse / CK to operate as an inverter only when a signal is to be transmitted internally, and a high-level clock pulse / CK is supplied to a signal that should not be transmitted. Give CK. As a result, the clocked inverter CI becomes inactive, and it is possible to prevent unnecessary signals from being transmitted to the internal circuits and adversely affecting them.

[0030]

As described above, according to the level conversion circuit of the present invention, the change in the level of the signal input from the outside is detected by the capacitor, and the detected signal is CMOS.
Since the means for converting into a level is applied to the converting means while being clamped to a level at which it can operate with the highest sensitivity, it is possible to perform the level conversion at a high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a level of a signal input to the same level conversion circuit, a level at which the signal is clamped, and a level of a signal converted to a CMOS level and output.

FIG. 3 is a graph showing a clamp level of an inverter 5 in the same level conversion circuit.

FIG. 4 is a circuit diagram showing a configuration of a level conversion circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a level conversion circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a level conversion circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a conventional level conversion circuit.

FIG. 8 is a circuit diagram showing the configuration of another conventional level conversion circuit.

FIG. 9 is a circuit diagram showing a modification of the level conversion circuit according to the second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a modification of the level conversion circuit according to the first embodiment of the present invention.

[Explanation of symbols]

 1 ECL chip 2, 2a, 2b CMOS chip 4 capacitor 5, 6, 7, 15, 16 inverter 8 latch circuit 10 output terminal 11 input terminal 12, 13 output terminal 14a, 14b diode R1, R2 resistance BT1 to BT3 bipolar transistor IS1 , IS2 constant current source NA1, NA2 NAND circuit P1 to P3 P channel transistor N1 to N4 N channel transistor

Claims (7)

[Claims] 1. A first signal is input from the outside, and the first signal is input.
A capacitor for detecting a change in the signal of the second signal and outputting a second signal; a clamp means for receiving the second signal output from the capacitor, clamping the signal at a predetermined level, and outputting a third signal; Conversion means for inputting the third signal output from the means, converting the third signal to a CMOS logic level and outputting a fourth signal, and operating to obtain the highest driving capability in the vicinity of the predetermined level. A level conversion circuit comprising: a conversion unit; and a latch unit that receives the fourth signal output from the conversion unit and holds and outputs the fourth signal. 2. An input terminal for inputting a signal from the outside, a capacitor connected between the input terminal and a first node, a gate and a drain connected to the first node, and a source connected to the first node. A first conductivity type transistor connected to the first power supply voltage terminal; and a second conductivity type transistor having a gate and drain connected to the first node and a source connected to the second power supply voltage terminal. Clamp means having: a first conductivity type transistor having a gate connected to the first node, a source connected to a first power supply voltage terminal, and a drain connected to a second node; An inverter having a second conductivity type transistor connected to a first node, a source connected to a second power supply voltage terminal, and a drain connected to the second node. The level conversion circuit, wherein the potential of the first node clamped by the ramp means is set near a level at which the driving capability of the inverter is highest. 3. Any one between the first conductivity type transistor and the first power supply voltage terminal of the clamp means, and / or between the second conductivity type transistor and the second power supply voltage terminal. 3. The level conversion circuit according to claim 2, further comprising at least one transistor connected to the transistor, the potential of the first node clamped by the clamp means being adjusted by the conduction resistance of the transistor. . 4. Either between the first conductivity type transistor and the first power supply voltage terminal of the inverter, and / or between the second conductivity type transistor and the second power supply voltage terminal. 3. The level conversion circuit according to claim 2, further comprising at least one transistor connected to, wherein the operating threshold of the inverter is adjusted by the conduction resistance of the transistor. 5. The level conversion circuit according to claim 2, further comprising latch means for receiving and holding the potential of the second node. 6. Clamping means are provided between the first node and a first power supply voltage terminal and between the first node and a second power supply voltage terminal, respectively, and clamp means are provided between the first node and the first power supply voltage terminal. 6. The level conversion circuit according to claim 2, wherein the potential does not exceed the range between the first power supply voltage and the second power supply voltage. 7. The level conversion circuit according to claim 2, wherein the capacitor is provided below a region of a bonding pad connected to the input terminal.