JPH05315931A - Level shifting circuit - Google Patents

Level shifting circuit

Info

Publication number
JPH05315931A
JPH05315931A JP3296900A JP29690091A JPH05315931A JP H05315931 A JPH05315931 A JP H05315931A JP 3296900 A JP3296900 A JP 3296900A JP 29690091 A JP29690091 A JP 29690091A JP H05315931 A JPH05315931 A JP H05315931A
Authority
JP
Japan
Prior art keywords
circuit
level shifting
voltage source
vcc
shifting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3296900A
Other languages
Japanese (ja)
Inventor
Noriko Tsuda
典子 津田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3296900A priority Critical patent/JPH05315931A/en
Publication of JPH05315931A publication Critical patent/JPH05315931A/en
Pending legal-status Critical Current

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  • Direct Current Feeding And Distribution (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of a through current and to stabilize a circuit in a high voltage source system by providing a level shifting circuit with a gate circuit for fixing the potential of the level shifting circuit at the occurance of abnormality. CONSTITUTION:The gate circuit is constituted by adding a detection circuit 10 for monitoring a low voltage source VCC and detecting its abnormal rise and two transistors(TRs) QP1, QN1 for receiving an output from the circuit 10 by their gates to a convensional level shifting circuit. The n-channel TR QN1 is connected between ground and the output terminal T1 of the level shifting circuit, and if abnormality is detected in the VCC, it is turned on to fix the output terminal T1 to the ground. Thereby an output terminal 5 is initialized to a high impedance state. On the other hand, the sources of two p-channel TRs Q1, Q3 in the level shifting circuit are connected to a high voltage source VDD through the p-channel TR QP1, and when the VCC is abnormal, the QP1 is turned off, so that the level shifting circuit is disconnected from the VDD and a current flow disappears.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はレベルシフト回路に関す
る。
BACKGROUND OF THE INVENTION The present invention relates to a level shift circuit.

【0002】[0002]

【従来の技術】図3は従来のレベルシフト回路を用いた
ドライバ回路の一例を示す回路図である。入力端Tは低
電圧源(以後VCCと記す)をソースとするインバータ
2の入力に接続され、さらにこのインバータ2の出力が
同じくVCCをソースとするインバータ3に入力されて
いる。これら2つのインバータ2,3の出力がレベルシ
フト回路を構成する2つのNチャネル型絶縁ゲート電界
効果トランジスタ(以下、Nチャネルトランジスタとい
う)Q2,Q4のゲートに接続されている。レベルシフ
ト回路は高電圧源(以後VDDと記す)とグランド間に
Pチャネル型絶縁ゲート電界効果トランジスタ(以下、
Pチャネルトランジスタという)Q1とNチャネルトラ
ンジスタQ2、PチャネルトランジスタQ3とNチャネ
ルトランジスタQ4が各々直列に接続される構成となっ
ており、PチャネルトランジスタQ1のゲートにはPチ
ャネルトランジスタQ3とNチャネルトランジスタQ4
の接続点T1が接続され、一方Pチャネルトランジスタ
Q3のゲートにはPチャネルトランジスタQ1とNチャ
ネルトランジスタQ2の接続点T2が接続されている。
2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a driver circuit using a conventional level shift circuit. The input terminal T is connected to the input of an inverter 2 whose source is a low voltage source (hereinafter referred to as VCC), and the output of the inverter 2 is also input to an inverter 3 whose source is VCC. The outputs of these two inverters 2 and 3 are connected to the gates of two N-channel insulated gate field effect transistors (hereinafter referred to as N-channel transistors) Q2 and Q4 that form a level shift circuit. The level shift circuit is a P-channel insulated gate field effect transistor (hereinafter, referred to as “VDD”) between a high voltage source (hereinafter referred to as VDD) and the ground.
A P-channel transistor Q1 and an N-channel transistor Q2, and a P-channel transistor Q3 and an N-channel transistor Q4 are connected in series. The P-channel transistor Q1 has a gate connected to the P-channel transistor Q3 and the N-channel transistor Q4. Q4
Of the P-channel transistor Q3 is connected to the connection point T1 of the P-channel transistor Q1 and the N-channel transistor Q2.

【0003】レベルシフト回路の出力T1はVDDをソ
ースとするインバータ4を経て、そのドレインが出力端
子5に接続されたPチャネルトランジスタQ5のゲート
に入力される。ここでレベルシフト回路以降のトランジ
スタQ1〜Q5、インバータ4には高電圧が印加される
ため高耐圧設計となっている。
The output T1 of the level shift circuit passes through an inverter 4 whose source is VDD, and its drain is input to the gate of a P-channel transistor Q5 connected to an output terminal 5. Here, a high voltage is applied to the transistors Q1 to Q5 and the inverter 4 after the level shift circuit, so that the design is high withstand voltage.

【0004】動作としては入力端Tに入力されたVCC
レベルの信号がレベルシフト回路によってVDDレベル
の信号に変換され、ICの出力端子5には入力端Tが0
のときハイ・インピーダンス、Tが1すなわちVCCの
とき1すなわちVDDが出力される。
In operation, the VCC input to the input terminal T
The level signal is converted into a VDD level signal by the level shift circuit, and the input terminal T is 0 at the output terminal 5 of the IC.
Is output at high impedance, and when T is 1 or VCC, 1 or VDD is output.

【0005】図5の波形図に示すようにVCCが異常に
上昇すると(時刻to )、VCC系のトランジスタがブ
レークダウンし、T1の電位は不定となりT11レベル
となる(図5(c))。出力端子5はこの信号レベルに
よりオンまたはオフする(図5(d))。
As shown in the waveform diagram of FIG. 5, when VCC rises abnormally (time t o ), the VCC transistor breaks down and the potential of T1 becomes indefinite and becomes T11 level (FIG. 5 (c)). .. The output terminal 5 is turned on or off according to this signal level (FIG. 5 (d)).

【0006】[0006]

【発明が解決しようとする課題】一般に自動車内で使用
される2電源を有するICには、バッテリーからの高電
圧源と、それを3端子レギュレータ等で降圧した低電圧
源が用いられる。
Generally, a high voltage source from a battery and a low voltage source obtained by stepping down the high voltage source from a battery are used for an IC having two power sources used in an automobile.

【0007】3端子レギュレータの異常により低電圧源
が上昇し低電圧源系のトランジスタの耐圧を越えると、
トランジスタはブレークダウンしてその出力は不足とな
る。
When the low voltage source rises due to the abnormality of the three-terminal regulator and the withstand voltage of the transistor of the low voltage source system is exceeded,
The transistor breaks down and its output becomes insufficient.

【0008】レベルシフト回路の入力も不足となるため
貫通電流が発生し、レベルシフト回路の出力、さらにI
Cの出力端子も不定となってシステム全体に異常を引き
起こすという問題点があった。
Since the input of the level shift circuit also becomes insufficient, a shoot-through current is generated, and the output of the level shift circuit and I
There is also a problem that the output terminal of C becomes undefined and causes an abnormality in the entire system.

【0009】[0009]

【課題を解決するための手段】本発明のレベルシフト回
路は、低電圧源を監視し、異常な上昇を検知する検知回
路と、その信号を受けて異常発生時にレベルシフト回路
の動作を停止し電位を固定するゲート回路を備えてい
る。
SUMMARY OF THE INVENTION A level shift circuit of the present invention monitors a low voltage source and detects an abnormal rise, and receives the signal to stop the operation of the level shift circuit when an abnormality occurs. A gate circuit for fixing the electric potential is provided.

【0010】[0010]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の第1の実施例の回路図である。図3
の従来のレベルシフト回路に対して低電圧源(VCC)
を監視してその異常上昇を検知する検知回路10と、そ
の出力をゲートに受ける2つのトランジスタQP1,Q
N1が追加してゲート回路を構成する。Nチャネルトラ
ンジスタQN1はグランドとレベルシフト回路の出力端
T1との間に接続されVCCに異常が検出された場合に
オンし、出力端T1をグランドに固定する。これにより
出力端子5はハイ・インピーダンス状態に初期化され
る。一方レベルシフト回路の2つのPチャネルトランジ
スタQ1,Q3のソースはPチャネルトランジスタQP
1を介してVDDと接続されVCCが異常時にはQP1
がオフすることによってレベルシフト回路はVDDから
切り離され電流が流れなくなる。
The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the first embodiment of the present invention. Figure 3
Low voltage source (VCC) for the conventional level shift circuit of
Of the detection circuit 10 that monitors the voltage and detects an abnormal rise thereof, and two transistors QP1 and Q that receive the output at their gates.
N1 is added to form a gate circuit. The N-channel transistor QN1 is connected between the ground and the output terminal T1 of the level shift circuit, and is turned on when an abnormality is detected in VCC, and the output terminal T1 is fixed to the ground. As a result, the output terminal 5 is initialized to the high impedance state. On the other hand, the sources of the two P-channel transistors Q1 and Q3 of the level shift circuit are P-channel transistors QP.
QP1 when connected to VDD via 1 and VCC is abnormal
Is turned off, the level shift circuit is disconnected from VDD, and no current flows.

【0011】以上、記述した通り貫通電流を防ぎ、出力
を初期化、固定できる。
As described above, it is possible to prevent the shoot-through current and initialize and fix the output.

【0012】図2は本発明の第2の実施例を示す回路図
である。
FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

【0013】図3に対してNチャネルトランジスタQN
1,QN2が追加されてゲート回路を構成する。Nチャ
ネルトランジスタQN2はNチャネルトランジスタQ2
のゲートに接続されVCC以上検知時にオンして、QN
2をオフ状態にし貫通電流を防ぐ。一方Nチャネルトラ
ンジスタQN1は図1の第1の実施例と同様である。以
上のようにして図1と同様の効果を得られる。
In contrast to FIG. 3, N-channel transistor QN
1, QN2 are added to form a gate circuit. The N-channel transistor QN2 is the N-channel transistor Q2
It is connected to the gate of the
2 is turned off to prevent shoot-through current. On the other hand, the N-channel transistor QN1 is similar to that of the first embodiment shown in FIG. As described above, the same effect as that of FIG. 1 can be obtained.

【0014】尚VCC異常検知回路は図4に一例を示す
ようにコンパレータ6を用いて容易に構成できる。VD
Dとグランド間に直列に接続された2つの抵抗R1,R
2による分圧を利用して、コンパレータの(−)側入力
にはVCC定格以上の検知したいレベルを入力しておけ
ば良い。(+)側入力V5にVCC又はそれに応じた電
圧が入力される。
The VCC abnormality detecting circuit can be easily constructed by using the comparator 6 as shown in FIG. VD
Two resistors R1 and R connected in series between D and ground
It is sufficient to input the level to be detected above the VCC rating to the (-) side input of the comparator by using the voltage division by 2. VCC or a voltage corresponding thereto is input to the (+) side input V5.

【0015】先に従来技術の不都合を説明した図5を用
いて、本発明のレベルシフト回路の動作を説明する。
The operation of the level shift circuit according to the present invention will be described with reference to FIG.

【0016】時刻to においてVCCが異常検知レベル
を越すと(図5(a))、検知回路10の出力信号が1
すなわちVDD(図5(b))になり、それによりT1
は0に固定され(図5(c))、出力端子5はハイ・イ
ンピーダンス(図5(d))となる。
When VCC exceeds the abnormality detection level at time t o (FIG. 5A), the output signal of the detection circuit 10 becomes 1
That is, it becomes VDD (FIG. 5 (b)), so that T1
Is fixed to 0 (FIG. 5 (c)), and the output terminal 5 has a high impedance (FIG. 5 (d)).

【0017】[0017]

【発明の効果】以上説明した様に本発明は電源系統の故
障などによる低電圧源の異常上昇を検知し、その場合に
レベルシフト回路の電位を固定するゲート回路を設けた
ので、貫通電流を防ぎ、高電圧源系の回路を安定化でき
るという効果を有している。
As described above, according to the present invention, a gate circuit for detecting an abnormal rise of a low voltage source due to a failure of the power supply system and fixing the potential of the level shift circuit in that case is provided. This has the effect of preventing and stabilizing the circuit of the high voltage source system.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す回路図。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

【図2】本発明は第2の実施例を示す回路図。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

【図3】従来技術を示す回路図。FIG. 3 is a circuit diagram showing a conventional technique.

【図4】図1および図2で示した低電圧源異常検出回路
の一例の回路図。
FIG. 4 is a circuit diagram of an example of the low voltage source abnormality detection circuit shown in FIGS. 1 and 2.

【図5】従来技術および本発明のレベルシフト回路の動
作を示す波形図。
FIG. 5 is a waveform diagram showing the operation of the level shift circuit according to the related art and the present invention.

【符号の説明】[Explanation of symbols]

2,3,4 インバータ 5 出力端子 6 コンパレータ 10 低電圧源異常検出力回路 Q1,Q3,Q5,QP1 Pチャネルトランジスタ Q2,Q4,QN1,QN2 Nチャネルトランジス
タ T 入力端 T1,T2 レベルシフト回路の出力端 VDD 高電圧源 VCC 低電圧源
2, 3, 4 Inverter 5 Output terminal 6 Comparator 10 Low voltage source abnormality detection circuit Q1, Q3, Q5, QP1 P-channel transistor Q2, Q4, QN1, QN2 N-channel transistor T input terminal T1, T2 Output of level shift circuit Edge VDD High voltage source VCC Low voltage source

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 低電圧源系の回路を高電圧源の回路に変
換するレベルシフト回路において、前記低電圧源の定格
以上の上昇を検知する検知回路と、前記検知回路の信号
を受けてレベルシフト回路の電位を固定するゲート回路
とを有することを特徴とするレベルシフト回路。
1. A level shift circuit for converting a circuit of a low voltage source system into a circuit of a high voltage source, a detection circuit for detecting a rise of the low voltage source above a rating, and a level for receiving a signal from the detection circuit. A level shift circuit having a gate circuit for fixing the potential of the shift circuit.
JP3296900A 1991-11-13 1991-11-13 Level shifting circuit Pending JPH05315931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3296900A JPH05315931A (en) 1991-11-13 1991-11-13 Level shifting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3296900A JPH05315931A (en) 1991-11-13 1991-11-13 Level shifting circuit

Publications (1)

Publication Number Publication Date
JPH05315931A true JPH05315931A (en) 1993-11-26

Family

ID=17839616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3296900A Pending JPH05315931A (en) 1991-11-13 1991-11-13 Level shifting circuit

Country Status (1)

Country Link
JP (1) JPH05315931A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107832A (en) * 1999-02-05 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Input/output circuit
US6545521B2 (en) * 2001-06-29 2003-04-08 International Business Machines Corporation Low skew, power sequence independent CMOS receiver device
JP2004048377A (en) * 2002-07-11 2004-02-12 Renesas Technology Corp Level shifter circuit
JP2005323195A (en) * 2004-05-10 2005-11-17 Texas Instr Japan Ltd Level shift circuit
US6985022B2 (en) 2001-08-31 2006-01-10 Renesas Technology Corp. Semiconductor device
US7005908B2 (en) * 2003-01-13 2006-02-28 Samsung Electronics Co., Ltd. Voltage level shift circuit and power supply detection circuit
JP2007116388A (en) * 2005-10-20 2007-05-10 Nec Electronics Corp Semiconductor device
JP2008096473A (en) * 2006-10-06 2008-04-24 Hitachi Displays Ltd Display device
SG143089A1 (en) * 2006-11-22 2008-06-27 Hui Feng Lin Structure of a cap of a chopstick
JP2009081805A (en) * 2007-09-27 2009-04-16 Oki Semiconductor Co Ltd Level shifter circuit
US7759976B2 (en) 2006-08-24 2010-07-20 Fujitsu Semiconductor Limited Level shift circuit

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107832A (en) * 1999-02-05 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Input/output circuit
US6545521B2 (en) * 2001-06-29 2003-04-08 International Business Machines Corporation Low skew, power sequence independent CMOS receiver device
US7375574B2 (en) 2001-08-31 2008-05-20 Renesas Technology Corporation Semiconductor device
US6985022B2 (en) 2001-08-31 2006-01-10 Renesas Technology Corp. Semiconductor device
JP2004048377A (en) * 2002-07-11 2004-02-12 Renesas Technology Corp Level shifter circuit
US7005908B2 (en) * 2003-01-13 2006-02-28 Samsung Electronics Co., Ltd. Voltage level shift circuit and power supply detection circuit
JP2005323195A (en) * 2004-05-10 2005-11-17 Texas Instr Japan Ltd Level shift circuit
JP2007116388A (en) * 2005-10-20 2007-05-10 Nec Electronics Corp Semiconductor device
JP4658770B2 (en) * 2005-10-20 2011-03-23 ルネサスエレクトロニクス株式会社 Semiconductor device
US7759976B2 (en) 2006-08-24 2010-07-20 Fujitsu Semiconductor Limited Level shift circuit
JP2008096473A (en) * 2006-10-06 2008-04-24 Hitachi Displays Ltd Display device
SG143089A1 (en) * 2006-11-22 2008-06-27 Hui Feng Lin Structure of a cap of a chopstick
JP2009081805A (en) * 2007-09-27 2009-04-16 Oki Semiconductor Co Ltd Level shifter circuit

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