JP3186994B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a television receiver,
The present invention relates to an image display device such as a monitor and a projection tube.

[0002]

2. Description of the Related Art As an image display device, for example, in recent television receivers, a large screen and high image quality are required to be powerful and realistic. On the other hand, in order to increase the power and sense of realism as video information, a lot of wide-screen movie-size wide screen information having no video information at the top and bottom of the screen (that is, having upper and lower blanks) has been created.

Under these circumstances, recently, the number of scanning lines has been increased to about twice that of the current NTSC system, the frequency band has been widened, the resolution has been increased, and the aspect ratio of the displayed image has been reduced. For example, it is wider than the current 4: 3,
A 16: 9 television system has been proposed, and based on this proposal, a television receiver having a horizontally long display has been put to practical use.

Further, as a television receiver having such a horizontally long display having an aspect ratio of a displayed image of 16: 9, an existing television signal having an aspect ratio of 4: 3 (hereinafter referred to as a standard television signal) is used. A television receiver having a function of displaying an image obtained from a television signal has also been proposed.

However, a television receiver having such a function receives a current television broadcast and has an aspect ratio of 4: 4 as shown in FIG.
When an image obtained from the standard television signal No. 3 is displayed on the entire screen of a horizontally long display having an aspect ratio of 16: 9, there is a problem that the image is distorted as shown in FIG. 7B. That is, in this case, since the aspect ratio of the image obtained from the standard television signal is 4: 3 = 12: 9, the aspect ratio of this image is 16:
When the image is displayed on a horizontally long display of No. 9, the displayed image is expanded 16/16 = 4/3 times in the horizontal direction.

Therefore, conventionally, the deflection current is controlled so that only a part of the screen of the display is scanned with the electron beam, and an image having an aspect ratio of 4: 3 is displayed on the part, thereby obtaining the image shown in FIG. As shown in c), an image without distortion was obtained. As such a conventional technique, for example, JP-A-61-206381 is cited.

[0007] Recently, even in a television receiver having a normal display having a 4: 3 aspect ratio of an image to be displayed, the number of scanning lines of a standard television signal is reduced to about 2 in the current NTSC system. In some cases, the resolution is doubled to achieve higher resolution.

[0008]

As described above, conventionally, a horizontally long display having an aspect ratio of 16: 9, which has a function of displaying an image obtained from a standard television signal having an aspect ratio of 4: 3. When a television receiver displays an image obtained from a standard television signal having an aspect ratio of 4: 3, the television receiver controls the deflection current and controls only a part of the screen of the display by an electron beam. , And an image is displayed on that portion, thereby obtaining an image without distortion.

In a television receiver having a normal display having an aspect ratio of 4: 3, the number of scanning lines of a standard television signal is approximately twice as large as that of the current NTSC system to achieve higher resolution. there were.

In the former television receiver, since only a part of the screen of the display is scanned by the electron beam, only an image obtained from a standard television signal having an aspect ratio of 4: 3 is displayed. When,
There is a problem in that only the scanned portion of the phosphor on the screen of the display deteriorates faster than the unscanned portion. Another problem is that the configuration of a circuit for controlling the deflection current becomes complicated.

On the other hand, in the latter television receiver, there is no problem in the case where the current television broadcast is received and an image is displayed, but the time base such as a signal reproduced from a video tape recorder or the like is not problematic. When a television signal including fluctuation (jitter) is input and an image is displayed, there is a problem that the image quality is deteriorated because the time-axis fluctuation removing ability is low. In addition, when a new time axis correction circuit is provided to solve the problem, there is a problem that the circuit scale becomes large.

The present invention has been made to solve the latter problem among the above-mentioned problems of the prior art. Therefore, an object of the present invention is to provide a display having a display,
As an image display device for displaying the number of scanning lines of a power television signal by multiplying the number of scanning lines by N (N is an integer of 2 or more), a television signal including a time axis variation such as a signal reproduced from a video tape recorder or the like It is an object of the present invention to provide an image display device which can display an image without deteriorating the image quality even when the image is displayed by inputting an image.

[0013]

In order to achieve the above-mentioned object, the present invention provides a display for displaying an input television signal.
In an image display device having a spray,

A unit which outputs a clock having a high oscillation cycle stability
First oscillating means (124) for oscillating and outputting as a force;
The display according to the oscillation output of the first oscillation means.
Horizontal drive pulse that generates a horizontal drive pulse to drive the
Loose generating means (109) and the input television
Oscillates depending on the horizontal synchronization signal in synchronization with the
Second oscillating means (107) and an input television signal
And the number of scanning lines of the input television signal is set to N.
(Where N is 2 or an integer exceeding 2)
N-speed means (105);

The television signal input to the N-times speed means
When writing at the time of capture,
Oscillates in a manner synchronized with the horizontal synchronization signal of the signal
The input television signal is an oscillation output from the second oscillation means.
And the N-times speeded television from the N-times speed means.
When reading out the version signal, the horizontal drive
Synchronized with the output of the dynamic pulse generation means (109),
A clock having a high oscillation cycle stability from the first oscillation means.
Using the clock reads the television signal N-times speed, the
The oscillation output of the first oscillation means has a high oscillation cycle stability.
Clock, and the oscillation output of the second oscillation means
The water is synchronized with the horizontal synchronizing signal of the power television signal.
Since the oscillation output depends on the flat synchronization signal,
In the television signal output from the double speed means,
Time axis fluctuations that had been had before the speed conversion were removed
The writing / reading means (16, 123, 1
25, 114), and

Time axis variation included in input television signal
N-speed television signal from which the
Displayed on the screen .

[0017]

The N-times speed means has a storage unit therein, and writes a signal obtained from an input television signal into the storage unit in synchronization with an oscillation output from the second oscillation means. Then, the written signal is read out from the storage section in synchronization with the oscillation output from the first oscillating means, so that the number of scanning lines of the television signal is output N times.

Thus, when the television signal is read from the storage section in the N-times speed means, the television signal is read in synchronization with the very stable oscillation output from the first oscillation means. Can not only perform double speed conversion but also perform time axis correction of signals.

Therefore, a signal containing a time axis fluctuation reproduced from a video tape recorder or the like is transmitted to the input television receiver.
Even if it is input as a TV signal , the time axis fluctuation is sufficiently removed and the double-speed converted TV
Signal can be displayed on the display, and the circuit scale does not increase.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described. Before that, for convenience of explanation, a circuit example which is useful for understanding the embodiments of the present invention will be described. FIG. 3 is a block diagram showing an example of an image display device useful for understanding the embodiment of the present invention.

In FIG. 3, reference numeral 101 denotes a standard television signal having an aspect ratio of 4: 3, 102 denotes an analog / digital (hereinafter, referred to as A / D) converter, 103
Is a motion-adaptive luminance signal / color signal (hereinafter, referred to as Y / C) separation circuit, 104 is a motion-adaptive scanning line interpolation circuit,
105 is a double speed conversion circuit.

The double speed conversion circuit 105 is composed of line memories 105a and 105b and a switching circuit 105c, receives a signal from the motion adaptive scanning line interpolation circuit 104, doubles the frequency and outputs the signal. The horizontal synchronizing signal from the standard television signal 101 is 106 (hereinafter, the frequency of this signal, that is,. The horizontal frequency and f _H) sync separator for separating a 107 is a clock generation circuit.

The clock generation circuit 107 is composed of a phase locked loop (hereinafter, referred to as PLL) circuit including a phase comparator 107a, a low-pass filter 107b, a voltage controlled oscillation circuit 107c, and a counter 107d. Generates a clock synchronized with the horizontal synchronization signal.

Further, the crystal oscillator circuit 108, 109 divides the oscillation output from the crystal oscillator circuit 108, a horizontal driving pulse generating circuit for generating a horizontal drive pulse having a frequency of 2f _H, 110 is a crystal oscillator circuit 108 A timing generation circuit for inputting an oscillation output from the oscilloscope and a horizontal drive pulse from the horizontal drive pulse generation circuit 109 to generate various signals synchronized with the horizontal drive pulse from the oscillation output, 111 is a gate circuit, and 112 is a gate circuit 111 A control signal to be controlled.

Reference numeral 113 denotes a clock for giving a read timing in the compression circuit 117 described later, reference numeral 114 denotes a read reset signal (RR) indicating a reading start position in the compression circuit 117 described later, and reference numeral 115 denotes a gate circuit 119 to be described later. And a decoder 116 for generating a write reset signal (WR) indicating a write start position in the compression circuit 117 described later.
Reference numeral 7 denotes a compression circuit which has a buffer memory for storing signals and compresses the signal from the double-speed conversion circuit 105 in the time direction.

Reference numeral 118 denotes a clock having a frequency of 8f _SC (f _SC is a color subcarrier frequency) which is one of the outputs of the clock generation circuit 107, 119 denotes a gate circuit, and 120 denotes a digital / analog (hereinafter D / A and D / A). Converter), 12
Reference numeral 1 denotes a horizontally long display having an aspect ratio of a displayed image of 16: 9.

The above is the configuration of this circuit example. Next, the operation of this circuit example will be described. FIG. 4 is a waveform chart showing the waveform of the main part signal in FIG.

The input standard television signal 101 having an aspect ratio of 4: 3 is separated by a sync separation circuit 106 into a horizontal sync signal as shown in FIG. 107 is input.

The input horizontal synchronizing signal is supplied to the phase comparator 1
In 07a, the clock and the phase comparison from the counter 107d having the same frequency as the frequency f _H of the horizontal synchronizing signal. The comparison result is the low-pass filter 1
07b to the voltage controlled oscillation circuit 107c,
Controlling the oscillation frequency, the voltage controlled oscillation circuit 107c, as shown in FIG. 4 (e), synchronized with the horizontal synchronizing signal corresponds to 1820 times the frequency f _H of the horizontal synchronizing signal 8
A clock 118 having a frequency of f _SC is generated.

The clock 118 having the frequency of 8f _SC
Is input to the compression circuit 117 as a write clock and to the counter 107d. Counter 1
The clock 118 input to the counter 107 d
is 910 divided by d, is input to the switching circuit 105c of double speed conversion circuit 105 as a clock having a frequency of 2f _H, is circumferentially 1820 minutes, the phase comparison decoder 116 and described above as a clock having a frequency f _H Vessel 1
07a.

At the decoder 116, the input f _H
Is decoded and sent to the compression circuit 117 as a write reset signal (WR) having a vertical period as shown in FIG.

The standard television signal 101 has A
The signal is converted into a digital signal by the / D converter 102 as shown in FIG. 4B, and is input to the motion adaptive scanning line interpolation circuit 104 via the motion adaptive Y / C separation circuit 103.
In FIG. 4B, the number in parentheses is the number of data in the digital signal, and the same applies hereinafter.

The motion-adaptive scanning line interpolation circuit 104 creates an actual signal and an interpolation signal from the input signal. The created real signal and interpolation signal are input to the double speed conversion circuit 105, where the frequency is doubled, and alternately output every half horizontal cycle as shown in FIG. 4C. You. In this way, a signal of high image quality is output from the double speed conversion circuit 105. In FIG. 4C, R is a real signal, I is an interpolation signal, and so on.

FIG. 4 output from the double speed conversion circuit 105
The signal shown in (f) is input to the compression circuit 117 having a buffer memory. In the compression circuit 117, the write reset signal (W
R), the buffer memory is reset, and from that point, 8f
_The input signal from the double-speed conversion circuit 105 is written to the buffer memory in synchronization with the write clock 118 having the _SC frequency.

The oscillation output from the crystal oscillation circuit 108 is (32/3) f, as shown in FIG.
_It has an _SC frequency and is input to the horizontal drive pulse generation circuit 109, the timing generation circuit 110, and the gate circuit 111, respectively.

The horizontal drive pulse generation circuit 109 divides the frequency of the input oscillation output, generates a horizontal drive pulse as shown in FIG. 4 (n), and outputs it to the timing generation circuit 110 and the display 121, respectively. .

The timing generation circuit 110 generates a read reset signal (RR) 114 having a vertical period as shown in FIG. 4G based on the input oscillation output from the crystal oscillation circuit 108 and the horizontal drive pulse. , To the compression circuit 117.

Here, the reset at the time of reading of the buffer memory in the compression circuit 117 is performed by the read reset signal (RR) 114 shown in FIG.
This is performed in the same vertical cycle as the write reset signal (WR) shown in (d), but the phase is shifted by 水平 horizontal cycle. This is to prevent the writing and reading of signals to and from the buffer memory from competing with each other.

In the timing generation circuit 110, the oscillation output from the crystal oscillation circuit
FIG. 4 (h) synchronized with a horizontal drive pulse having a frequency of _H
A control signal 112 as shown in FIG.
Enter 1 The control signal 112 is supplied to the compression circuit 117
Is a signal for designating a reading period of the buffer memory in FIG.

The gate circuit 111 calculates the logical product of the input oscillation output from the crystal oscillation circuit 108 and the control signal 112 to obtain the read clock 1 as shown in FIG.
13 is input to the compression circuit 117.

Accordingly, when signals (data) are read from the buffer memory in accordance with the read clock 113 in the compression circuit 117, the signals are read separately as shown in FIG. In addition, in FIG.
A is a video period portion, B is a black level period portion, and the rest is a non-reading period.

On the other hand, in the timing generation circuit 110, a control as shown in FIG. 4 (l) having the same timing as the above-mentioned non-reading period, synchronized with the horizontal drive pulse, is performed from the input oscillation output from the crystal oscillation circuit 108. A signal 115 is created and input to the gate circuit 119.

The gate circuit 119 receives the signal output from the compression circuit 117, and, based on the control signal 115,
As shown in FIG. 4 (m), a frame signal, that is, a signal having another predetermined level (hatched portion) is added and output only during the non-reading period.

The signal output from the gate circuit 119 is
After that, the signal is converted into an analog signal by the D / A converter 120 and input to the display 121. And
The display 121 displays the signal input from the D / A converter 120 based on the previously input horizontal drive pulse.

As described above, in the present circuit example, the write clock 118 having a frequency of 8 f _SC is used for writing a signal to the buffer memory in the compression circuit 117, and the signal is read from the buffer memory. , (32/3) read clock 1 having a frequency of _SC
13, the read frequency (32/3) f _SC in the buffer memory is 4/3 of the write frequency 8f _SC .
Therefore, the signal is compressed by the compression circuit 117 by a factor of 3/4 in the time direction.

Therefore, when the compressed signal is displayed on the display 121, the signal is enlarged by 4/3 times by the display 121, so that the distortion of the display 121 shown in FIG. No images can be displayed. However, in FIG. 7 (c), the difference from the prior art is that, in the present circuit example, an image obtained by the above-described frame signal, that is, a frame is displayed at both ends of the screen, and this portion is also sufficiently scanned by the electron beam. That is the point.

In this circuit example, the compression circuit 11
To read the signal from the buffer memory in step 7,
Since the very stable read clock 113 obtained from the oscillation output from the crystal oscillation circuit 108 is used, the compression circuit 117 can perform not only the above-described signal compression but also the time axis correction of the signal. Therefore, even when a signal including time axis fluctuation reproduced from a video tape recorder or the like is input as the standard television signal 101, the time axis fluctuation is sufficiently removed and the display 1
21 can be displayed.

In this circuit example, the compression circuit 11
7 when reading out the signal from the buffer memory in the video period portion and the black level period portion by separately reading the signal so that the video period portion is displayed at the center of the screen of the display 121. However, since the black level period can be read out so as to be included in the horizontal retrace period, the black level can be reproduced correctly.

In this circuit example, the read clock 113 used for reading signals is obtained from the oscillation output from the crystal oscillation circuit 108. However, even if it is not obtained from the oscillation output from the crystal oscillation circuit 108, for example, A signal synchronized with the color burst signal included in the standard television signal 101 may be generated by the PLL circuit, and the signal may be obtained from the generated signal.

Further, in the present circuit example, the frame signal is added by digital processing at the subsequent stage of the compression circuit 117. However, the frame signal is switched to a predetermined DC level by analog processing at the subsequent stage of the D / A converter 120. May be added.

FIG. 5 is a block diagram showing another example of an image display device useful for understanding the embodiment of the present invention, and FIG.
FIG. 4 is a waveform chart showing a main part signal waveform in FIG. 5, reference numeral 122 denotes a frequency dividing circuit, 123 denotes a write clock output from the frequency dividing circuit 122, and other components that are the same as those in FIG. 3 are denoted by the same reference numerals.

In this circuit example, the compression operation of the signal performed by the compression circuit 117 is performed by the double-speed conversion circuit 105 together with the double-speed conversion operation.
There is a feature in that 17 is deleted.

The operation of this circuit example is basically similar to that of FIG.
Since the operation is the same as that of the circuit example, only the different parts will be mainly described. In the frequency dividing circuit 122, the clock generating circuit 1
The clock having the frequency of 8f _SC output from the
Divide and write clock 123 with frequency of 4f _SC
Is output to the double speed conversion circuit 105. Also, in the decoder 116, the frequency f
A clock having a frequency of _H is input, decoded, and output to the double speed conversion circuit 105 as a write reset signal (WR) of a vertical cycle.

Next, the double speed conversion circuit 105 receives the actual signal and the interpolation signal generated by the motion adaptive scanning line interpolation circuit 104 and writes them into the line memories 105a and 105b. At that time, each line memory 105a, 105
b respectively correspond to FIG. 6 input from the decoder 116.
(A) is reset by a write reset signal (WR) having a vertical cycle as shown in FIG.
6B, the real signal (FIG. 6C) from the motion adaptive scanning line interpolation circuit 104 and the interpolation signal are synchronized with the write clock 123 having a frequency of 4f _SC as shown in FIG. Is written.

Then, each of the line memories 105a, 105
b is reset by a read reset signal (RR) 114 of a vertical cycle inputted from the timing generation circuit 110, and from that point on, the read clock 11 shown in FIG.
3 and are read out in synchronization with 3.

As described above, each line memory 105a, 1
When the signal is read from the signal line 05b in accordance with the read clock 113, the signal is read separately in the video period portion and the black level period portion as described in the circuit example of FIG. The signal is read so as to be included in the period, and is output as a signal as shown in FIG.

As described above, in the double speed conversion circuit 105, the signal compression operation is performed together with the double speed conversion operation. According to this circuit example, the signal is compressed by a factor of 3/4 in the time direction by the above-described signal compression operation in the double speed conversion circuit 105, as in the circuit example of FIG. And
When the compressed signal is displayed on the display 121, the signal is enlarged to 4/3 times by the display 121, so that an image without distortion can be displayed on the screen of the display 121.

Also in this circuit example, when reading the signals from the line memories 105a and 105b in the double speed conversion circuit 105, a very stable read clock 113 obtained from the oscillation output from the crystal oscillation circuit 108 is used.
Therefore, the double-speed conversion circuit 105 can perform double-speed conversion and signal compression, and can also perform time-base correction of the signal. Further, in the present circuit example, since the compression circuit is deleted, the circuit configuration is simplified as compared with the circuit example of FIG.

In each of the above circuit examples, a television receiver having a horizontally long display having an aspect ratio of a displayed image of 16: 9 has been described. An embodiment of the present invention will be described at last with respect to a television receiver having the above display.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 124 denotes a crystal oscillation circuit;
Is an oscillation output of the crystal oscillation circuit 124, 126 is a normal display having an aspect ratio of a displayed image of 4: 3, and the same components as those in FIG. 5 are denoted by the same reference numerals.

The operation in this embodiment is basically the same as that of FIG.
Since the operation is the same as that of the circuit example, only the different parts will be mainly described. In the frequency dividing circuit 122, the clock generating circuit 1
The clock having the frequency of 8f _SC output from the
Divide and write clock 123 with frequency of 4f _SC
Is input to the double speed conversion circuit 105. Further, in the decoder 126, the frequency f
A clock having a frequency of _H is input, decoded, and input to the double speed conversion circuit 105 as a write reset signal (WR) of a vertical cycle.

On the other hand, an oscillation output 125 output from the crystal oscillation circuit 124 has a frequency of 8 f _SC , and is input to the horizontal drive pulse generation circuit 109 and the timing generation circuit 110, respectively. Is also entered.

The horizontal drive pulse generation circuit 109 divides the frequency of the input oscillation output 125 to generate a horizontal drive pulse having a frequency of 2 f _H , and
0 and the display 126 respectively.

The timing generation circuit 110 generates a read reset signal (RR) 114 having a vertical cycle based on the oscillation output 105 and the horizontal drive pulse, and outputs the signal to the double speed conversion circuit 105.

Next, the double speed conversion circuit 105 inputs the real signal and the interpolation signal generated by the motion adaptive scanning line interpolation circuit 104 and writes them into the line memories 105a and 105b. At that time, each line memory 105a, 105
b are respectively reset by a write reset signal (WR) of a vertical cycle inputted from the decoder 116, and from that time, in synchronization with a write clock 123 having a frequency of 4f _SC inputted from the frequency divider 122, The real signal and the interpolation signal from the motion adaptive scanning line interpolation circuit 104 are written.

Then, each line memory 105a, 105
b is reset by a read reset signal (RR) 114 having a vertical period input from the timing generation circuit 110, and is read out from that point in synchronization with a read clock which is an oscillation output 125 of the crystal oscillation circuit 124.

As described above, according to the present embodiment, each line memory 105a, 105b in the double speed conversion circuit 105
A very stable read clock, which is the oscillation output 125 of the crystal oscillation circuit 124, is used to read the signal from the multiplexing circuit. Therefore, the double-speed conversion circuit 105 performs the double-speed conversion and also corrects the time axis of the signal. It can be carried out.

Therefore, even when a signal containing a time axis fluctuation reproduced from a video tape recorder or the like is input as the standard television signal 101, the time axis fluctuation is sufficiently removed and the double-speed converted signal is displayed. 126
And the circuit scale does not increase.

Next, FIG. 2 is a block diagram showing another embodiment of the present invention. In FIG. 2, 127 is a bandpass filter, and 128 is a clock generation circuit. The clock generation circuit 128 is constituted by a PLL circuit including a phase comparator 128a, a low-pass filter 128b, a voltage controlled oscillation circuit 128c, and a frequency dividing circuit 128d. In addition, the same components as those in FIG. 1 are denoted by the same reference numerals.

In this embodiment, the crystal oscillation circuit 124
Is characterized in that a clock generation circuit 128 for generating a clock synchronized with the color burst signal included in the standard television signal 101 is used instead of the above.

The operation of this embodiment is basically the same as that of FIG.
Since the operation is the same as that of the embodiment, only different parts will be mainly described. Standard television signal 101 input
, Only the color signal band is extracted by the band-pass filter 127, and the output color burst signal is input to the clock generation circuit 128.

The input color burst signal is compared in phase with the clock from the frequency dividing circuit 128d having the same frequency as the frequency f _{SC of} the color burst signal in the phase comparator 128a. The comparison result is output to the voltage controlled oscillation circuit 128c via the low-pass filter 128b.
, The oscillation frequency of which is controlled by the voltage-controlled oscillation circuit 128c and synchronized with the color burst signal.
Generate a clock with _SC frequency. This clock is input to the frequency dividing circuit 128d, frequency-divided by 8, and input to the phase comparator 128a as a clock having the same frequency as the frequency f _SC of the color burst signal as described above.

Generally, a color burst signal included in a standard television signal, including a signal reproduced from a video tape recorder or the like, has a small time axis fluctuation and is stable, and thus is included in the standard television signal 101 as described above. A very stable clock can be obtained by generating a clock using the clock generation circuit 128 including a PLL circuit based on the obtained color burst signal.

Then, this clock is supplied to the double speed conversion circuit 1
1 is used as a read clock for reading signals from the line memories 105a and 105b in the same manner as in the embodiment of FIG.
In this case, the double-speed conversion can be performed, and the time axis of the signal can be corrected.

Therefore, even if a signal containing a time axis fluctuation reproduced from a video tape recorder or the like is input as the standard television signal 101, the time axis fluctuation is sufficiently removed and the double-speed converted signal is displayed. 126
And the circuit scale does not increase.

In each of the above embodiments, the case where the present invention is applied to a television receiver, which is one of the image display devices, has been described as an example. For example, the present invention can be applied to a monitor, a projection tube, and the like.

[0077]

As described above, according to the present invention,
In an image display apparatus having a display and displaying the input television signal by multiplying the number of scanning lines by N (N is an integer of 2 or more), when a television signal is read from a storage unit in the N × speed means, Since reading is performed in synchronization with an oscillation output with a very stable oscillation cycle from an oscillation circuit or the like (while writing,
Depends on the horizontal sync signal in synchronization with the horizontal sync signal
Writing with the oscillation output from the oscillation means that oscillates
Therefore , the N-times speed means can perform the double-speed conversion and also perform the time axis correction of the signal.

Accordingly, a signal containing time axis fluctuation reproduced from a video tape recorder or the like is input to an input television signal.
Even when entered as No., the time base fluctuations and sufficiently removed, the double-speed converted signal without time base fluctuation can be displayed on the display, moreover, there is no fact that the circuit scale increases.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing an example of an image display device useful for understanding an embodiment of the present invention.

FIG. 4 is a waveform chart showing a main part signal waveform in FIG. 3;

FIG. 5 is a block diagram showing another example of an image display device useful for understanding the embodiment of the present invention.

FIG. 6 is a waveform chart showing a main part signal waveform in FIG. 5;

FIG. 7 is an explanatory diagram for explaining a display result when an image based on a standard television signal having an aspect ratio of 4: 3 is displayed on a horizontally long display having an aspect ratio of 16: 9 in the conventional example and the present invention. It is.

[Explanation of symbols]

101: standard television signal, 102: A / D converter, 103: motion adaptive Y / C separation circuit, 104: motion adaptive scanning line interpolation circuit, 105: double speed conversion circuit, 106
... Synchronization separation circuit, 107 ... Clock generation circuit, 108 ...
Crystal oscillation circuit, 109 horizontal drive pulse generation circuit, 11
0 ... timing generation circuit, 111, 119 ... gate circuit, 116 ... decoder, 117 ... compression circuit, 120 ... D
/ A converter, 124: crystal oscillation circuit, 126: display.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takayuki Mori 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Nao Suzuki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Hitachi, Hitachi Video Engineering Co., Ltd. (56) References JP-A-62-266988 (JP, A) JP-A-63-117582 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 7 / 01

Claims (2)

(57) [Claims] A display for displaying an input television signal.
In an image display device with play, oscillate using a clock with high oscillation cycle stability as a unit output
First oscillating means for outputting, and oscillating output of the first oscillating means.
A horizontal drive for driving the display based on force
Horizontal drive pulse generating means for generating a driving pulse;
The horizontal sync signal is synchronized with the horizontal sync signal of the revision.
Second oscillating means that oscillates depending on the
Signal and scan lines of the input television signal.
Multiply the number by N (where N is 2 or an integer greater than 2)
And N-speed means for force, upon incorporation of an input television signal to the N times speed means
When writing, horizontal synchronization of the input television signal
The second oscillating means which oscillates dependently in synchronization with a signal
The input television signal is written with the oscillation output from the stage, and the N-fold speed television signal from the N-times speed means is output.
When reading at the time of output, the horizontal drive pulse is generated.
In synchronism with the output of the means,
A clock with high stability of the oscillation period
The vision signal is read out, and the oscillation output of the first oscillation means indicates the stability of the oscillation cycle.
A high clock, and an oscillation output of the second oscillation means.
Is synchronized with the horizontal synchronization signal of the input television signal.
Since the oscillation output depends on the horizontal synchronization signal,
In the television signal output from the N-times speed means,
In this case, the time axis fluctuation that had occurred before the double-speed conversion
Writing / reading means for removing time-axis fluctuations contained in the input television signal.
Displaying an N-speed television signal on the display;
An image display device characterized in that: 2. The image display device according to claim 1, wherein said first oscillating means comprises means for oscillating in synchronization with a color burst signal extracted from an input television signal. Display device.