JPH09233403A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display an image without distortion and to prevent uneven deterioration in the fluorescent material of a screen in the image display device whose aspect ratio differs from that of a standard television signal by using a compression means so as to compress the standard television signal in a time base direction and displaying the resulting signal onto the display device. SOLUTION: Time base revision means 117, 110, 111, 116 store a received standard television signal to revise the time base of the standard television signal so that the standard television signal is compressed in a time base direction in a rate of the aspect ratio of the display device screen to the aspect ratio of the standard television signal. A frame signal insert means 119 inserts a frame signal with a prescribed signal level to a non-signal part located at both ends of the display screen caused due to the rate of the aspect ratio of the display device screen to the aspect ratio of the standard television signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a television receiver,
The present invention relates to an image display device such as a monitor and a projection tube.

[0002]

2. Description of the Related Art As an image display device, for example, in recent television receivers, there is a demand for power and a sense of presence due to a large screen and high image quality. On the other hand, in order to increase the power and the sense of presence as image information, a lot of wide-screen information of a horizontally long movie size, which has no image information at the top and bottom of the screen (that is, has upper and lower blanks), is being made.

Under such circumstances, recently, the number of scanning lines has been doubled from the current NTSC system to broaden the frequency band to achieve high resolution and the aspect ratio of the displayed image. Horizontal than the current 4: 3, for example,
A 16: 9 television system has been proposed, and a television receiver having a horizontally long display has been put into practical use based on this proposal. Further, such a television receiver having a horizontally long display in which the aspect ratio of the displayed image is 16: 9 has an aspect ratio of 4 :.
A television receiver having a function of displaying an image obtained from the current television signal of No. 3 (hereinafter, referred to as a standard television signal) has also been proposed.

However, a television receiver having such a function receives the current television broadcast and has an aspect ratio of 4: as shown in FIG.
When an image obtained from the standard television signal of No. 3 is displayed on the entire screen of a horizontally long display having an aspect ratio of 16: 9, there is a problem that the image is distorted as shown in FIG.

That is, in this case, since the aspect ratio of the image obtained from the standard television signal is 4: 3 = 12: 9, the aspect ratio of the image is 16: 9 when the images are vertically aligned.
When it is displayed on the horizontally long display, the displayed image is stretched by 16/12 = 4/3 times in the horizontal direction.

Therefore, in the prior art, the deflection current is controlled so that only a part of the screen of the display is scanned with the electron beam, and an image having an aspect ratio of 4: 3 is displayed on that part, so that the image shown in FIG. As shown in c), an image without distortion was obtained. Note that, as such a conventional technique, for example, JP-A-61-206381 can be cited.

By the way, recently, even in a television receiver having a normal display in which an aspect ratio of an image to be displayed is 4: 3, the number of scanning lines of a standard television signal is about 2 in the current NTSC system. Some have doubled the resolution to achieve higher resolution.

[0008]

As described above, in the related art, a horizontally long display having an aspect ratio of 16: 9, which has a function of displaying an image obtained from a standard television signal having an aspect ratio of 4: 3, is also available. In the case of displaying a picture obtained from a standard television signal with an aspect ratio of 4: 3, there is a television receiver having an electron beam, and the deflection current is controlled so that only a part of the screen of the display is controlled by the electron beam. Then, the image is displayed on that portion by scanning with, so that an image without distortion is obtained.

Further, even in a television receiver having a normal display with an aspect ratio of 4: 3, one having a high resolution by doubling the number of scanning lines of a standard television signal as compared with the current NTSC system is known. there were.

In the former television receiver, since only a part of the screen of the display is scanned with the electron beam, only the image obtained from the standard television signal with the aspect ratio of 4: 3 is displayed. When,
There is a problem that only the scanned portion of the phosphor on the screen of the display deteriorates faster than the unscanned portion. There is also a problem that the circuit configuration for controlling the deflection current becomes complicated.

On the other hand, in the latter television receiver, there is no problem in receiving an existing television broadcast and displaying an image, but a time axis like a signal reproduced from a video tape recorder or the like. When a television signal including fluctuations (jitter) is input to display an image, there is a problem that the image quality is deteriorated because the temporal axis fluctuation eliminating capability is low. In addition, when a time axis correction circuit is newly provided to solve the problem, there is a problem that the circuit scale becomes large.

The present invention has been made to solve the former problem among the above problems of the prior art,
Therefore, an object of the present invention is to provide a standard television as an image display device having a display in which the aspect ratio of the displayed image is different from the aspect ratio of the standard television signal (for example, a horizontally long display having an aspect ratio of 16: 9). When an image obtained from a signal is displayed, the image can be displayed without distortion, and even when only an image obtained from a standard television signal is displayed, unevenness in the screen due to deterioration of the phosphor on the screen of the display is displayed. An object of the present invention is to provide an image display device that does not cause (unevenness of deterioration caused by the presence of a scanned portion and a non-scanned portion) and that can be configured with a simple circuit.

[0013]

In order to achieve the above object, according to the present invention, in an image display device having a display in which the aspect ratio of a displayed image is different from the aspect ratio of a standard television signal, an input standard television signal is used. The time axis of the standard television signal is changed so as to compress the standard television signal in the time axis direction at a ratio corresponding to the ratio of the aspect ratio of the display image and the aspect ratio of the standard television signal. A time axis changing means for outputting and a television signal output from the time axis changing means, the display occurring due to the ratio between the aspect ratio of the display image and the aspect ratio of the standard television signal. It has a frame signal inserting means for inserting a frame signal having a specific signal level into the non-signal portions located at both ends of the image. It was.

[0014]

In the present invention, the standard television signal is
Even though it is displayed on a display having an aspect ratio different from that of a standard television signal, it can be displayed without distortion and the entire screen can be scanned to prevent uneven deterioration of the phosphor. .

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
In this embodiment, the present invention is applied to a television receiver which is one of image display devices.

In FIG. 1, 101 is a standard television signal having an aspect ratio of 4: 3, 102 is an analog / digital (hereinafter referred to as A / D) converter, and 103.
Is a motion adaptive luminance signal / color signal (hereinafter referred to as Y / C) separation circuit, 104 is a motion adaptive scanning line interpolation circuit,
Reference numeral 105 is a double speed conversion circuit.

The double speed conversion circuit 105 is composed of line memories 105a and 105b and a switching circuit 105c, receives a signal from the motion adaptive scanning line interpolation circuit 104, doubles the frequency and outputs the signal. Further, 106 is a sync separation circuit for separating a horizontal sync signal (hereinafter, the frequency of this signal, that is, the horizontal frequency is f _H ) from the standard television signal 101, and 107 is a clock generation circuit.

The clock generation circuit 107 is composed of a phase locked loop (hereinafter referred to as PLL) circuit composed of a phase comparator 107a, a low pass filter 107b, a voltage controlled oscillator circuit 107c, and a counter 107d, and a sync separation circuit 106. Generates a clock synchronized with the horizontal sync signal of.

Reference numeral 108 is a crystal oscillation circuit, reference numeral 109 is a horizontal drive pulse generation circuit for dividing the oscillation output from the crystal oscillation circuit 108 to generate a horizontal drive pulse having a frequency of 2f _H , and reference numeral 110 is the crystal oscillation circuit 108. From the horizontal drive pulse generation circuit 109 and the oscillation output from the horizontal drive pulse generation circuit 109 to generate various signals synchronized with the horizontal drive pulse from the oscillation output, 111 is a gate circuit, 112 is a gate circuit 111. This is a control signal for controlling.

Reference numeral 113 is a clock for giving a read timing in a compression circuit 117 described later, 114 is a read reset signal (RR) indicating a read start position in the compression circuit 117 described later, and 115 is for controlling a gate circuit 119 described later. Is a control signal, and a decoder 116 creates a write reset signal (WR) indicating a write start position in the compression circuit 117 described later.

Reference numeral 117 denotes a compression circuit which has a buffer memory for storing a signal, and compresses the signal from the double speed conversion circuit 105 in the time direction, and 118 denotes a clock generation circuit 107.
8f _SC, which is one of the outputs of f (f _SC is the color subcarrier frequency)
A clock having a frequency of 119, a gate circuit 119,
Is a digital / analog (hereinafter referred to as D / A) converter, and 121 has an aspect ratio of a displayed image of 16: 9.
Is a landscape display. The above is the configuration of the present embodiment, and next, the operation of the present embodiment will be described.

FIG. 2 is a waveform diagram showing a main part signal waveform in FIG. The input standard television signal 101 having an aspect ratio of 4: 3 is separated into horizontal sync signals as shown in FIG. 2A by the sync separation circuit 106, and the horizontal sync signals are input to the clock generation circuit 107. To be done.

The input horizontal synchronizing signal is supplied to the phase comparator 1
At 07a, the phase is compared with the clock from the counter 107d having the same frequency as the frequency f _H of the horizontal synchronizing signal. Then, the comparison result is the low-pass filter 1.
Is input to the voltage controlled oscillator circuit 107c via 07b,
The oscillation frequency is controlled to be 1820 times the frequency f _H of the horizontal synchronizing signal synchronized with the horizontal synchronizing signal by the voltage controlled oscillator 107c, as shown in FIG.
Generate a clock 118 with a frequency of f _SC .

This clock 118 having a frequency of 8f _SC
Is input to the compression circuit 117 as a write clock and also to the counter 107d. Counter 1
The clock 118 input to 07d is the counter 107.
It is divided by 910 at d and inputted to the switching circuit 105c of the double speed conversion circuit 105 as a clock having a frequency of 2f _H , and at the same time divided by 1820 as a clock having a frequency of f _H , the decoder 116 and the phase comparison described above. Bowl 1
It is input to 07a.

At the decoder 116, the input f _H
A clock having a frequency of is decoded and sent to the compression circuit 117 as a write reset signal (WR) having a vertical cycle as shown in FIG.

The standard television signal 101 is A
As shown in FIG. 2B, the signal is converted into a digital signal by the / D converter 102 and input to the motion adaptive scanning line interpolation circuit 104 via the motion adaptive Y / C separation circuit 103.
In FIG. 2B, the numbers in parentheses are the numbers of data in the digital signal, and the same applies hereinafter.

The motion-adaptive scanning line interpolation circuit 104 creates an actual signal and an interpolation signal from the input signal. The created real signal and the interpolated signal are respectively input to the double speed conversion circuit 105, the frequency is doubled, and alternately output every ½ horizontal cycle as shown in FIG. 2C. It In this way, the double speed conversion circuit 105 outputs a signal with high image quality. In FIG. 2C, R is an actual signal, I is an interpolation signal, and so on.

FIG. 2 output from the double speed conversion circuit 105.
The signal shown in (f) is input to the compression circuit 117 having a buffer memory. In the compression circuit 117, the write reset signal (W
R) resets the buffer memory, and 8f from the clock generation circuit 107 starts from the time when it is reset.
_The input signal from the double speed conversion circuit 105 is written in the buffer memory in synchronization with the write clock 118 having the frequency of _SC .

The oscillation output from the crystal oscillator circuit 108 is (32/3) f as shown in FIG. 2 (i).
_It has a frequency of _SC and is input to the horizontal drive pulse generation circuit 109, the timing generation circuit 110, and the gate circuit 111, respectively. The horizontal drive pulse generation circuit 109 divides the input oscillation output to generate a horizontal drive pulse as shown in FIG. 2 (n) and outputs it to the timing generation circuit 110 and the display 121, respectively.

In the timing generation circuit 110, a read reset signal (RR) 114 having a vertical cycle as shown in FIG. 2G is created based on the input oscillation output from the crystal oscillation circuit 108 and the horizontal drive pulse. , To the compression circuit 117.

Here, the reset at the time of reading the buffer memory in the compression circuit 117 is performed by the read reset signal (RR) 114 shown in FIG.
It is performed in the same vertical cycle as the write reset signal (WR) shown in (d), but with a phase shift of 1/2 horizontal cycle. This is to prevent the signal writing and the signal reading from the buffer memory from competing with each other.

Further, in the timing generation circuit 110, 2f is output from the oscillation output from the crystal oscillation circuit 108 which is input.
Fig. 2 (h) synchronized with a horizontal drive pulse having a frequency of _H
The control circuit 112 shown in FIG.
Enter 1 The control signal 112 is transmitted to the compression circuit 117.
Is a signal that specifies the read period of the buffer memory in.

The gate circuit 111 calculates the logical product of the oscillation output from the crystal oscillation circuit 108 and the control signal 112, and outputs the read clock 1 as shown in FIG. 2 (j).
13 is obtained and input to the compression circuit 117.

Therefore, when the signal (data) is read from the buffer memory in accordance with the read clock 113 in the compression circuit 117, the signal is read separately as shown in FIG. 2 (k). In addition, in FIG.
A is a video period portion, B is a black level period portion, and the rest is a non-reading period. On the other hand, the timing generation circuit 1
In FIG. 10, the control signal 115 as shown in FIG. 2L having the same timing as the non-reading period, which is synchronized with the horizontal drive pulse, is generated from the input oscillation output from the crystal oscillation circuit 108, and the gate circuit is generated. Input to 119.

The gate circuit 119 inputs the signal output from the compression circuit 117, and based on the control signal 115,
As shown in FIG. 2M, a frame signal, that is, a signal having another predetermined level (hatched portion) is added and output only in the non-reading period. The signal output from the gate circuit 119 is then converted into an analog signal in the D / A converter 120 and input to the display 121.
Then, in the display 121, the D / A converter 120
The signal input from is displayed based on the horizontal drive pulse previously input.

As described above, in the present embodiment, the write clock 118 having a frequency of 8f _SC is used for writing the signal to the buffer memory in the compression circuit 117, and the signal is read from the buffer memory for the writing. , Read clock 1 with a frequency of (32/3) f _SC
13 is used, and the read frequency (32/3) f _SC in the buffer memory is 4/3 of the write frequency 8f _SC .
Therefore, the compression circuit 117 compresses the signal 3/4 times in the time direction.

Therefore, when this compressed signal is displayed on the display 121, the display 121 expands it by a factor of 4/3, so that the distortion of the display 121 as shown in FIG. No image can be displayed. However, in FIG. 5C, the difference from the conventional one is that in this embodiment, the image obtained by the frame signal, that is, the frame is displayed at both end portions of the screen, and this portion is also sufficiently scanned by the electron beam. That is the point.

Further, in the present embodiment, the compression circuit 11
To read the signal from the buffer memory in 7,
Since the very stable read clock 113 obtained from the oscillation output from the crystal oscillating circuit 108 is used, the compression circuit 117 can perform the above-mentioned signal compression as well as the time-axis correction of the signal. Therefore, even when a signal reproduced from a video tape recorder or the like containing a time base fluctuation is input as the standard television signal 101, the time base fluctuation is sufficiently removed and the display 1
21 can be displayed.

Further, in the present embodiment, the compression circuit 11
7. When the signal is read out from the buffer memory in No. 7, the signal is read so as to be displayed in the center of the screen on the display 121 by reading out the signal by dividing the signal into the video period portion and the black level period portion. However, since the black level period portion can be read so as to be included in the horizontal blanking period, it is possible to correctly reproduce the black level.

In this embodiment, the read clock 113 used for reading a signal is obtained from the oscillation output from the crystal oscillation circuit 108, but even if it is not obtained from the oscillation output from the crystal oscillation circuit 108, for example, A signal synchronized with the color burst signal included in the standard television signal 101 may be generated by the PLL circuit and obtained from the generated signal.

Further, in this embodiment, the frame signal is added by digital processing in the latter stage of the compression circuit 117, but it is switched to a predetermined DC level by analog processing in the latter stage of the D / A converter 120. It may be added in. Next, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a waveform diagram showing a main part signal waveform in FIG.

In FIG. 3, 122 is a frequency dividing circuit and 123
Is a write clock output from the frequency dividing circuit 122, and other same components as those in FIG. 1 are denoted by the same reference numerals.

In the present embodiment, the compression circuit 1 performs the signal compression operation performed in the compression circuit 117 together with the double speed conversion operation in the double speed conversion circuit 105.
The feature is that 17 is deleted.

The operation of this embodiment is basically as shown in FIG.
Since the operation is the same as that of the embodiment described above, only different parts will be mainly described. In the frequency dividing circuit 122, the clock generating circuit 1
2 clocks with a frequency of 8f _SC output from 07
Write clock 123 divided by frequency of 4f _SC
Is output to the double speed conversion circuit 105. Further, in the decoder 116, f output from the clock generation circuit 107
A clock having an _H frequency is input, decoded, and output as a vertical cycle write reset signal (WR) to the double speed conversion circuit 105.

Next, in the double speed conversion circuit 105, the actual signal and the interpolation signal created by the motion adaptive scanning line interpolation circuit 104 are input and written into the line memories 105a and 105b, respectively. At that time, each line memory 105a, 105
4 b input from the decoder 116.
It is reset by a write reset signal (WR) having a vertical cycle as shown in FIG.
2 is input from the motion adaptive scanning line interpolation circuit 104 in synchronization with the write clock 123 having a frequency of 4f _SC as shown in FIG. 4B and the interpolation signal. Is written.

Then, each line memory 105a, 105
b is reset by a read reset signal (RR) 114 having a vertical cycle input from the timing generation circuit 110, and from that point, the read clock 11 as shown in FIG. 4D input from the gate circuit 112.
It is read in synchronism with 3.

In this way, each line memory 105a, 1a
When the signal is read from the reference numeral 05b in accordance with the read clock 113, the signal is read separately in the video period portion and the black level period portion as described in the embodiment of FIG. The signal is read so as to be included in the period and output as a signal as shown in FIG. As described above, in the double speed conversion circuit 105, the signal compression operation is performed together with the double speed conversion operation.

According to the present embodiment, the signal compression operation in the double speed conversion circuit 105 described above compresses the signal 3/4 times in the time direction as in the embodiment of FIG. Then, when this compressed signal is displayed on the display 121, the display 121 expands it by a factor of 4/3, so that an image without distortion can be displayed on the screen of the display 121.

Also in the present embodiment, in reading signals from the line memories 105a and 105b in the double speed conversion circuit 105, a very stable read clock 113 obtained from an oscillation output from the crystal oscillation circuit 108.
Therefore, the double speed conversion circuit 105 can perform double speed conversion and signal compression as well as time axis correction of the signal.

Further, in this embodiment, since the compression circuit is omitted, the circuit configuration becomes simpler than that of the embodiment of FIG. In each of the above embodiments, the case where the present invention is applied to a television receiver, which is one of the image display devices, has been described as an example, but the present invention may be applied to other image display devices, for example. It can also be applied to monitors, projection tubes, etc.

[0051]

As described above, according to the present invention,
In an image display device having a display in which the aspect ratio of the displayed image is different from the aspect ratio of the standard television signal, after compressing the standard television signal in the time direction by the compression means, the image is displayed on the display. Can be displayed without distortion.

Further, even when displaying an image based on the standard television signal, the electron beam scanning on the display covers the entire screen. Therefore, even if only the image based on the standard television signal is displayed, the screen of the display is displayed. There is no unevenness in the deterioration of the phosphor, and the circuit configuration itself is simple.

Further, when the standard television signal is read from the storage section of the compression means, the standard television signal is read in synchronization with a very stable oscillation output from a crystal oscillation circuit or the like. It is possible to perform not only compression but also time-axis correction of the signal. In addition, even if the signal is read so that the video period portion is displayed in the center of the screen of the display by reading the signal separately for the video period portion and the black level period portion, the black level period portion is horizontally retraced. Since the data can be read so as to be included within the period, it is possible to correctly reproduce the black level.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram showing a main part signal waveform in FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a waveform diagram showing a main part signal waveform in FIG.

FIG. 5 is an explanatory view for explaining a display result when an image by a standard television signal having an aspect ratio of 4: 3 is displayed on a horizontally long display having an aspect ratio of 16: 9 in the conventional example and the present invention. Is.

[Explanation of symbols]

101 ... Standard television signal, 102 ... A / D converter, 103 ... Motion adaptive Y / C separation circuit, 104 ... Motion adaptive scanning line interpolation circuit, 105 ... Double speed conversion circuit, 106
... Synchronous separation circuit, 107 ... Clock generation circuit, 108 ...
Crystal oscillator circuit, 109 ... Horizontal drive pulse generation circuit, 11
0 ... Timing generation circuit, 111, 119 ... Gate circuit, 116 ... Decoder, 117 ... Compression circuit, 120 ... D
/ A converter, 121 ... Display.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Takayuki Mori Inventor Takayuki Mori 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (72) Inventor Nao Suzuki 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Tachi Video Engineering Co., Ltd.

Claims (1)

[Claims] 1. An image display device having a display in which an aspect ratio of a displayed image is different from an aspect ratio of a standard television signal, the inputted standard television signal is stored, and the aspect ratio of the display image and the standard television signal are stored. Time axis changing means (117, 1) for changing and outputting the time axis of the standard television signal so as to compress the standard television signal in the time axis direction at a rate corresponding to the aspect ratio of the signal.
10, 111, 116), and both ends of the display image generated due to the ratio between the aspect ratio of the display image and the aspect ratio of the standard television signal of the television signal output from the time axis changing means. Frame signal inserting means (119) for inserting a frame signal having a specific signal level into the no-signal portion located at
The standard TV signal is displayed on a display having an aspect ratio different from that of the standard TV signal, but is displayed without distortion and the entire screen is scanned. Image display device.