JP3149143B2 - Access arbitration method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to an information processing apparatus, a communication exchange, in particular, an ATM exchange, and other systems having a plurality of resources commonly connected by a bus.
Here, the resource refers to a memory device, an output device, a display device, an input device, a printing device, a functional unit, and other facilities including hardware for operating the system.

[0002] The present invention relates to arbitration of a plurality of access requests generated within a system with respect to a plurality of shared resources arranged in one system.

[0003]

2. Description of the Related Art The arbitration of access requests according to the prior art will be described with reference to a model shown in FIG. 8, which is based on a control method of a ring arbiter. In this model, there are eight access request sources R (1) to R (8) and eight resources S (1) to S (8) for receiving the access requests.
These are connected to the input terminal group and the output terminal group of the matrix switch means, respectively. The matrix switch means may be provided with hardware having a matrix configuration as shown in the figure, or may be a virtual one constituted by a logic circuit having a matrix function as shown and capable of transmitting an access request. The number of access request sources and the number of resources need not necessarily be equal.

The access request sources R (1) to R (8) generate access requests one after another. Since an access request is generated according to the circumstances of the source, a plurality of access requests may simultaneously compete for one resource. The contention is arbitrated by the matrix switch means, and one access request source is transmitted to one request destination resource. At this time, ring arbiter RA
(1) to RA (8) sweep the access requests as indicated by arrows in FIG. 8, and when they hit the corresponding access request, the access request is unified via the intersection C (n, m). Only one is transmitted to the resource side, and the resource accepts the access request.

When one access request is accepted,
Information indicating that the request has been accepted is sent to the request source that sent the access request. By receiving one access request, another access request sent to the ring arbiter is waited, and the other access request is detected at the next timing or at the next timing. After the access request is accepted, processing such as transfer of necessary data via the matrix switch means or another bus signal line is performed.

FIG. 9 is a conceptual diagram illustrating the operation of the ring arbiter. The number of the resource of the request destination is displayed as an access request one by one from each of the request sources R (1) to R (8). The arbitration control is executed for each resource. Now, the arbitration control is executed for the m-th resource S (m) in FIG. Each request source R (1)-R (8)
Search for an access request from the
(m) is searched to see if there is one that has issued an access request. In this example, the second request source R (2) issues an access request to the m-th resource. In the arbitration control, when this is found, this request source is connected to the resource S (m). When one is connected, the other request sources are disconnected.

If there is only one request source that has issued an access request to the m-th resource S (m), the request is immediately accepted. If there is more than one request source, arbitration is performed for contention between them. And select one to accept the request. The arbitration logic can be set variously. Here, the request sources R (1) and R (2)
,..., R (n). This logic performs equally for each request source,
Any other logic can be set to prioritize the request sources.

[0008]

In such arbitration control of access requests, each of the ring arbiters RA (1) to RA (8) for performing arbitration in the case of contention requires each request in one time slot. Only one access request issued from the source can be accepted. Even if a plurality of access requests have already been generated at each request source and they are waiting in a queue as shown at the left end of FIG. 3, only the access request indicated by the diagonal line at the head is the contention arbitration. Therefore, the second and subsequent access requests in the queue must wait at least for the next time slot.

In one request source, if the first access request in the queue is the second resource S (2) and the second access request in the queue is the resource S (3), Time slot resource S (2)
Is in a race condition with another request source and cannot be accepted, and if there is no access request from another request source to resource S (3), the access request to resource S (3) is accepted. It should have been good. In other words, the intersection of the request source of the matrix switch means and the resource S (3) is not used in this time slot. This means that although the matrix switch means still has room, it is not used for arbitration control, and the throughput of access requests is substantially suppressed.

An object of the present invention is to provide an access arbitration system which improves the throughput of access requests.

[0011]

According to the present invention, there are provided N (N is an integer of 2 or more) request sources for generating access requests;
M (M is an integer equal to or greater than 2) resources shared by the access request sources, and N × N × request sources where the N request sources are connected to the input terminal and the M resources are connected to the output terminal The present invention is embodied in a device including a matrix switch having a capacity of M and a control circuit for controlling the connection / disconnection of the intersection of the matrix switch. The control circuit is configured to control access requests generated from the N request sources,
The arbitration control is performed once for each time slot, and the connection of a large number (strictly, one or more) of the matrix switch means is simultaneously controlled for each time slot in accordance with the result of the arbitration control.

The access request source is a resource in a broad sense, and may be one of the M resources depending on the device configuration. The matrix switch means may be a matrix switch in which switches configured by hardware are arranged at intersections of a matrix,
Further, a virtual matrix switch in which a circuit for substantially connecting or disconnecting an access request at the intersection is realized by a program control circuit may be used.

Here, the feature of the present invention resides in that a register for holding, as a queue, a resource number of a request destination of an access request generated corresponding to each request source is provided. Then, the arbitration control is sequentially performed for the resource, and prior to the timing of the arbitration control performed for the resource, of the access requests held up to the respective set depths of the waiting registers, The present invention is characterized in that selection control for selecting one of resource number access requests in advance is performed.

At this time, there is provided a priority register corresponding to each stage of the wait register, the priority register holding the priority of the access request held in the wait register, and referring to the contents of the priority register, You can make a selection.

[0015] Further, there is provided means for counting the number of access requests of the resource number out of the access requests held up to the set depth of the waiting register, and the number counted by the counting means is large. Arbitration control can be performed to give priority to a thing.

As still another configuration, information on the waiting time is held for the access requests held up to the respective set depths of the waiting register, and arbitration control performed for the resource uses the longer waiting time. It can be controlled to give priority.

The set depth may be the entire depth of the register or a part of the register, and the depth may be set to an individual value instead of the same for each request source. Can also.

[0018]

In the method of the present invention, the control circuit for controlling the matrix switch means executes arbitration control for each time slot when access requests from a plurality of request sources compete with each other over time. Based on the result of the arbitration control, the intersection of the matrix switch means is connected only once in one time slot and an access request is accepted. That is, in one time slot period, the arbitration control is executed first, and then the connection state is made only once for one intersection. Therefore, one request source can make an access request only once in one time slot. One resource can accept an access request only once in one time slot.

In the method of the present invention, the resource numbers of the request destinations of the access requests generated from the request sources are held as queues in registers provided corresponding to the request sources. Then, the selection control determines which of the access requests up to the set depth of the queue is to be selected, and then executes arbitration control corresponding to resources.

In this case as well, one request source can still accept one access request in one time slot, but by doing so, it is possible to respond to one resource. Even when an access request provided for arbitration control is not accepted due to contention with another request generation source, an access request corresponding to another resource may be accepted, so that throughput is improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of the first embodiment of the present invention. FIG. 2 is a configuration diagram of the request source according to the first embodiment of the present invention.

According to the present invention, eight request sources R (1) to R (8) for generating access requests and eight request sources R (1) to R (8) shared by the access request sources are provided. Resources S (1) ~
S (8) and eight request sources R (1) to R (8) are connected to input terminals ₁₁ to ₁₈ and eight resources S (1) to S (8)
A matrix switch 3 but having a capacitance of the output terminal 2 ₁ to 2 ₈ is connected to the 8 × 8, 8 pieces of request generation source R (1) ~
For the access request generated from R (8), the arbitration unit 10 performs arbitration control once for each time slot, and disconnects one or more intersections of the matrix switch 3 for each time slot according to the result of the arbitration control. And a control circuit 4 for controlling the access control by a matrix switch disconnection unit 11.

Here, a feature of the present invention is a wait register for holding, as a queue, resource numbers of request destinations of access requests generated for each of the request sources R (1) to R (8). The control circuit 4 includes a shift register 6, and the control circuit 4 is configured to sequentially perform arbitration control in correspondence with the resources S (1) to S (8), and performs the arbitration control in response to the resources S (1) to S (8). Prior to the timing, the arbitration unit 10 is provided with selection control means for selecting one of the access requests of the resource number among the access requests held up to the set depth of the shift register 6. .

Next, the operation of the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a configuration diagram of the second embodiment of the present invention.

In FIG. 2, SR (1) to SR (D) represent components of the shift register 6. The access request generator 7 outputs the position numbers of the resources S (1) to S (8) to which access is requested, and transfers them to the shift register 6.
Here, this position number is stored in the shift register 6 in the order of SR (1),..., SR (D).

The resource S performed by the arbitration unit 10 of the control circuit 4
The search order of access requests from the request source R (n) to (m) is in the order of SR (1),..., SR (d). This SR
The range from (1) to SR (d) is the search range, and d is called the number of searches, that is, the search depth.

In FIG. 2, the search depth of the request source R (n−1) is d ′, the search depth of the request source R (n) is d, and the search depth of the request source R (n + 1) is d ″.

First, retrieval is started from SR (1) of the request source R (n-1), and retrieval is performed in this order up to SR (d '). The resource S (m) is stored in the shift register 6 in the request source R (n-1).
Since there is no access request to, the access right is transferred to the next request source R (n).

In the request source R (n), the search is started from SR (1) and the search is performed in this order up to SR (d). here,
An access request to resource S (m) exists in SR (4),
Request H from the SR (4) to the arbitration unit 10 of the control circuit 4
(n) is output. In the request source R (n), the data of SR (4) is deleted, and the data after SR (5) is packed.

Upon receiving the request H (n) from the SR (4), the arbitration unit 10 of the control circuit 4 controls the matrix switch disconnection unit 11 to execute an access relating to the SR (4).

Subsequently, SR (1) of the request source R (n + 1)
Start search from. This access permission is given to SR (3) of request source R (n + 1). An access request to the resource S (m) exists in SR (3), and a request H (n + 1) is output from SR (3) to the arbitration unit 10 of the control circuit 4. At the request source R (n + 1), the data of SR (3) is deleted and the data after SR (4) is packed.

The arbitration unit 10 of the control circuit 4 having received the request H (n + 1) from the SR (3) controls the matrix switch disconnection unit 11 to execute an access relating to the SR (3).

FIG. 3 shows the search order. FIG. 3 is a diagram showing a search order according to the first embodiment of the present invention. The search is sequentially performed from the request source R (1) to the request source R (8), and returns to the request source R (1) at the next timing. Therefore, the throughput can be improved by performing the search of the search depth d × 8 before the actual access.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a configuration diagram of the second embodiment of the present invention. The second embodiment of the present invention is characterized in that, together with the access request from the access request generation unit 7, a priority PR is externally given to each access request. A priority storage unit 9 is provided which corresponds to SR (1) to SR (D) which are the components of the shift register 6 on a one-to-one basis. This priority storage unit 9 can be realized by providing a second shift register parallel to the shift register 6. The priority is expressed by “1” or “0”. In the case of an access request to the same resources S (1) to S (8), SR (1) in which “1” is stored in the priority storage 9 is stored. 1) The access requests of SR (D) are output in preference to the access requests of SR (1) to SR (D) in which "0" is stored. In FIG.
Although the contents of (2) and SR (5) are access requests to the resource S (m), the SR (5) whose priority PR is "1"
Is the access permission. An advantage of the second embodiment of the present invention resides in that a priority PR can be externally assigned to sequentially generated access requests.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a configuration diagram of the third embodiment of the present invention. The feature of the third embodiment of the present invention is that the control circuit 4 in the first and second embodiments of the present invention includes priority setting units PR (1) to PR (1).
(8) is provided. This priority setting unit PR
(1) to PR (8) are SRT (1) to SR (R) which are shift registers 6 provided for the request generation sources R (1) to R (8), respectively.
The access request amount stored in T (8) is monitored, and a priority order for starting a search from request sources R (1) to R (8) having a large amount is added.

In FIG. 5, request sources R (5), R
(8), R (2), R (6), R (3), R (7), R (1), R
The search is performed in the order of (4). Each request source R
The search method in (1) to R (8) is the same as in the first or second embodiment of the present invention. An advantage of the third embodiment of the present invention is that the priorities are set in the order of the largest access request amount, so that the access request amounts held by the request sources R (1) to R (8) can be kept equal. Is where you can.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a configuration diagram of the fourth embodiment of the present invention. The configuration of the fourth embodiment of the present invention is the same as that of the first embodiment of the present invention. The feature of the fourth embodiment of the present invention resides in that the control circuit 4 is provided with a priority order assigning circuit 12 based on the search depth.

If an access request exists in a place where the search depth is shallow, it is understood that the access request was issued earlier. That is, an access request whose search depth is shallow when viewed from the SR (1) side is an access request having a long waiting time when viewed from the SR (D) side. The access request with a long waiting time is output with priority. An advantage of the fourth embodiment of the present invention is that an access request having a long waiting time can be prioritized regardless of the search order.

FIG. 7 shows another example of the search order shown in the first to fourth embodiments of the present invention. FIG. 7 is a diagram showing another search order. In the first to fourth embodiments of the present invention, a search is performed for each of the request sources R (1) to R (8). However, as shown in FIG.
It is also possible to adopt a configuration in which a search is performed for each (D).

Each SR (1) of each request source R (1) to R (8)
, And then each request source R (1) to R (8)
Search all the SR (2) of. In this manner, a configuration may be employed in which the request sources R (1) to R (8) are searched for each SR (1) to SR (D).

[0041]

As described above, according to the present invention, since the number of access request searches is plural, the probability of being granted access permission is greatly improved. Therefore, the throughput of the access request can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a request generation source according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a search order according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a fourth embodiment of the present invention.

FIG. 7 is a diagram showing another search order.

FIG. 8 is a configuration diagram of a conventional example.

FIG. 9 illustrates a ring orbiter.

[Explanation of symbols]

1 ₁ to 1 ₈ input terminals 2 ₁ to 2 ₈ output terminals 3 matrix switch 4 control circuit 6 shift register 7 access request generation unit 9 priority storage unit 10 arbitration unit 11 matrix switch disconnection unit 12 priority assignment circuit PR priority PR (1)-PR (8) Priority setting section R (1)-R (8) Request source RA (1)-RA (8) Ring arbiter S (1)-S (8) Resource

Claims (4)

(57) [Claims] 1. N (N is an integer of 2 or more) request sources generating access requests, M (M is an integer of 2 or more) resources shared by the access request sources, and N Matrix switch means having a capacity of N × M, wherein N request sources are connected to an input terminal, and the M resources are connected to an output terminal; and for access requests generated from the N request sources, An access arbitration system comprising: a arbitration control that performs one arbitration control for each time slot; and a control circuit that controls disconnection of one or more intersections of the matrix switch means for each time slot in accordance with the result of the arbitration control. The control circuit includes a wait register that holds a resource number of a request destination of an access request generated for each of the request sources as a queue. Prior to the timing of the arbitration control performed corresponding to the resource, the access request of the resource number among the access requests held up to the respective set depths of the waiting registers is configured to be sequentially performed according to the source. An access arbitration system comprising selection control means for selecting one. 2. A system according to claim 1, further comprising: a priority register corresponding to each stage of the wait register, the priority register holding the priority of the access request held in the wait register. 2. The access arbitration method according to claim 1, further comprising means for executing the selection with reference to the following. 3. The apparatus according to claim 2, further comprising: means for counting the number of access requests of the resource number among the access requests held up to the respective set depths of the waiting register, wherein the control circuit performs the arbitration control by the counting. 2. The access arbitration method according to claim 1, further comprising: means for controlling so as to give priority to a large number counted by said means. 4. The waiting time information is held for the access request held up to the set depth of the waiting register, and the control circuit performs the arbitration control for the resource with the long waiting time. 2. The access arbitration method according to claim 1, further comprising means for controlling the priority of the access arbitration.