JP2013084750A - Method of manufacturing gan-based light-emitting diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a GaN-based light-emitting diode having a low-contact resistance n-side electrode formed on a rear face of an m-plane GaN substrate.SOLUTION: A method of manufacturing a GaN-based light-emitting diode includes: a first step of preparing an epitaxial wafer having a substrate 110 that is an n-type conductive m-plane GaN substrate, and an epitaxial layer 120 comprising a GaN-based semiconductor that is epitaxial-grown on the substrate 110 and including a pn-junction type light-emitting structure; a second step of polishing a rear face of the substrate 110 included in the epitaxial wafer; a third step of forming an n-side ohmic electrode to the whole of the rear face of the substrate 110 polished at the second step; and a fourth step of patterning the n-side ohmic electrode formed at the third step by etching.

Description

The present invention relates to a method for manufacturing a GaN-based light emitting diode having a light-emitting structure formed using a GaN-based semiconductor. The present invention relates to a method of manufacturing a diode. A GaN-based semiconductor is a compound semiconductor represented by the general formula Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1), and is a nitride semiconductor. It is also called a nitride compound semiconductor.

  2. Description of the Related Art Semiconductor light emitting devices having a pn junction type light emitting structure formed by epitaxially growing a GaN-based semiconductor on an m-plane GaN substrate are known (Non-Patent Documents 1 to 4).

  Non-Patent Documents 1 to 3 disclose light emitting diodes (LEDs), and in each element, an n-side ohmic electrode is formed on an n-type Si-doped GaN layer epitaxially grown on an m-plane GaN substrate. ing. Non-Patent Document 4 discloses a laser diode (LD). In this element, an n-side ohmic electrode is formed on the back surface of an m-plane GaN substrate. The threshold current of this laser diode is 36 mA at the time of CW driving and 28 mA at the time of pulse driving, and the threshold voltage is about 7 to 8V.

  In a light emitting device having a light emitting structure formed on a GaN substrate, it is said that it is difficult to form a good n-side ohmic electrode on the back surface of the GaN substrate (Patent Documents 1 to 6). Therefore, in the method described in Patent Document 2, the contact resistance of the n-side ohmic electrode formed on the back surface is reduced by polishing the back surface of the GaN substrate with a polishing agent having a particle diameter of 10 μm or more. It has been. In the method described in Patent Document 3, for the same purpose, the back surface of the GaN substrate is roughened by wet etching or dry etching. On the other hand, according to Patent Document 4, a damaged layer is formed when the back surface is ground, lapped or polished in order to reduce the thickness of the GaN substrate, which inhibits the formation of a good ohmic electrode. . Therefore, in the method described in Patent Document 4, the back surface of the polished GaN substrate is shaved by dry etching or wet etching. However, Patent Document 5 describes that this purpose cannot be achieved by wet etching. In the method described in Patent Document 6, the contact resistance between the GaN substrate and the n-side ohmic electrode is reduced by dry-etching the back surface of the GaN substrate and scraping off the portion containing crystal defects generated by mechanical polishing. It has been. In addition, the knowledge and invention described in these Patent Documents 1 to 6 basically relate to a c-plane GaN substrate.

  An electrode pad formed using a metal material on the element surface is essential for a light emitting diode as a part to which a power feeding member such as a metal wire, a metal bump, or solder is bonded. Since the electrode pad does not have optical transparency, a light emitting diode in which the current flowing through the light emitting structure is concentrated in a portion that is a shadow of the electrode pad when viewed from the light extraction direction has low light emission efficiency. This is because the light generated at this site is shielded and absorbed by the electrode pad and cannot be extracted efficiently outside the device. Therefore, to prevent the current from concentrating on this part, a high resistance film (insulating film) or a high resistance region is provided as a current block structure between the electrode pad and the light emitting structure to control the path of the current flowing in the element. (Patent Documents 7 to 9).

JP-A-11-340571 JP 2002-16312 A JP 2004-71657 A JP 2003-51614 A JP 2003-347660 A Japanese Patent Laid-Open No. 2004-6718 JP-A-1-151274 JP-A-7-193279 Japanese Patent Laid-Open No. 10-229219

Kuniyoshi Okamoto et al., Japanese Journal of Applied Physics, Vol. 45, No. 45, 2006, pp. L1197-L1199 Mathew C. Schmidt et al., JapaneseJournal of Applied Physics, Vol. 46, No. 7, 2007, pp.L126-L128 Shih-Pang Chang et al., Journal of The Electrochemical Society, 157 (5) H501-H503 (2010) Kuniyoshi Okamoto et al., Japanese Journal of Applied Physics, Vol. 46, No. 9, 2007, pp. L187-L189

  The main object of the present invention is to provide a method of manufacturing a GaN-based light emitting diode having a low contact resistance n-side electrode formed on the back surface of an m-plane GaN substrate.

According to the present invention, the following method for producing a GaN-based light emitting diode is provided.
(1) (i) preparing an epi wafer having a substrate which is an n-type conductive m-plane GaN substrate and an epi layer made of a GaN-based semiconductor epitaxially grown on the substrate and including a pn junction type light-emitting structure; 1 step; (ii) a second step of polishing the back surface of the substrate included in the epi-wafer; and (iii) forming an n-side ohmic electrode on the entire back surface of the substrate polished in the second step. And (iv) a fourth step of patterning the n-side ohmic electrode formed in the third step by etching.
(2) The manufacturing method according to (1), further including a fifth step of roughly processing the back surface of the substrate exposed in the fourth step.
(3) In the fifth step, the uneven pattern having periodicity is formed on the back surface of the substrate exposed in the fourth step.
(4) The n-side ohmic electrode is a polycrystalline transparent conductive oxide film, and in the fourth step, a part of the n-side ohmic electrode is etched so that the residue remains on the substrate. In the fifth step, the exposed back surface of the substrate is roughly processed by dry etching using the residue as an etching mask.
(5) The manufacturing method according to (1), further including a sixth step of forming a reflective film on the back surface of the substrate exposed in the fourth step.
(6) The manufacturing method according to (5), wherein the reflective film is a dielectric reflective film.
(7) The manufacturing method according to any one of (1) to (6), wherein the back surface of the substrate to be polished in the second step is lapped immediately before the second step.
(8) The manufacturing method in any one of said (1)-(7) whose carrier concentration of the said board | substrate is 10 ^{< 17} > cm ^<-3 >.

  According to the GaN-based light emitting diode manufacturing method according to the present invention, a GaN-based light emitting diode having a low contact resistance n-side electrode formed on the back surface of an m-plane GaN substrate can be manufactured.

It is a schematic diagram which shows the structure of the GaN-type light emitting diode which this inventor made as an experiment, FIG. 1 (a) is a top view, FIG.1 (b) is sectional drawing in the position of the XX line of FIG. It is. It is a top view of a mask pattern. It is a top view for demonstrating the direction of a mask pattern. It is a SEM image of the back surface of the m-plane GaN substrate which gave processing e. It is drawing which shows typically the structure of the GaN-type light emitting diode which can be manufactured with the manufacturing method of this invention, Fig.5 (a) is the top view seen from the epi layer side, FIG.5 (b) is FIG. It is sectional drawing in the position of XX of a). It is the top view which looked at the GaN-type light emitting diode shown in FIG. 5 from the substrate side. It is process sectional drawing for demonstrating the manufacturing method of this invention. It is process sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing which shows typically the structure of the GaN-type light emitting diode which can be manufactured with the manufacturing method of this invention. FIGS. 10A and 10B are cross-sectional views schematically showing the structure of a GaN-based light emitting diode that can be manufactured by the manufacturing method of the present invention. FIGS. 11A and 11B are diagrams illustrating patterns exhibited by the n-side ohmic electrode on the back surface of the substrate, respectively. It is drawing which shows typically the structure of the GaN-type light emitting diode which can be manufactured with the manufacturing method of this invention, Fig.12 (a) is the top view seen from the board | substrate side, FIG.12 (b) is FIG.12 (a). It is sectional drawing in the position of XX of (). It is drawing which shows typically the structure of the GaN-type light emitting diode which can be manufactured with the manufacturing method of this invention, Fig.13 (a) is the top view seen from the board | substrate side, FIG.13 (b) is FIG.13 (a). It is sectional drawing in the position of the PQ line. It is drawing which shows typically the structure of the GaN-type light emitting diode which can be manufactured with the manufacturing method of this invention, Fig.14 (a) is the top view seen from the board | substrate side, FIG.14 (b) is FIG.14 (a). It is sectional drawing in the position of the PQ line. It is drawing which shows typically the structure of the GaN-type light emitting diode which can be manufactured with the manufacturing method of this invention, Fig.15 (a) is the top view seen from the board | substrate side, FIG.15 (b) is FIG.15 (a). It is sectional drawing in the position of XX of (). It is process sectional drawing for demonstrating the manufacturing method of this invention. It is process sectional drawing for demonstrating the manufacturing method of this invention. It is drawing which shows typically the structure of the GaN-type light emitting diode which can be manufactured with the manufacturing method of this invention, Fig.18 (a) is the top view seen from the board | substrate side, FIG.18 (b) is FIG.18 (a). It is sectional drawing in the position of the PQ line.

  FIG. 5 schematically shows the structure of a GaN-based light emitting diode that can be manufactured using the manufacturing method of the present invention. A GaN-based light emitting diode 101 shown in FIG. 5 has a substrate 110 and an epitaxial layer 120 made of a GaN-based semiconductor epitaxially grown thereon. FIG. 5A is a plan view of the GaN-based light emitting diode 101 viewed from the epi layer 120 side, and FIG. 5B is a cross-sectional view taken along the line XX in FIG. FIG. 6 shows a plan view of the GaN-based light emitting diode 101 as viewed from the substrate 110 side.

  The substrate 110 is an n-type conductive m-plane GaN substrate. The epi layer 120 includes an n-type layer 121 and a p-type layer 123 that form a pn junction. An active layer 122 is provided between the n-type layer 121 and the p-type layer 123 so that a double heterostructure is formed. An n-side electrode E100 that serves both as an ohmic electrode and an electrode pad is formed on the back surface of the substrate 110. On the epi layer 120, a p-side ohmic electrode E201 which is a translucent electrode is formed. Light emission occurs in the active layer 122 by applying a forward voltage to the epi layer 120 through the n-side electrode E100 and the p-side electrode pad E202 formed in part on the p-side ohmic electrode E201. This light is emitted to the outside of the GaN-based light emitting diode 101 from the surface of the p-side ohmic electrode E201, the end face of the epi layer 120, the end face of the substrate 110, and the like.

  The n-side electrode E100 is formed of a material that forms an ohmic contact with an n-type GaN-based semiconductor, such as Al, Ti, Cr, V, W, or ITO, at least at a portion in contact with the substrate 110. In a preferred embodiment, the n-side electrode E100 is formed of Al, Ti, Cr, V, W, ITO, or the like in contact with the substrate 110, and further has a conductive property such as Au, Al, Cu, or Ag. A multi-layer structure in which layers made of a high metal are laminated.

  The p-side ohmic electrode E201 is formed of a transparent conductive oxide (TCO; Transparent Conductive Oxide) such as ITO. Preferably, the p-side ohmic electrode E201 is provided so as to cover the entire top surface of the p-type layer 123. The p-side electrode pad E202 is formed using metal. In a preferred embodiment, the p-side electrode pad E202 is formed of a metal having excellent adhesion to TCO, such as Cr, Ti, Ni, Pt, and Rh, in contact with the p-side ohmic electrode E201. A multilayer structure in which layers made of highly conductive metals such as Au, Al, Cu, and Ag are stacked. The thickness of the p-side ohmic electrode E201 made of TCO is preferably 0.1 μm to 0.5 μm, and the thickness of the p-side electrode pad E202 made of metal is preferably 0.5 μm to 5 μm.

  As shown in FIG. 6, the n-side electrode E100 formed on the back surface of the substrate 110 is patterned into a specific shape. At the center of the n-side electrode E100, a circular opening is provided at a position overlapping the orthogonal projection of the p-side electrode pad E202 on the back surface of the substrate 110. Due to this opening, the current flowing from the p-side electrode pad E202 to the epi layer 120 does not concentrate directly below the p-side electrode pad E202. That is, the current does not concentrate on the path indicated by the arrow in FIG. As a result, the shielding and absorption received by the p-side electrode pad E202 by the light generated in the active layer 122 is reduced as compared with the case where current is concentrated in this path. In addition, since the density of the current flowing across the active layer 122 becomes more uniform, a reduction in light emission efficiency due to the droop phenomenon (a phenomenon in which the light emission efficiency decreases as the current density increases, which is peculiar to a GaN-based light emitting diode) is suppressed. Is done.

Next, the manufacturing method according to the embodiment of the present invention will be described by taking as an example the case of manufacturing the GaN-based light emitting diode 101 shown in FIG. The GaN-based light emitting diode 101 can be manufactured by sequentially executing the steps (A) to (G) described below.
(A) Preparation of Epi Wafer In the first step, as shown in FIG. 7A, an n-type layer 121 made of a GaN-based semiconductor, an active layer 122, and a p-type are formed on an n-type conductive m-plane GaN substrate 110. An epi wafer on which the epi layer 120 including the layer 123 is formed is prepared. The thickness of the substrate 110 at this stage is typically 300 μm to 1 mm.
(B) Process of Epi Layer In this step, as shown in FIG. 7B, the epi layer 120 is dry-etched to form an element isolation groove G100. Then, the p-side ohmic electrode E201 and the p-side electrode pad E202 are sequentially formed on the p-type layer 123 of each light-emitting diode section partitioned by the element isolation trench G100. The order of forming the element isolation trench G100 and the p-side ohmic electrode E201 is not limited, and the p-side ohmic electrode E201 may be formed before forming the element isolation trench G100. In this example, the element isolation groove G100 has a depth reaching the n-type layer 121, but can be formed to a depth reaching the surface or the inside of the substrate 110. Preferably, after forming the element isolation trench G100, the p-side ohmic electrode E201, and the p-side electrode pad E202, the surface of the p-side ohmic electrode E201 and the exposed surface of the epi layer 120 are made of a transparent material such as SiO ₂ or SiN _x. And an insulating protective film (not shown).
(C) Substrate Thinning In this step, the back surface of the substrate 110 is ground or lapped to reduce the thickness of the substrate 110 as shown in FIG. When grinding is performed, lapping is continuously performed to reduce the roughness of the processed surface. At the time of this lapping, it is preferable to gradually reduce the particle diameter of the diamond abrasive used.
(D) Polishing of Backside of Substrate In this step, an acidic CMP slurry is used to polish the backside of the substrate 110 at a low polishing rate of 0.5 μm / h or less, and the range of 10 μm square measured using AFM. The arithmetic average roughness Ra is set to 0.1 nm or less. In the case where the back surface of the substrate 110 before polishing is a rough surface such as a ground surface, polishing is performed after lapping is performed as preliminary processing to reduce the roughness. At the time of this lapping, it is desirable to gradually reduce the grain size of the diamond abrasive grains to be used. After polishing, the slurry adhering to the substrate 110 is washed away with water and dried. After washing with water, organic cleaning or ultraviolet ozone cleaning may be performed.
(E) Formation of n-side electrode In this step, as shown in FIG. 8D, the n-side electrode E100 is formed on the entire back surface of the substrate 110 into a thin film using a vapor phase method such as vapor deposition, sputtering, or CVD. Form. Thus, after polishing the surface of the substrate 110 at a low rate using an acidic slurry, the contact resistance of the n-side electrode E100 is reduced by forming the n-side electrode E100 on the polished surface. Can do.
(F) Patterning of n-side electrode In this step, as shown in FIG. 8E, an n-side electrode E100 is formed by a method of removing unnecessary portions by etching after protecting necessary portions with a mask, that is, a subtractive method. Is patterned into a predetermined shape. Mask patterning can be performed using well-known photolithography techniques. The etching method may be either wet etching or dry etching. An etchant used in wet etching and an etching gas used in dry etching may be selected by appropriately referring to known techniques. In a preferred embodiment, after patterning the n-side electrode E100, the exposed surface of the substrate 110 is covered with an insulating protective film (not shown) made of a transparent material such as SiO ₂ or SiN _x .
(G) Dicing As the last step, the epi-wafer is cut at the position of the element isolation groove G100 formed in the epi layer 120, and the chip-like GaN-based light emitting diode 101 is obtained.

  The following is a modification of the GaN-based light emitting diode 101 shown in FIG. 5, and any of them can be manufactured by sequentially executing the above steps (A) to (G). 9 to 18, the same reference numerals are given to components common to the GaN-based light emitting diode 101 illustrated in FIG. 5.

  In the GaN-based light emitting diode 102 shown in FIG. 9, a concavo-convex pattern capable of irregularly reflecting light generated in the active layer 122 is provided in a portion of the back surface of the substrate 110 that is not covered with the n-side electrode E100. This concavo-convex pattern is, for example, a pattern in which dot-shaped concave portions or convex portions are periodically arranged, and can be formed by photolithography and dry etching. The concave / convex pattern can diffusely reflect light in the near ultraviolet to visible wavelength generated in the active layer 122 if the depth of the concave portion or the height of the convex portion and the pattern period are 1 μm or more. Multiple reflections are suppressed by forming a concavo-convex pattern that can cause irregular reflection, and the light extraction efficiency is improved. Instead of forming the concavo-convex pattern having periodicity, a rough surface having no periodicity can be formed by dry etching or sand blasting using a random etching mask.

  When the GaN-based light emitting diode 102 shown in FIG. 9 is manufactured, the step of processing the back surface of the substrate 110 into an uneven shape is performed after the step of patterning the n-side electrode E100.

  In the GaN-based light-emitting diode 103 shown in FIG. 10A and the GaN-based light-emitting diode 104 shown in FIG. 10B, a patterned n-side ohmic electrode is used instead of the n-side electrode E100 that also serves as an ohmic electrode and an electrode pad. E101 and an n-side electrode pad E102 covering the same are formed on the back surface of the substrate 110. The pattern exhibited by the n-side ohmic electrode E101 on the back surface of the substrate 110 can be a dot pattern shown as an example in FIG. 11A, a net pattern shown as an example in FIG. The n-side ohmic electrode E101 is formed so as to cover the entire back surface of the substrate 110, and then patterned by removing unnecessary portions. That is, patterning is performed by a subtractive method.

  In the GaN-based light emitting diode 103 of FIG. 10A, the n-side electrode pad E102 is provided in contact with the exposed back surface of the substrate 110. In the GaN-based light emitting diode 104 of FIG. A dielectric reflection film R100 is interposed between the back surface of the electrode and the n-side electrode pad E102. A suitable example of the dielectric reflection film R is a Bragg reflection film (DBR), but is not limited, and may be a single layer film made of a dielectric having a refractive index lower than that of the substrate 110.

  In the GaN-based light emitting diodes 103 and 104, the n-side ohmic electrode E101 is formed by vapor deposition or sputtering using a material that forms an ohmic contact with an n-type GaN-based semiconductor, such as Al, Ti, Cr, V, W, or ITO. It is preferably formed to a thickness of 0.05 μm to 0.5 μm by a vapor phase method such as CVD. The n-side electrode pad E102 preferably includes a layer having a thickness of 0.5 μm to 5 μm made of a highly conductive metal such as Au, Al, Cu, or Ag. The n-side electrode pad E102 preferably includes a high reflection portion made of a metal having high reflectivity in the near ultraviolet to visible wavelength region, such as Ag, Al, Rh, and Pt, on the substrate 110 side.

  In the GaN-based light emitting diode 105 shown in FIG. 12, the electrode provided on the p-type layer 123 is a p-side electrode E200 that serves both as an ohmic electrode and an electrode pad, and light generated in the active layer 122 is emitted from the back surface of the substrate 110. The area of the n-side electrode E100 is reduced so as to be emitted from the GaN-based light emitting diode 100 to the outside. In a preferred embodiment, the p-side electrode E200 is formed of a material that forms an ohmic contact with the p-type GaN-based semiconductor at a portion in contact with the p-type layer 123, and Au, Al, Cu, Ag, or the like is formed thereon. A multi-layer structure in which layers made of highly conductive metals are stacked. Examples of the material that forms ohmic contact with the p-type GaN-based semiconductor include metals such as Ni, Au, Pd, Rh, Pt, Co, ITO, zinc-doped indium oxide, zinc oxide, tin oxide, titanium oxide, Examples thereof include transparent conductive oxides such as gallium oxide. The layer made of a highly conductive metal is preferably formed to a thickness of 0.5 μm to 5 μm.

  A GaN-based light emitting diode 106 shown in FIG. 13 is a modification of the GaN-based light emitting diode 105 shown in FIG. As a difference, as shown in FIG. 13A, which is a plan view, in the GaN-based light emitting diode 106, the n-side electrode E100 is electrically connected to the connection portion E100a, which is a portion to which a bonding wire or the like is connected, in the lateral direction ( It is comprised from the extension part E100b for extending to the direction orthogonal to the thickness direction of the board | substrate 110). In addition, in the GaN-based light emitting diode 106, as shown in FIG. 13B, which is a cross-sectional view, the exposed portion of the back surface of the substrate 110 is roughly processed. In the rough processed portion, micron-sized irregularities that can diffusely reflect the light generated in the active layer 122, submicron-sized periodic irregularities pattern that can diffract the light generated in the active layer 122, or the active layer 122 Sub-micron-sized fine irregularities that can suppress the total reflection of light are formed. The submicron-sized unevenness can be formed by a method of etching the substrate 110 using polymer fine particles or silica fine particles as a mask.

  A GaN light emitting diode 107 shown in FIG. 14 is another modification of the GaN light emitting diode 105 shown in FIG. As a difference, as shown in FIGS. 14A and 14B, in the GaN-based light emitting diode 107, a transparent conductive oxide such as ITO is used in place of the n-side electrode E100 that serves both as an ohmic electrode and an electrode pad. The formed translucent n-side ohmic electrode E101 and an n-side electrode pad E102 provided on a part thereof are formed on the back surface of the substrate 110.

  Similarly to the n-side electrode E100 in the GaN-based light emitting diode 106 of FIG. 13, the n-side electrode pad E102 includes a connection portion E102a that is a portion to which a bonding wire or the like is connected, and an extension portion E102b for spreading the current in the lateral direction. It consists of and. The translucent n-side ohmic electrode E101 is patterned by a subtractive method, and has a circular opening at a portion immediately below the n-side electrode pad E102a.

  A GaN-based light emitting diode 108 shown in FIG. 15 is yet another modification of the GaN-based light emitting diode 105 shown in FIG. As a difference, as shown in FIGS. 15A and 15B, the light-emitting diode 108 is formed of a transparent conductive oxide such as ITO instead of the n-side electrode E100 that serves both as an ohmic electrode and an electrode pad. The translucent n-side ohmic electrode E101 and the n-side electrode pad E102 provided on a part thereof are formed on the back surface of the substrate 110. However, unlike the GaN-based light emitting diode 107 of FIG. 14, the n-side ohmic electrode E101 does not cover the back surface of the substrate 110 widely, and its area is only slightly larger than the n-side electrode pad E102. In addition, in the GaN-based light emitting diode 108, unlike the GaN-based light emitting diode 105 in FIG. 12, the portion of the back surface of the substrate 110 that is not covered by the n-side ohmic electrode E101 is a rough surface.

  In order to manufacture the GaN-based light emitting diode 108 shown in FIG. 15, first, an n-type layer 121 made of a GaN-based semiconductor, an active layer 122, and a p-type layer 123 are included on an n-type conductive m-plane GaN substrate 110. An epi wafer on which the epi layer 120 is formed is prepared. Then, the epi layer 120 is dry-etched to form the element isolation groove G100, and the p-side electrode E200 is formed on the p-type layer 123 of each light-emitting diode section partitioned by the element isolation groove G100.

  After forming the p-side electrode E200, the back surface of the substrate 110 is ground or lapped to reduce the thickness of the substrate 110. When grinding is performed, lapping is continuously performed to reduce the roughness of the processed surface. Thereafter, the back surface of the substrate 110 is polished using an acidic CMP slurry at a polishing rate as low as 0.5 μm / h or less, and the arithmetic average roughness Ra in the range of 10 μm square measured using AFM is 0.1 nm. The following. After polishing, the slurry adhering to the substrate 110 is washed away with water and dried. After washing with water, organic washing or ultraviolet ozone washing may be performed.

  Next, an n-side ohmic electrode E101 made of ITO is formed in a thin film shape on the entire back surface of the substrate 110 that has been polished using a vapor phase method such as vapor deposition, sputtering, or CVD. FIG. 16A is a cross-sectional view of the epi-wafer completed up to this step.

  In the next step, the n-side ohmic electrode E101 is patterned into a predetermined shape as shown in FIG. 16B by a method of removing unnecessary portions by etching after protecting the necessary portions with a resist mask, that is, a subtractive method. To do. Patterning of the resist mask can be performed using a normal photolithography technique. Etching of ITO is preferably performed by a wet method using an aqueous iron chloride solution or hydrochloric acid as an etchant. In this wet etching, the etching time or the like is adjusted so that the unnecessary portion of ITO is not completely removed and the residue remains on the substrate 110.

  A polycrystalline TCO thin film such as ITO can increase the etching rate difference between the crystal part and the grain boundary part during wet etching by annealing after film formation to improve the crystallinity of the crystal part. . Therefore, when the n-side ohmic electrode E101 is a polycrystalline TCO film such as ITO, the TCO residue can be easily left on the substrate 110 after wet etching by heat-treating it.

  In the next step, the exposed back surface of the substrate 110 is dry-etched using chlorine gas as an etching gas while the resist mask used for protecting the n-side ohmic electrode E101 in the previous step remains as a mask. At this time, the remaining ITO residue acts as a fine mask, and as shown in FIG. 16C, innumerable fine irregularities are formed in the dry-etched portion of the substrate 110.

After dry etching, an n-side electrode pad E102 is formed on the n-side ohmic electrode E101 as shown in FIG. In a preferred embodiment, thereafter, the exposed surface of the substrate 110 is covered with an insulating protective film (not shown) made of a transparent material such as SiO ₂ or SiN _x . Then, as the last step, the epi-wafer is cut at the position of the element isolation groove G100 formed in the epi layer 120, and the chip-like GaN-based light emitting diode 108 is obtained.

A GaN-based light emitting diode 109 shown in FIG. 18 is a modification of the GaN-based light emitting diode 108 shown in FIG. As a difference, in the GaN-based light emitting diode 109, as shown in FIGS. 18 (a) and 18 (b), the n-side electrode pad E102 has a current flowing in the horizontal direction ( It is comprised from the grid-like extension part E102b for expanding to the direction orthogonal to the thickness direction of the board | substrate 110). The n-side ohmic electrode E101 interposed between the n-side electrode pad E102 and the p-type layer 123 is formed in substantially the same shape as the n-side electrode pad E102.
(Experimental result)
The results of trial manufacture and evaluation of a GaN-based light emitting diode (hereinafter also simply referred to as “LED”) by the present inventor will be described below.
1. Basic Structure of Prototype LED FIG. 1 schematically shows the basic structure of a prototype LED. 1A is a top view, and FIG. 1B is a cross-sectional view taken along the line XX in FIG. 1A. As shown to Fig.1 (a), the planar shape of LED1 is a rectangle, and a size is 350 micrometers x 340 micrometers.

As shown in FIG. 1B, the LED 1 has a semiconductor stacked body 20 made of a GaN-based semiconductor on a substrate 10. The substrate 10 is an m-plane GaN substrate, and the semiconductor stacked body 20 is disposed on the front surface 11 of the substrate 10. The semiconductor stacked body 20 includes, in order from the substrate 10 side, a first undoped GaN layer 21, a Si-doped n-type GaN contact layer 22, a second undoped GaN layer 23, a Si-doped n-type GaN cladding layer 24, an MQW. An active layer 25, a Mg-doped p-type Al _0.1 Ga _0.9 N clad layer 26, and an Mg-doped p-type Al _0.03 Ga _0.97 N contact layer 27 are provided.

The MQW active layer 25 has undoped In _0.04 Ga _0.96 N barrier layers and undoped In _0.16 Ga _0.84 N well layers that are alternately stacked. The number of undoped InGaN barrier layers is four, and the number of undoped InGaN well layers is three. Therefore, the lowermost layer and the uppermost layer of the MQW active layer 25 are both barrier layers. The composition of the well layer is adjusted so that the emission peak wavelength falls within the range of 445 to 465 nm.

  LED1 has two n-side electrodes and one p-side electrode. One of the n-side electrodes is a first n-side metal pad E11, which is provided so as to cover the entire back surface 12 of the substrate 10. The other is the second n-side metal pad E12, which is formed on the surface of the n-type GaN contact layer 22 exposed by partially removing the semiconductor stacked body 20. Both the first n-side metal pad E11 and the second n-side metal pad E12 also serve as ohmic electrodes. The p-side electrode is composed of an ohmic translucent electrode E21 formed on the upper surface of the p-type AlGaN contact layer 27 and a p-side metal pad E22 formed on a part of the translucent electrode E21. It is. The current application to the MQW active layer 25 can be performed through the first n-side metal pad E11 and the p-side metal pad E22, or can be performed through the second n-side metal pad E12 and the p-side metal pad E22. .

The first n-side metal pad E11 is a multilayer film, and includes a TiW layer, an Au layer, a Pt layer, an Au layer, a Pt layer, an Au layer, a Pt layer, and an Au layer in order from the substrate 10 side. The second n-side metal pad E12 is also a multilayer film having a similar laminated structure, and in order from the n-type GaN contact layer 22 side, a TiW layer, an Au layer, a Pt layer, an Au layer, a Pt layer, an Au layer, a Pt layer, It has an Au layer. The translucent electrode E21 is an ITO (indium tin oxide) film. The p-side metal pad E12 is a multilayer film having a laminated structure similar to that of the first n-side metal pad E11 and the second n-side metal pad E12, and sequentially includes a TiW layer, an Au layer, and Pt from the translucent electrode E21 side. A layer, an Au layer, a Pt layer, an Au layer, a Pt layer, and an Au layer.
2. LED Trial Production LED1 was produced by the following procedure.
2-1. Epitaxial growth Size is 7 mm (c-axis direction) x 15 mm (a-axis direction) x 330 μm (thickness), and the off-angle of the front surface (main surface on which the semiconductor laminate is provided) is 0 ± 0.5 ° The n-type conductive m-plane GaN substrate to which Si was added as an n-type impurity was prepared. The carrier concentration of the m-plane GaN substrate examined by hole measurement was 1.3 × 10 ¹⁷ cm ⁻³ .

A plurality of GaN-based semiconductor layers were epitaxially grown on the front surface of the m-plane GaN substrate using the atmospheric pressure MOVPE method to form a semiconductor laminate. TMG (trimethylgallium), TMI (trimethylindium) and TMA (trimethylaluminum) for Group III materials, ammonia for Group V materials, silane for Si materials, bisethylcyclopentadienylmagnesium ((EtCp) for Mg materials ) ₂ Mg) was used.

  Table 1 shows the growth temperature and film thickness of each layer.

  Table 2 shows the concentration of impurities added to the n-type GaN contact layer, n-type GaN clad layer, p-type AlGaN clad layer, and p-type AlGaN contact layer.

The activation of Mg added to the p-type AlGaN cladding layer and the p-type AlGaN contact layer is performed while the p-type AlGaN contact layer is grown for a predetermined time and then the substrate temperature is lowered to room temperature in the growth furnace of the MOVPE apparatus. This was carried out using a method for controlling the flow rates of nitrogen gas and ammonia gas flowing into the growth furnace.
2-2. Formation of p-side electrode and second n-side metal pad An ITO film having a thickness of 210 nm was formed on the surface of the semiconductor laminate formed by the epitaxial growth (surface of the p-type AlGaN contact layer) by electron beam evaporation. Subsequently, the ITO film was patterned into a predetermined shape using photolithography and etching techniques to form a translucent electrode. After patterning, a part of the semiconductor stacked body is removed by reactive ion etching (RIE) processing to expose the n-type GaN contact layer at the site where the second n-side metal pad is to be formed, and perform mesa formation. It was. In RIE processing, Cl ₂ was used as an etching gas, the antenna / bias was set to 100 W / 20 W, and the pressure in the chamber was set to 0.5 Pa.

  Subsequent to the RIE process, the produced ITO film was heat-treated at 520 ° C. for 20 minutes in the air atmosphere. Further, using an RTA (Rapid Thermal Annealing) apparatus, this ITO film was heat-treated at 500 ° C. for 1 minute in a nitrogen gas atmosphere.

After the heat treatment of the ITO film, a second n-side metal pad and a p-side metal pad were simultaneously formed in a predetermined pattern using a lift-off method. All layers (TiW layer, Au layer, and Pt layer) included in the metal multilayer film constituting the second n-side metal pad and the p-side metal pad were formed by sputtering. When forming a TiW film, a Ti-W target having a Ti content of 10 wt% is used as a target, Ar (argon) is used as a sputtering gas, sputtering conditions are RF power 800 W, Ar flow rate 50 sccm, sputtering gas pressure 2.2. × 10 ⁻¹ Pa. The thickness of the lowermost TiW layer and the Au layer laminated immediately above it was 108 nm, and the thicknesses of the other Pt layers and Au layers were all 89 nm.

After forming the second n-side metal pad and p-side metal pad, a passivation film made of SiO ₂ was formed to a thickness of 213 nm on the exposed surface of the semiconductor stacked body and the surface of the translucent electrode.
2-3. Processing of the back surface of the m-plane GaN substrate After the formation of the passivation film, six different processes described below as processing a to processing f were performed on the back surface of the m-plane GaN substrate.

  Process a: The thickness of the substrate was reduced to 200 μm by lapping and polishing the back surface of the m-plane GaN substrate in this order.

  In the lapping process, the grain size of the diamond abrasive used was gradually reduced in accordance with a conventional method.

  In the polishing step, a CMP slurry in which acid is added to acidic colloidal silica (particle size 70-100 nm) and the pH is adjusted to less than 2 is used, and the load is adjusted so that the polishing rate is 0.5 μm / h. The processing time was about 14 hours. The surface of the m-plane GaN substrate polished under these conditions has an arithmetic average roughness Ra in the range of 10 μm square measured using AFM (for example, DIMENSION 5000 manufactured by DIGITALINSTRUMENTS) of 0.1 nm or less.

  The polished surface (the back surface of the m-plane GaN substrate) is washed with water, further washed with IPA and acetone at room temperature, and then dried with ultraviolet ozone cleaning (110 ° C., oxygen flow rate 5 L / min) for 5 minutes. gave.

  Process b: After process a, the surface layer portion was further removed from the back surface of the m-plane GaN substrate by RIE. The RIE condition is the above 2-2. The etching time was set to 60 seconds so that the etching depth was 0.1 μm under the same conditions as when the RIE processing was performed on the semiconductor laminate. When the roughness of the surface after RIE processing was measured with a stylus type step gauge (ET3000 manufactured by Kosaka Laboratory Ltd.), the arithmetic average roughness Ra was 0.02 μm, and the maximum height Rz was 0.04 μm.

  Processing c: After processing a, the surface layer portion was further scraped off from the back surface of the m-plane GaN substrate by RIE. The RIE condition is the above 2-2. The etching time was set to 610 seconds so that the etching depth was 1.0 μm under the same conditions as when the semiconductor laminate was subjected to RIE processing. When the surface roughness after RIE processing was measured with a stylus profilometer, the arithmetic average roughness Ra was 0.06 μm, and the maximum height Rz was 0.55 μm.

  Processing d: After processing a, the surface layer portion was further scraped off from the back surface of the m-plane GaN substrate by RIE. The RIE condition is the above 2-2. The etching time was set to 1220 seconds so that the etching conditions were the same as those when the RIE processing was performed on the semiconductor laminate. When the surface roughness after RIE processing was measured with a stylus profilometer, the arithmetic average roughness Ra was 0.07 to 0.12 μm, and the maximum height Rz was 1.30 μm.

  Process e: A positive photoresist (Sumiresist PFI-34AL manufactured by Sumitomo Chemical Co., Ltd.) using a novolac resin is coated on the back surface of the m-plane GaN substrate after the process a to a thickness of 1.6 μm. The mask pattern shown in FIG. 2 was formed by patterning the photoresist using a photolithography technique. That is, it is a mask pattern in which a plurality of circular etching masks are arranged at the lattice positions of a triangular lattice. The diameter of each circular mask (R in FIG. 2) was 2 μm, and the space between adjacent circular masks (S in FIG. 2) was 2.5 μm. As shown in FIG. 3, the direction of the mask pattern was determined so that the two sides BC and EF of the regular hexagon ABCDEF having the six lattice positions of the triangular lattice as vertices were orthogonal to the c-axis of the m-plane GaN substrate. .

The back surface of the m-plane GaN substrate was processed into a concavo-convex shape by performing RIE using the mask pattern formed as described above as an etching mask. Cl ₂ was used as an etching gas, the antenna / bias was set to 100 W / 20 W, the pressure in the chamber was set to 0.5 Pa, and the etching selectivity was about 1. The etching selectivity here is [GaN etching rate] / [mask etching rate] when the etching time is about 800 seconds or less. Under these conditions, RIE processing was performed for 1500 seconds. The mask pattern almost disappeared when the etching time reached about 800 seconds. After the RIE processing, the wafer was cleaned using an organic solvent, and then the surface subjected to the RIE processing was subjected to ultraviolet ozone cleaning (110 ° C., oxygen flow rate 5 L / min) for 5 minutes.

  FIG. 4 shows an SEM image of the back surface of the m-plane GaN substrate subjected to the processing e. 4A is a plan view, FIG. 4B is a diagram viewed from the cross-sectional direction, and FIG. 4C is a perspective view. 4A to 4C, the direction from right to left in the drawing is the [0001] direction (c + direction) of GaN, and the direction from left to right is [000-1] of GaN. ] Direction (c-direction). The height of the protrusion formed on the back surface of the m-plane GaN substrate was 1.5 μm.

Processing f: A mask pattern was formed on the back surface of the m-plane GaN substrate after processing a by the same procedure as processing e, but after installing in the RIE chamber, the back surface of the m-plane GaN substrate was covered with a thin sapphire plate. By covering, the back surface was protected from being subjected to RIE processing. Except for this, the process performed in process f is the same as process e. That is, on the back surface of the m-plane GaN substrate subjected to processing f, a process of forming a mask pattern using a photoresist, a process of removing the mask pattern using an organic solvent, and an ultraviolet ozone after removing the mask pattern A cleaning process is being performed.
2-4. Formation of first n-side metal pad A metal multilayer film serving as a first n-side metal pad was formed on the back surface of the m-plane GaN substrate subjected to any of the above processes a to f. All layers (TiW layer, Au layer, and Pt layer) included in this metal multilayer film were formed by sputtering. When forming a TiW film, a Ti-W target having a Ti content of 10 wt% is used as a target, Ar (argon) is used as a sputtering gas, sputtering conditions are RF power 800 W, Ar flow rate 50 sccm, sputtering gas pressure 2.2. × 10 ⁻¹ Pa. The thickness of the lowermost TiW layer and the Au layer laminated immediately above it was 108 nm, and the thicknesses of the other Pt layers and Au layers were all 89 nm.

After the formation of the metal multilayer film, the wafer was divided by scribing and breaking to form LEDs as chips. The metal multilayer film was cut together with the GaN substrate in this step. Therefore, the planar shape of the first n-side metal pad is the same as the shape of the back surface of the m-plane GaN substrate. The size of the first n-side metal pad was 350 μm × 340 μm, which was substantially the same as the chip size.
2-5. Evaluation of forward voltage Forward voltage (Vf ₁ ) when current is applied through the first n-side metal pad and p-side metal pad to the LED chip obtained by the above procedure, and the second n-side The forward voltage (Vf ₂ ) when current was applied through the metal pad and the p-side metal pad was compared. The applied current was a pulse current having a pulse width of 1 msec and a pulse period of 100 msec, and the current value was 20 mA and 60 mA. The results are shown in Table 3.

As shown in Table 3, Vf ₁ and Vf ₂ coincided with the LED chip in which only the processing a was performed on the back surface of the m-plane GaN substrate, whereas Vf ₁ was all in the LED chips subjected to processing b to f. It becomes larger than the vf _2. In particular, the difference between the LED chips subjected to processing b to e including RIE processing was several V or more.

101, 102, 103, 104, 105, 106, 107, 108, 109 GaN-based light emitting diode 110 Substrate 120 Epi layer 121 n-type layer 122 active layer 123 p-type layer E100 n-side electrode E101 n-side ohmic electrode E102 n-side electrode Pad E200 p-side electrode E201 p-side ohmic electrode E202 p-side electrode pad G100 element isolation trench R100 dielectric reflection film

Claims (8)

(I) a first step of preparing an epi wafer having a substrate which is an n-type conductive m-plane GaN substrate and an epi layer made of a GaN-based semiconductor epitaxially grown on the substrate and including a pn junction type light emitting structure; ,
(Ii) a second step of polishing the back surface of the substrate included in the epi-wafer;
(Iii) a third step of forming an n-side ohmic electrode over the entire back surface of the substrate polished in the second step;
(Iv) a fourth step of patterning the n-side ohmic electrode formed in the third step by etching;
The manufacturing method of the GaN-type light emitting diode which has this. The manufacturing method according to claim 1, further comprising a fifth step of roughly processing the back surface of the substrate exposed in the fourth step. The manufacturing method according to claim 2, wherein in the fifth step, an uneven pattern having periodicity is formed on the back surface of the substrate exposed in the fourth step. The n-side ohmic electrode is a polycrystalline transparent conductive oxide film, and in the fourth step, a part of the n-side ohmic electrode is etched so that the residue remains on the substrate, The manufacturing method according to claim 2, wherein in step 5, the exposed back surface of the substrate is roughly processed by dry etching using the residue as an etching mask. The manufacturing method according to claim 1, further comprising a sixth step of forming a reflective film on the back surface of the substrate exposed in the fourth step. The manufacturing method according to claim 5, wherein the reflective film is a dielectric reflective film. The manufacturing method according to claim 1, wherein the back surface of the substrate to be polished in the second step is lapped immediately before the second step. The manufacturing method as described in any one of Claims 1-7 whose carrier concentration of the said board | substrate is 10 ^{< 17} > cm ^<-3 >.