JP2013062542A - SURFACE TREATMENT METHOD OF m-SURFACE GaN SUBSTRATE - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a surface treatment method of an m-surface GaN substrate.SOLUTION: A surface treatment method of an m-surface GaN substrate includes: a first step of polishing a surface of the m-surface GaN substrate at a polishing rate of 0.5 μm/h or lower using an acid CMP slurry; and a second step of washing the surface of the m-surface GaN substrate following the first step.

Description

The present invention relates to a surface treatment method for an m-plane GaN substrate.

As a light-emitting diode element, there is a GaN-based light-emitting diode element having a light-emitting structure formed using a GaN-based semiconductor. A GaN-based semiconductor is a compound semiconductor represented by the general formula Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1), and is a nitride semiconductor. It is also called a nitride compound semiconductor.
Semiconductor light emitting devices having a double hetero pn junction type light emitting structure formed using a GaN-based semiconductor on an m-plane GaN substrate are known (Non-Patent Documents 1 to 4).

  Non-Patent Documents 1 to 3 disclose light-emitting diode elements. In any element, an n-side ohmic electrode is formed on an n-type Si-doped GaN layer formed by epitaxial growth on an m-plane GaN substrate. Is formed. Non-Patent Document 4 discloses a laser diode element in which an n-side ohmic electrode is formed on the back surface of an m-plane GaN substrate. The threshold current of this laser diode element is 36 mA at the time of CW driving, 28 mA at the time of pulse driving, and the threshold voltage is about 7 to 8V.

  In a light emitting device having a light emitting structure formed on a GaN substrate, it is said that it is difficult to form a good n-side ohmic electrode on the back surface of the GaN substrate (Patent Documents 1 to 6). Therefore, in the method described in Patent Document 2, the contact resistance of the n-side ohmic electrode formed on the back surface is reduced by polishing the back surface of the GaN substrate with a polishing agent having a particle diameter of 10 μm or more. It has been. In the method described in Patent Document 3, for the same purpose, the back surface of the GaN substrate is roughened by wet etching or dry etching. On the other hand, according to Patent Document 4, a damaged layer is formed when the back surface is ground, lapped or polished in order to reduce the thickness of the GaN substrate, which inhibits the formation of a good ohmic electrode. . Therefore, in the method described in Patent Document 4, the back surface of the polished GaN substrate is shaved by dry etching or wet etching. However, Patent Document 5 describes that this purpose cannot be achieved by wet etching. In the method described in Patent Document 6, the contact resistance between the GaN substrate and the n-side ohmic electrode is reduced by dry-etching the back surface of the GaN substrate and scraping off the portion containing crystal defects generated by mechanical polishing. It has been. In addition, the knowledge and invention described in these Patent Documents 1 to 6 basically relate to a c-plane GaN substrate.

JP-A-11-340571 JP 2002-16312 A JP 2004-71657 A JP 2003-51614 A JP 2003-347660 A Japanese Patent Laid-Open No. 2004-6718

Kuniyoshi Okamoto et al., Japanese Journal of Applied Physics, Vol. 45, No. 45, 2006, pp. L1197-L1199 Mathew C. Schmidt et al., Japanese Journal of Applied Physics, Vol. 46, No. 7, 2007, pp. L126-L128 Shih-Pang Chang et al., JournalofThe Electrochemical Society, 157 (5) H501-H503 (2010) Kuniyoshi Okamoto et al., Japanese Journal of Applied Physics, Vol. 46, No. 9, 2007, pp. L187-L189

  A GaN-based light-emitting diode element in which a light-emitting structure is formed on an m-plane GaN substrate does not produce a QCSE effect, so it is suitable for an excitation light source for white LEDs that require a small variation in emission wavelength with an increase in applied current ing. However, if the heat generation amount of the light emitting diode element is large or its heat dissipation is not good, the temperature of the phosphor largely fluctuates due to the heat emitted by the light emitting diode element, and the expected effect cannot be obtained. . Further, a light emitting diode element having a large amount of heat generation and poor heat dissipation has a low luminous efficiency because its own temperature greatly increases as the applied current is increased.

The present invention provides a surface treatment method for an m-plane GaN substrate.

A surface treatment method for an m-plane GaN substrate according to an embodiment of the present invention includes a first step of polishing the surface of an m-plane GaN substrate at a polishing rate of 0.5 μm / h or less using an acidic CMP slurry, Following the first step, a second step of washing the surface of the m-plane GaN substrate with water.

  According to the present invention, a surface treatment method for an m-plane GaN substrate is provided.

It is a schematic diagram which shows the structure of the GaN-type light emitting diode element which the present inventors made as an experiment, FIG. 1 (a) is a top view, FIG.1 (b) is a cross section in the position of the XX line of FIG. FIG. It is a top view of a mask pattern. It is a top view for demonstrating the direction of a mask pattern. It is a SEM image of the back surface of the m-plane GaN substrate which gave processing e.

Since the GaN-based light emitting diode device according to each of the following embodiments has the n-side ohmic electrode formed on the back surface of the m-plane GaN substrate, it can be fixed on the metal electrode using solder. That is, it can be mounted in a form with good heat dissipation. In addition, since the GaN-based light emitting diode elements according to the above embodiments have a low forward voltage, the amount of heat generated is small. Therefore, it is extremely suitable as an excitation light source for white LEDs.
The results of trial manufacture and evaluation of a GaN-based light emitting diode element (hereinafter also referred to as “LED element”) by the present inventors are described below.
1. Basic Structure of Prototype LED Element FIG. 1 schematically shows the basic structure of the prototype LED element. 1A is a top view, and FIG. 1B is a cross-sectional view taken along the line XX in FIG. 1A. As shown to Fig.1 (a), the planar shape of the LED element 1 is a rectangle, and a size is 350 micrometers x 340 micrometers.

As shown in FIG. 1B, the LED element 1 has a semiconductor stacked body 20 made of a GaN-based semiconductor on a substrate 10. The substrate 10 is an m-plane GaN substrate, and the semiconductor stacked body 20 is disposed on the front surface 11 of the substrate 10. The semiconductor stacked body 20 includes, in order from the substrate 10 side, a first undoped GaN layer 21, a Si-doped n-type GaN contact layer 22, a second undoped GaN layer 23, a Si-doped n-type GaN cladding layer 24, an MQW. An active layer 25, a Mg-doped p-type Al _0.1 Ga _0.9 N clad layer 26, and an Mg-doped p-type Al _0.03 Ga _0.97 N contact layer 27 are provided.

The MQW active layer 25 has undoped In _0.04 Ga _0.96 N barrier layers and undoped In _0.16 Ga _0.84 N well layers that are alternately stacked. The number of undoped InGaN barrier layers is four, and the number of undoped InGaN well layers is three. Therefore, the lowermost layer and the uppermost layer of the MQW active layer 25 are both barrier layers. The composition of the well layer is adjusted so that the emission peak wavelength falls within the range of 445 to 465 nm.

  The LED element 1 has two n-side electrodes and one p-side electrode. One of the n-side electrodes is a first n-side metal pad E11, which is provided so as to cover the entire back surface 12 of the substrate 10. The other is the second n-side metal pad E12, which is formed on the surface of the n-type GaN contact layer 22 exposed by partially removing the semiconductor stacked body 20. Both the first n-side metal pad E11 and the second n-side metal pad E12 also serve as ohmic electrodes. The p-side electrode is composed of an ohmic translucent electrode E21 formed on the upper surface of the p-type AlGaN contact layer 27 and a p-side metal pad E22 formed on a part of the translucent electrode E21. It is. The current application to the MQW active layer 25 can be performed through the first n-side metal pad E11 and the p-side metal pad E22, or can be performed through the second n-side metal pad E12 and the p-side metal pad E22. .

The first n-side metal pad E11 is a multilayer film, and includes a TiW layer, an Au layer, a Pt layer, an Au layer, a Pt layer, an Au layer, a Pt layer, and an Au layer in order from the substrate 10 side. The second n-side metal pad E12 is also a multilayer film having a similar laminated structure, and in order from the n-type GaN contact layer 22 side, a TiW layer, an Au layer, a Pt layer, an Au layer, a Pt layer, an Au layer, a Pt layer, It has an Au layer. The translucent electrode E21 is an ITO (indium tin oxide) film. The p-side metal pad E12 is a multilayer film having a laminated structure similar to that of the first n-side metal pad E11 and the second n-side metal pad E12, and sequentially includes a TiW layer, an Au layer, and Pt from the translucent electrode E21 side. A layer, an Au layer, a Pt layer, an Au layer, a Pt layer, and an Au layer.
2. Prototyping of LED Element An LED element 1 was produced by the following procedure.
2-1. Epitaxial growth Size is 7 mm (c-axis direction) x 15 mm (a-axis direction) x 330 μm (thickness), and the off-angle of the front surface (main surface on which the semiconductor laminate is provided) is 0 ± 0.5 ° The n-type conductive m-plane GaN substrate to which Si was added as an n-type impurity was prepared. The carrier concentration of the m-plane GaN substrate examined by hole measurement was 1.3 × 10 ¹⁷ cm ⁻³ .

A plurality of GaN-based semiconductor layers were epitaxially grown on the front surface of the m-plane GaN substrate using the atmospheric pressure MOVPE method to form a semiconductor laminate. TMG (trimethylgallium), TMI (trimethylindium) and TMA (trimethylaluminum) for Group III materials, ammonia for Group V materials, silane for Si materials, bisethylcyclopentadienylmagnesium ((EtCp) for Mg materials ) ₂ Mg) was used.

  Table 1 shows the growth temperature and film thickness of each layer.

  Table 2 shows the concentration of impurities added to the n-type GaN contact layer, n-type GaN clad layer, p-type AlGaN clad layer, and p-type AlGaN contact layer.

The activation of Mg added to the p-type AlGaN cladding layer and the p-type AlGaN contact layer is performed while the p-type AlGaN contact layer is grown for a predetermined time and then the substrate temperature is lowered to room temperature in the growth furnace of the MOVPE apparatus. This was carried out using a method for controlling the flow rates of nitrogen gas and ammonia gas flowing into the growth furnace.
2-2. Formation of p-side electrode and second n-side metal pad An ITO film having a thickness of 210 nm was formed on the surface of the semiconductor laminate formed by the epitaxial growth (surface of the p-type AlGaN contact layer) by electron beam evaporation. Subsequently, the ITO film was patterned into a predetermined shape using photolithography and etching techniques to form a translucent electrode. After patterning, a part of the semiconductor stacked body is removed by reactive ion etching (RIE) processing to expose the n-type GaN contact layer at the site where the second n-side metal pad is to be formed, and perform mesa formation. It was. In RIE processing, Cl ₂ was used as an etching gas, the antenna / bias was set to 100 W / 20 W, and the pressure in the chamber was set to 0.3 Pa.

  Subsequent to the RIE process, the produced ITO film was heat-treated at 520 ° C. for 20 minutes in the air atmosphere. Further, using an RTA (Rapid Thermal Annealing) apparatus, this ITO film was heat-treated at 500 ° C. for 1 minute in a nitrogen gas atmosphere.

After the heat treatment of the ITO film, a second n-side metal pad and a p-side metal pad were simultaneously formed in a predetermined pattern using a lift-off method. All layers (TiW layer, Au layer, and Pt layer) included in the metal multilayer film constituting the second n-side metal pad and the p-side metal pad were formed by sputtering. When forming a TiW film, a Ti-W target having a Ti content of 10 wt% is used as a target, Ar (argon) is used as a sputtering gas, sputtering conditions are RF power 800 W, Ar flow rate 50 sccm, sputtering gas pressure 2.2. × 10 ⁻¹ Pa. The thickness of the lowermost TiW layer and the Au layer laminated immediately above it was 108 nm, and the thicknesses of the other Pt layers and Au layers were all 89 nm.

After forming the second n-side metal pad and the p-side metal pad, a passivation film made of SiO ₂ was formed to a thickness of 230 nm on the exposed surface of the semiconductor stacked body and the surface of the translucent electrode.
2-3. Processing of the back surface of the m-plane GaN substrate After the formation of the passivation film, six different processes described below as processing a to processing f were performed on the back surface of the m-plane GaN substrate.

  Process a: The thickness of the substrate was reduced to 200 μm by lapping and polishing the back surface of the m-plane GaN substrate in this order.

  In the lapping process, the grain size of the diamond abrasive used was gradually reduced in accordance with a conventional method.

  In the polishing step, a CMP slurry in which acid is added to acidic colloidal silica (particle size 70-100 nm) and the pH is adjusted to less than 2 is used, and the load is adjusted so that the polishing rate is 0.5 μm / h. The processing time was about 14 hours. The surface of the m-plane GaN substrate polished under these conditions has an arithmetic average roughness Ra in the range of 10 μm square measured using AFM (for example, DIMENSION 5000 manufactured by DIGITALINSTRUMENTS) of 0.1 nm or less.

  The polished surface (the back surface of the m-plane GaN substrate) is washed with water, further washed with IPA and acetone at room temperature, and then dried with ultraviolet ozone cleaning (110 ° C., oxygen flow rate 5 L / min) for 5 minutes. gave.

  Process b: After process a, the surface layer portion was further removed from the back surface of the m-plane GaN substrate by RIE. The RIE condition is the above 2-2. The etching time was set to 60 seconds so that the etching depth was 0.1 μm under the same conditions as when the RIE processing was performed on the semiconductor laminate. When the roughness of the surface after RIE processing was measured with a stylus type step gauge (ET3000 manufactured by Kosaka Laboratory Ltd.), the arithmetic average roughness Ra was 0.02 μm, and the maximum height Rz was 0.04 μm.

  Processing c: After processing a, the surface layer portion was further scraped off from the back surface of the m-plane GaN substrate by RIE. The RIE condition is the above 2-2. The etching time was set to 610 seconds so that the etching depth was 1.0 μm under the same conditions as when the semiconductor laminate was subjected to RIE processing. When the surface roughness after RIE processing was measured with a stylus profilometer, the arithmetic average roughness Ra was 0.06 μm, and the maximum height Rz was 0.55 μm.

  Processing d: After processing a, the surface layer portion was further scraped off from the back surface of the m-plane GaN substrate by RIE. The RIE condition is the above 2-2. The etching time was set to 1220 seconds so that the etching conditions were the same as those when the RIE processing was performed on the semiconductor laminate. When the surface roughness after RIE processing was measured with a stylus profilometer, the arithmetic average roughness Ra was 0.07 to 0.12 μm, and the maximum height Rz was 1.30 μm.

  Process e: A positive photoresist (Sumiresist PFI-34AL manufactured by Sumitomo Chemical Co., Ltd.) using a novolac resin is coated on the back surface of the m-plane GaN substrate after the process a to a thickness of 1.6 μm. The mask pattern shown in FIG. 2 was formed by patterning the photoresist using a photolithography technique. That is, it is a mask pattern in which a plurality of circular etching masks are arranged at the lattice positions of a triangular lattice. The diameter of each circular mask (R in FIG. 2) was 2 μm, and the space between adjacent circular masks (S in FIG. 2) was 2.5 μm. As shown in FIG. 3, the direction of the mask pattern was determined so that the two sides BC and EF of the regular hexagon ABCDEF having the six lattice positions of the triangular lattice as vertices were orthogonal to the c-axis of the m-plane GaN substrate. .

The back surface of the m-plane GaN substrate was processed into a concavo-convex shape by performing RIE using the mask pattern formed as described above as an etching mask. Cl ₂ was used as an etching gas, the antenna / bias was set to 100 W / 20 W, the pressure in the chamber was set to 0.3 Pa, and the etching selectivity was about 1. The etching selectivity here is [GaN etching rate] / [mask etching rate] when the etching time is about 800 seconds or less. Under these conditions, RIE processing was performed for 1500 seconds. The mask pattern almost disappeared when the etching time reached about 800 seconds. After the RIE processing, the wafer was cleaned using an organic solvent, and then the surface subjected to the RIE processing was subjected to ultraviolet ozone cleaning (110 ° C., oxygen flow rate 5 L / min) for 5 minutes.

  FIG. 4 shows an SEM image of the back surface of the m-plane GaN substrate subjected to the processing e. 4A is a plan view, FIG. 4B is a diagram viewed from the cross-sectional direction, and FIG. 4C is a perspective view. 4A to 4C, the direction from right to left in the drawing is the [0001] direction (c + direction) of GaN, and the direction from left to right is [000-1] of GaN. ] Direction (c-direction). The height of the protrusion formed on the back surface of the m-plane GaN substrate was 1.5 μm.

Processing f: A mask pattern was formed on the back surface of the m-plane GaN substrate after processing a by the same procedure as processing e, but after installing in the RIE chamber, the back surface of the m-plane GaN substrate was covered with a thin sapphire plate. By covering, the back surface was protected from being subjected to RIE processing. Except for this, the process performed in process f is the same as process e. That is, on the back surface of the m-plane GaN substrate subjected to processing f, a process of forming a mask pattern using a photoresist, a process of removing the mask pattern using an organic solvent, and an ultraviolet ozone after removing the mask pattern A cleaning process is being performed.
2-4. Formation of first n-side metal pad A metal multilayer film serving as a first n-side metal pad was formed on the back surface of the m-plane GaN substrate subjected to any of the above processes a to f. All layers (TiW layer, Au layer, and Pt layer) included in this metal multilayer film were formed by sputtering. When forming a TiW film, a Ti-W target having a Ti content of 10 wt% is used as a target, Ar (argon) is used as a sputtering gas, sputtering conditions are RF power 800 W, Ar flow rate 50 sccm, sputtering gas pressure 2.2. × 10 ⁻¹ Pa. The thickness of the lowermost TiW layer and the Au layer laminated immediately above it was 108 nm, and the thicknesses of the other Pt layers and Au layers were all 89 nm.

After the metal multilayer film was formed, the wafer was divided by scribing and breaking to form LED elements as chips. The metal multilayer film was cut together with the GaN substrate in this step. Therefore, the planar shape of the first n-side metal pad is the same as the shape of the back surface of the m-plane GaN substrate. The size of the first n-side metal pad was 350 μm × 340 μm, which was substantially the same as the chip size.
2-5. Evaluation of forward voltage Forward voltage (Vf ₁ ) when current is applied through the first n-side metal pad and p-side metal pad to the LED chip obtained by the above procedure, and the second n-side The forward voltage (Vf ₂ ) when current was applied through the metal pad and the p-side metal pad was compared. The applied current was a pulse current having a pulse width of 1 msec and a pulse period of 1 msec, and the current values were two types of 20 mA and 60 mA. The results are shown in Table 3.

As shown in Table 3, Vf ₁ and Vf ₂ coincided with the LED chip in which only the processing a was performed on the back surface of the m-plane GaN substrate, whereas Vf ₁ was all in the LED chips subjected to processing b to f. It becomes larger than the vf _2. In particular, the difference between the LED chips subjected to processing b to e including RIE processing was several V or more.

Further, Vf ₁ when forward current of 20 mA, 60 mA, 100 mA, 120 mA, 180 mA, 240 mA and 350 mA is applied to an LED chip in which only the processing a is performed on the back surface of the m-plane GaN substrate with a pulse width of 1 msec and a pulse period of 1 msec. Is shown in Table 4. In addition to that, Table 4 shows the average current density in the first n-side metal pad. This average current density is a value obtained by dividing the forward current by the area of the n-side metal pad (350 μm × 340 μm), and is an average of the current flowing across the interface between the n-side metal pad and the back surface of the m-plane GaN substrate. Represents density.

  The present invention has been completed based on the knowledge obtained from the trial manufacture and evaluation of the LED elements described above. However, it goes without saying that the present invention is not limited to a prototype LED element or a method used in the trial production.

The matters disclosed in this specification include the semiconductor light-emitting elements described below.
(1) An n-type conductive m-plane GaN substrate, a light emitting structure formed using a GaN-based semiconductor on the front surface of the m-plane GaN substrate, and formed on the back surface of the m-plane GaN substrate A semiconductor light emitting device having an n-side ohmic electrode and having a forward voltage of 4.0 V or less when a forward current applied to the device is 20 mA.
(2) An n-type conductive m-plane GaN substrate, a light emitting structure formed using a GaN-based semiconductor on the front surface of the m-plane GaN substrate, and formed on the back surface of the m-plane GaN substrate A semiconductor light emitting device having an n-side ohmic electrode and having a forward voltage of 4.5 V or less when a forward current applied to the device is 60 mA.
(3) An n-type conductive m-plane GaN substrate, a light emitting structure formed using a GaN-based semiconductor on the front surface of the m-plane GaN substrate, and formed on the back surface of the m-plane GaN substrate A semiconductor light emitting device having an n-side ohmic electrode and having a forward voltage of 5.0 V or less when a forward current applied to the device is 120 mA.
(4) An n-type conductive m-plane GaN substrate, a light emitting structure formed using a GaN-based semiconductor on the front surface of the m-plane GaN substrate, and formed on the back surface of the m-plane GaN substrate A semiconductor light emitting device having an n-side ohmic electrode and having a forward voltage of 5.5 V or less when a forward current applied to the device is 200 mA.
(5) An n-type conductive m-plane GaN substrate, a light emitting structure formed using a GaN-based semiconductor on the front surface of the m-plane GaN substrate, and formed on the back surface of the m-plane GaN substrate A semiconductor light emitting device having an n-side ohmic electrode and having a forward voltage of 6.0 V or less when a forward current applied to the device is 350 mA.
(6) The light emitting structure includes an active layer made of a GaN-based semiconductor, an n-type GaN-based semiconductor layer disposed between the active layer and the m-plane GaN substrate, and the n-type GaN-based semiconductor layer. A semiconductor light emitting device according to any one of (1) to (5), comprising a p-type GaN-based semiconductor layer sandwiching the active layer.
(7) The semiconductor light-emitting device according to any one of (1) to (6), which is a light-emitting diode device.
(8) The semiconductor light emitting element according to any one of (1) to (7), wherein an area of the back surface of the m-plane GaN substrate is 0.0012 cm ² or more.
(9) The semiconductor light emitting element according to (8), wherein an area of the n-side ohmic electrode is 0.0012 cm ² or more and not more than an area of the back surface of the m-plane GaN substrate.
(10) The semiconductor light emitting element according to any one of (1) to (11), wherein the m-plane GaN substrate has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ .

Moreover, those skilled in the art will understand that the surface treatment method of the m-plane GaN substrate or the manufacturing method of the semiconductor element described below is disclosed in this specification.
(A1) A first step of polishing the surface of the m-plane GaN substrate using an acidic CMP slurry at a polishing rate of 0.5 μm / h or less, and the surface of the m-plane GaN substrate following the first step And a second step of washing the surface with water.
(A2) The surface treatment method according to (a1), wherein the pH of the CMP slurry is less than 2.
(A3) The surface treatment method according to (a1) or (a2), wherein in the first step, the surface of the m-plane GaN substrate is polished so that the arithmetic average roughness Ra after polishing is 0.1 nm or less. .
(A4) An electrode forming step of forming an ohmic electrode on the surface of an n-type GaN substrate having n-type conductivity, and before the electrode step, the surface finishing steps (a1) to (a3) The manufacturing method of a semiconductor element which has a surface treatment process which performs the surface treatment using the surface treatment method in any one on this surface.
(A5) The method for manufacturing a semiconductor element, wherein the m-plane GaN substrate having n-type conductivity has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ .

Claims (1)

A first step of polishing the surface of the m-plane GaN substrate using an acidic CMP slurry at a polishing rate of 0.5 μm / h or less, and subsequent to the first step, the surface of the m-plane GaN substrate is washed with water. A surface treatment method for an m-plane GaN substrate, comprising: a second step.