JP2000277649A - Semiconductor and manufacture of the same - Google Patents
Semiconductor and manufacture of the sameInfo
- Publication number
- JP2000277649A JP2000277649A JP11083895A JP8389599A JP2000277649A JP 2000277649 A JP2000277649 A JP 2000277649A JP 11083895 A JP11083895 A JP 11083895A JP 8389599 A JP8389599 A JP 8389599A JP 2000277649 A JP2000277649 A JP 2000277649A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- solder
- bump
- substrate
- metal pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電気・電子機器等
に使用される半導体装置及びその製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for electric / electronic equipment and the like and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】半導体装置の高機能化に伴い、母基板に
実装するための外部端子の数は増大する傾向にある。そ
のため、半導体装置の１つの面にボール状の端子を格子
状に形成した、ボールグリッドアレイ（ＢＧＡ）半導体
装置と呼ばれる半導体装置が検討されている。2. Description of the Related Art As semiconductor devices become more sophisticated, the number of external terminals mounted on a motherboard tends to increase. Therefore, a semiconductor device called a ball grid array (BGA) semiconductor device in which ball-shaped terminals are formed in a grid on one surface of the semiconductor device has been studied.
【０００３】この半導体装置は、図５に示すように、配
線回路を有する基板１上に半導体チップ２が搭載される
と共に、その半導体チップ２と基板１がボンディングワ
イヤー３で電気的に接続されており、その基板１の半導
体チップ２を搭載した部分は、封止材４で封止されてい
る。また、基板１の表面には、半導体チップ２と電気的
に接続された複数のバンプ用電極５が形成されており、
そのバンプ用電極５にハンダバンプ６が接続されてい
る。そして、この半導体装置を母基板に実装するときに
は、ハンダバンプ６が溶融して、半導体装置と母基板の
電気的な接続を行うようになっている。なお、バンプ用
電極５の周囲には、ソルダーレジスト等を塗布すること
によって絶縁層７が形成されており、ハンダバンプ６が
溶融した際に、隣合うハンダバンプ６，６が接続しない
ようになっている。In this semiconductor device, as shown in FIG. 5, a semiconductor chip 2 is mounted on a substrate 1 having a wiring circuit, and the semiconductor chip 2 and the substrate 1 are electrically connected by bonding wires 3. The portion of the substrate 1 on which the semiconductor chip 2 is mounted is sealed with a sealing material 4. A plurality of bump electrodes 5 electrically connected to the semiconductor chip 2 are formed on the surface of the substrate 1.
The solder bump 6 is connected to the bump electrode 5. When the semiconductor device is mounted on the motherboard, the solder bumps 6 are melted, and the semiconductor device and the motherboard are electrically connected. An insulating layer 7 is formed around the bump electrode 5 by applying a solder resist or the like, so that when the solder bump 6 is melted, the adjacent solder bumps 6, 6 are not connected. .
【０００４】上記バンプ用電極５にハンダバンプ６を形
成する方法としては、予め球状に形成したハンダボール
をバンプ用電極５に接合する方法や、その周囲に絶縁層
７が形成されたバンプ用電極５を有する基板１上に、印
刷等によってハンダペーストを供給した後、加熱するこ
とにより、ハンダペーストをバンプ用電極５の部分で球
状に凝集させてハンダバンプ６を形成する方法が行われ
ている。As a method of forming the solder bump 6 on the bump electrode 5, there is a method of joining a solder ball formed in advance in a spherical shape to the bump electrode 5, or a method of forming the bump electrode 5 having an insulating layer 7 formed therearound. A method of supplying a solder paste by printing or the like onto the substrate 1 having the above-described method, and then heating the solder paste so that the solder paste is aggregated into a spherical shape at the bump electrode 5 to form the solder bump 6 is performed.
【０００５】しかし、この半導体装置は、バンプ用電極
５にハンダバンプ６を形成する際に、ハンダバンプ６の
内部に亀裂が発生する場合があり、電気的信頼性が低い
という問題があった。そのため、ハンダバンプの内部に
亀裂が少なく、信頼性の高い半導体装置が求められてい
る。However, in this semiconductor device, when the solder bumps 6 are formed on the bump electrodes 5, cracks may be generated inside the solder bumps 6, and there is a problem that the electrical reliability is low. Therefore, there is a demand for a highly reliable semiconductor device having few cracks inside the solder bump.
【０００６】[0006]
【発明が解決しようとする課題】本発明は、上記問題点
を改善するために成されたもので、その目的とするとこ
ろは、母基板に実装するためのハンダバンプを設けた半
導体装置であって、ハンダバンプの内部に亀裂が少ない
半導体装置を提供することにある。また、ハンダバンプ
の内部に亀裂が発生しにくい、半導体装置の製造方法を
提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device provided with solder bumps for mounting on a motherboard. It is another object of the present invention to provide a semiconductor device having less cracks inside solder bumps. Another object of the present invention is to provide a method for manufacturing a semiconductor device, in which a crack is not easily generated inside a solder bump.
【０００７】[0007]
【課題を解決するための手段】本発明に係る半導体装置
は、その周囲に絶縁層が形成されたバンプ用電極を有す
る基板上に半導体チップを搭載すると共に、母基板に実
装するための複数のハンダバンプをバンプ用電極と電気
的に接続して設けた半導体装置において、バンプ用電極
とハンダバンプとの間に、絶縁層より厚み方向に突出す
る厚みの金属パッドを備え、その金属パッドを介してハ
ンダバンプとバンプ用電極とが電気的に接続しているこ
とを特徴とする。SUMMARY OF THE INVENTION A semiconductor device according to the present invention has a plurality of semiconductor chips mounted on a substrate having a bump electrode having an insulating layer formed therearound and a plurality of semiconductor chips mounted on a mother substrate. In a semiconductor device in which a solder bump is electrically connected to a bump electrode, a metal pad having a thickness protruding in a thickness direction from an insulating layer is provided between the bump electrode and the solder bump, and the solder bump is provided via the metal pad. And the bump electrodes are electrically connected.
【０００８】上記金属パッドは、金属メッキにより形成
されてなると好ましく、特に銅メッキや、ハンダメッキ
により形成されてなると好ましい。The metal pad is preferably formed by metal plating, particularly preferably formed by copper plating or solder plating.
【０００９】本発明に係る半導体装置の製造方法は、そ
の周囲に絶縁層が形成されたバンプ用電極を有する基板
上に半導体チップを搭載すると共に、母基板に実装する
ための複数のハンダバンプをバンプ用電極と電気的に接
続して製造する半導体装置の製造方法において、ハンダ
バンプをバンプ用電極と電気的に接続する方法が、バン
プ用電極の表面に接して絶縁層より厚み方向に突出する
厚みの金属パッドを設けた後、その金属パッドに接する
ようにハンダバンプを設ける方法であることを特徴とす
る。According to a method of manufacturing a semiconductor device according to the present invention, a semiconductor chip is mounted on a substrate having a bump electrode having an insulating layer formed therearound, and a plurality of solder bumps for mounting on a mother substrate are formed by bumping. In the method of manufacturing a semiconductor device which is electrically connected to the bump electrode, the method of electrically connecting the solder bump to the bump electrode is performed by a method of contacting the surface of the bump electrode with a thickness protruding from the insulating layer in the thickness direction. The method is characterized in that after a metal pad is provided, a solder bump is provided so as to be in contact with the metal pad.
【００１０】[0010]
【発明の実施の形態】本発明に係る半導体装置を図面に
基づいて説明する。図１は本発明に係る半導体装置の一
実施の形態を説明する断面図である。また、図２は本発
明に係る半導体装置の製造方法の、一実施の形態を説明
する断面図であり、図３は本発明に係る半導体装置の製
造方法の、他の実施の形態を説明する断面図である。ま
た、図４は半導体装置を破断して示した要部拡大図であ
り、（ａ）は本発明に係る半導体装置を示し、（ｂ）は
従来の半導体装置を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device according to the present invention. FIG. 2 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device according to the present invention. FIG. 3 illustrates another embodiment of a method for manufacturing a semiconductor device according to the present invention. It is sectional drawing. 4 is an enlarged view of a main part of the semiconductor device, in which the semiconductor device is cut away. FIG. 4A shows a semiconductor device according to the present invention, and FIG. 4B shows a conventional semiconductor device.
【００１１】本発明に係る半導体装置の一実施の形態
は、図１に示すような、配線回路を有する基板１上に半
導体チップ２が搭載されると共に、その半導体チップ２
と基板１がボンディングワイヤー３で電気的に接続され
ており、その基板１の半導体チップ２を搭載した部分
は、封止材４で封止されている半導体装置である。ま
た、基板１の表面には、半導体チップ２と電気的に接続
された複数のバンプ用電極５が形成されており、そのバ
ンプ用電極５の周囲には、絶縁層７が形成されている。In one embodiment of the semiconductor device according to the present invention, a semiconductor chip 2 is mounted on a substrate 1 having a wiring circuit as shown in FIG.
And the substrate 1 are electrically connected by bonding wires 3, and a portion of the substrate 1 on which the semiconductor chip 2 is mounted is a semiconductor device sealed with a sealing material 4. A plurality of bump electrodes 5 electrically connected to the semiconductor chip 2 are formed on the surface of the substrate 1, and an insulating layer 7 is formed around the bump electrodes 5.
【００１２】バンプ用電極５は、配線回路を介して半導
体チップ２と電気的に接続されており、更にバンプ用電
極５には、ハンダバンプ６が接続されている。そして、
この半導体装置を母基板に実装するときには、ハンダバ
ンプ６が溶融して、半導体装置と母基板の電気的な接続
を行うようになっている。なお、バンプ用電極５の周囲
には絶縁層７が形成されているため、ハンダバンプ６が
溶融した際に、隣合うハンダバンプ６が接続しないよう
になっている。The bump electrode 5 is electrically connected to the semiconductor chip 2 via a wiring circuit, and the bump electrode 5 is further connected to a solder bump 6. And
When this semiconductor device is mounted on the motherboard, the solder bumps 6 are melted to make electrical connection between the semiconductor device and the motherboard. Since the insulating layer 7 is formed around the bump electrodes 5, when the solder bumps 6 are melted, the adjacent solder bumps 6 are not connected.
【００１３】そして、バンプ用電極５とハンダバンプ６
との間には、絶縁層７より厚み方向に突出する厚みの金
属パッド８が形成されており、その金属パッド８を介し
てハンダバンプ６とバンプ用電極５とが電気的に接続さ
れている。The bump electrode 5 and the solder bump 6
A metal pad 8 having a thickness protruding from the insulating layer 7 in the thickness direction is formed between the solder bump 6 and the bump electrode 5 via the metal pad 8.
【００１４】この半導体装置は、例えば図２に示すよう
な工程で製造されている。材料として、図２（ａ）に示
すような、その周囲に絶縁層７が形成されたバンプ用電
極５を有する基板１を用いる。そして、バンプ用電極５
の表面に、金属メッキを行ったり、金属片を接合する方
法により、図２（ｂ）に示すように、バンプ用電極５の
表面に金属パッド８を形成する。なおこの際、金属メッ
キを行う方法の場合には、バンプ用電極５の周囲に形成
された絶縁層７の厚みより、メッキ厚が厚くなるように
条件を調整することにより、絶縁層７より厚み方向に突
出する厚みの金属パッド８を形成する。また、金属片を
接合する方法の場合には、バンプ用電極５の周囲に形成
された絶縁層７の厚みより、厚みが厚い金属片を選択し
て接合することにより、絶縁層７より厚み方向に突出す
る厚みの金属パッド８を形成する。This semiconductor device is manufactured, for example, by the steps shown in FIG. As a material, a substrate 1 having a bump electrode 5 around which an insulating layer 7 is formed as shown in FIG. 2A is used. And the bump electrode 5
As shown in FIG. 2B, a metal pad 8 is formed on the surface of the bump electrode 5 by a method of performing metal plating or bonding a metal piece on the surface of the bump electrode 5. At this time, in the case of the method of performing metal plating, the thickness is adjusted to be larger than the thickness of the insulating layer 7 formed around the bump electrode 5 by adjusting the conditions so that the plating thickness is larger. A metal pad 8 having a thickness protruding in the direction is formed. In the case of a method of joining metal pieces, a metal piece having a thickness greater than the thickness of the insulating layer 7 formed around the bump electrode 5 is selected and joined, so that the metal layer is more thicker than the insulating layer 7 in the thickness direction. A metal pad 8 having a thickness protruding from the substrate is formed.
【００１５】なお、金属メッキで金属パッド８を形成す
る方法の場合、一度に多数のバンプ用電極５の表面に金
属パッド８を形成することが可能なため、生産性が優れ
好ましく、金属片を接合する方法の場合、厚みが厚い金
属片を選択することにより、金属パッド８を確実に絶縁
層７より厚み方向に突出して形成でき好ましい。In the case of forming the metal pads 8 by metal plating, the metal pads 8 can be formed on the surfaces of a large number of bump electrodes 5 at one time. In the case of the joining method, it is preferable to select a metal piece having a large thickness, so that the metal pad 8 can be reliably formed to protrude from the insulating layer 7 in the thickness direction.
【００１６】金属パッド８が、絶縁層７より厚み方向に
突出する、その突起量としては、１００μｍ以下が好ま
しい。１００μｍを超える場合、実装に有効なハンダバ
ンプ６のサイズが小さくなるため、反った半導体装置を
母基板に実装する場合や、半導体装置を反った母基板に
実装する場合に、母基板と接続しないハンダバンプ６が
生じる場合が有る。The metal pad 8 projects from the insulating layer 7 in the thickness direction. The amount of projection is preferably 100 μm or less. If the thickness exceeds 100 μm, the size of the solder bump 6 effective for mounting becomes small. Therefore, when mounting the warped semiconductor device on the mother board or mounting the semiconductor device on the warped mother board, the solder bump which is not connected to the mother board is used. 6 may occur.
【００１７】金属パッド８を形成する金属としては、特
に限定するものではないが、ハンダ濡れ性や絶縁層７と
の密着性が優れた金属が好ましい。上記金属メッキとし
て銅メッキを行った場合、得られる金属パッド８の導電
性が優れ好ましく、ハンダメッキを行った場合、ハンダ
バンプ６を形成した際に、金属パッド８とハンダバンプ
６が一体化するため、実装に有効なハンダバンプ６のサ
イズが大きくなり好ましい。また、銅メッキを行って形
成した銅パッドの表面に、ニッケルメッキを行った金属
パッド８の場合、導電性が優れると共に、ハンダ濡れ性
や絶縁層７との密着性が特に優れ好ましい。The metal forming the metal pad 8 is not particularly limited, but a metal having excellent solder wettability and adhesion to the insulating layer 7 is preferable. When the copper plating is performed as the metal plating, the conductivity of the obtained metal pad 8 is excellent and preferable. When the solder plating is performed, the metal pad 8 and the solder bump 6 are integrated when the solder bump 6 is formed. This is preferable because the size of the solder bump 6 effective for mounting is increased. Further, in the case of the metal pad 8 formed by performing nickel plating on the surface of a copper pad formed by performing copper plating, the conductivity is excellent, and the solder wettability and the adhesion to the insulating layer 7 are particularly excellent, and thus are preferable.
【００１８】次いで、図２（ｃ）に示すように、基板１
の表面に半導体チップ２を装着した後、基板１表面の配
線回路と半導体チップ２をボンディングワイヤー３等で
接続し、次いで、半導体チップ２及びその周囲を、エポ
キシ樹脂等の封止材４でコーティングした後、樹脂を硬
化させて封止する。次いで、図２（ｄ）に示すように、
予め球状に形成したハンダボールを金属パッド８に接合
することにより、ハンダバンプ６を形成すると共に、ハ
ンダバンプ６とバンプ用電極５とを電気的に接続して半
導体装置を製造する。Next, as shown in FIG.
After the semiconductor chip 2 is mounted on the surface of the semiconductor chip 2, the wiring circuit on the surface of the substrate 1 is connected to the semiconductor chip 2 with a bonding wire 3 or the like, and then the semiconductor chip 2 and its surroundings are coated with a sealing material 4 such as epoxy resin. After that, the resin is cured and sealed. Then, as shown in FIG.
Solder balls previously formed into a spherical shape are bonded to metal pads 8 to form solder bumps 6 and to electrically connect the solder bumps 6 and the bump electrodes 5 to manufacture a semiconductor device.
【００１９】バンプ用電極５にハンダバンプ６を形成す
る方法としては、図３（ｄ）に示すように、バンプ用電
極５及びその周囲の絶縁層７の表面に、印刷等によって
ハンダペースト６１を供給した後、加熱することによ
り、図３（ｅ）に示すように、ハンダペースト６１をバ
ンプ用電極５の部分で球状に凝集させてハンダバンプ６
を形成するようにしても良い。ハンダボールをバンプ用
電極５に接合する方法の場合、バンプ用電極５の大きさ
がほぼ均一になり好ましく、ハンダペースト６１を供給
して形成する方法の場合、ハンダボールを形成する工程
が不要になるため、コスト的に優れ好ましい。As shown in FIG. 3D, a method for forming the solder bump 6 on the bump electrode 5 is to supply a solder paste 61 to the surface of the bump electrode 5 and the insulating layer 7 around the bump electrode 5 by printing or the like. Then, by heating, as shown in FIG. 3E, the solder paste 61 is aggregated into a spherical shape at the bump electrode 5 to form the solder bump 6.
May be formed. In the case of the method of joining the solder ball to the bump electrode 5, the size of the bump electrode 5 is preferably substantially uniform, and in the case of the method of supplying and forming the solder paste 61, the step of forming the solder ball is unnecessary. Therefore, it is preferable in terms of cost.
【００２０】なお、予め球状に形成したハンダボールを
用いてハンダバンプ６を形成する方法の場合、図４
（ｂ）に示すような、従来の金属パッド８を備えない半
導体装置の場合には、ハンダボールをバンプ用電極５に
接合する際に、ハンダを多少溶融させて、絶縁層７，７
とバンプ用電極５とによって形成される凹部にハンダを
侵入させる必要があるため、その際に絶縁層７の角部で
ハンダバンプ６の内部にストレスが発生し、ハンダバン
プ６の内部に亀裂Ａが発生しやすくなる。In the case of the method of forming solder bumps 6 by using solder balls formed in a spherical shape in advance, FIG.
In the case of a conventional semiconductor device having no metal pad 8 as shown in FIG. 2B, when a solder ball is bonded to the bump electrode 5, the solder is slightly melted to form the insulating layers 7, 7.
It is necessary to cause the solder to penetrate into the concave portion formed by the solder bump 6 and the bump electrode 5. At this time, stress is generated inside the solder bump 6 at the corner of the insulating layer 7, and a crack A is generated inside the solder bump 6. Easier to do.
【００２１】しかし、図４（ａ）に示すような、絶縁層
７より厚み方向に突出する厚みの金属パッド８を備えた
半導体装置の場合、絶縁層７，７とバンプ用電極５との
間に凹部が形成され無いため、ハンダバンプ６の内部に
ストレスが発生しにくく、ハンダバンプ６の内部に亀裂
が発生しにくくなる。However, as shown in FIG. 4A, in the case of a semiconductor device provided with a metal pad 8 having a thickness protruding from the insulating layer 7 in the thickness direction, the distance between the insulating layers 7, 7 and the bump electrode 5 is increased. Since no recess is formed in the solder bump 6, stress is hardly generated inside the solder bump 6, and cracks are hardly generated inside the solder bump 6.
【００２２】また、ハンダペースト６１を供給してハン
ダバンプ６を形成する方法の場合も、図４（ｂ）に示す
ような、従来の金属パッド８を備えない半導体装置の場
合、ハンダペースト６１が球状に凝集する際に、絶縁層
７の角部でハンダバンプ６の内部にストレスが発生し、
ハンダバンプ６の内部に亀裂Ａが発生しやすくなるが、
図４（ａ）に示すような、絶縁層７より厚み方向に突出
する厚みの金属パッド８を備えた半導体装置の場合、絶
縁層７の角部が無いため、ハンダバンプ６の内部にスト
レスが発生しにくく、ハンダバンプの内部に亀裂が発生
しにくくなる。Also, in the case of the method of supplying the solder paste 61 to form the solder bumps 6, in the case of a conventional semiconductor device having no metal pad 8 as shown in FIG. When agglomeration occurs, stress is generated inside the solder bump 6 at the corner of the insulating layer 7,
Although crack A is likely to be generated inside the solder bump 6,
In the case of a semiconductor device having a metal pad 8 having a thickness protruding in the thickness direction from the insulating layer 7 as shown in FIG. 4A, stress is generated inside the solder bump 6 because there is no corner of the insulating layer 7. Cracks are less likely to occur inside the solder bumps.
【００２３】なお、上記の実施の形態の製造方法は、金
属パッド８を形成した後に、基板１に半導体チップ２を
搭載する実施の形態を説明したが、半導体チップ２を搭
載する工程の位置は特に限定するものではなく、金属パ
ッド８を形成する前や、ハンダバンプ６を形成した後で
も良い。In the manufacturing method of the above embodiment, the semiconductor chip 2 is mounted on the substrate 1 after the metal pad 8 is formed. However, the position of the step of mounting the semiconductor chip 2 is as follows. There is no particular limitation, and it may be before forming the metal pad 8 or after forming the solder bump 6.
【００２４】また、本発明に用いられる基板１として
は、その周囲に絶縁層７が形成されたバンプ用電極５を
有する基板１であれば特に限定するものではなく、例え
ば、エポキシ樹脂系、フェノール樹脂系、ポリイミド樹
脂系、不飽和ポリエステル樹脂系、ポリフェニレンエー
テル樹脂系等の熱硬化性樹脂や、これらの熱硬化性樹脂
に無機充填材等を配合したもののシートの片面又は両面
に金属箔が張られている板や、ガラス等の無機質繊維や
ポリエステル、ポリアミド、木綿等の有機質繊維のクロ
ス、ペーパー等の基材を、上記熱硬化性樹脂等で接着
し、片面又は両面に金属箔が張られている板や、セラミ
ック板等の無機系の板を用いて、金属メッキを行った
後、所定の部分をエッチングしてバンプ用電極５等の配
線回路を形成した後、ソルダーレジスト等を塗布するこ
とによって絶縁層７を形成したもの、及び、金属箔が張
られていない板に金属メッキを行い、バンプ用電極５等
の配線回路を形成した後、ソルダーレジスト等を塗布す
ることによって絶縁層７を形成したもの等が挙げられ
る。なお、配線回路を形成する金属としては、電気的信
頼性より銅や、銅の表面に金めっき層を形成したものが
好ましい。The substrate 1 used in the present invention is not particularly limited as long as it is a substrate 1 having a bump electrode 5 around which an insulating layer 7 is formed. A resin-based, polyimide resin-based, unsaturated polyester resin-based, thermosetting resin such as polyphenylene ether resin, or a mixture of these thermosetting resins with an inorganic filler or the like is covered with metal foil on one or both sides of a sheet. Plates, inorganic fibers such as glass, cloth of organic fibers such as polyester, polyamide and cotton, and a substrate such as paper are adhered with the above thermosetting resin or the like, and a metal foil is stretched on one or both surfaces. After performing metal plating by using a metal plate or an inorganic plate such as a ceramic plate, a predetermined portion is etched to form a wiring circuit such as a bump electrode 5 and the like. After forming a wiring circuit such as the bump electrode 5 by applying metal plating to a substrate on which the insulating layer 7 is formed by applying a solder resist or the like and a plate not covered with a metal foil, a solder resist or the like is applied. Then, an insulating layer 7 is formed. As a metal forming the wiring circuit, copper or a metal having a gold plating layer formed on the surface of copper is preferable from the viewpoint of electrical reliability.
【００２５】[0025]
【発明の効果】本発明に係る半導体装置は、バンプ用電
極とハンダバンプとの間に、絶縁層より厚み方向に突出
する厚みの金属パッドを備え、その金属パッドを介して
ハンダバンプとバンプ用電極とが電気的に接続している
ため、ハンダバンプの内部に亀裂が少ない半導体装置と
なる。The semiconductor device according to the present invention has a metal pad between the bump electrode and the solder bump, the metal pad having a thickness protruding from the insulating layer in the thickness direction, and the solder bump and the bump electrode are connected via the metal pad. Are electrically connected to each other, so that the semiconductor device has less cracks inside the solder bumps.
【００２６】本発明の請求項２に係る半導体装置は、上
記の効果に加え、一度に多数のバンプ用電極の表面に金
属パッドを形成することが可能となり、生産性が優れた
半導体装置となる。In the semiconductor device according to the second aspect of the present invention, in addition to the above effects, it is possible to form metal pads on the surfaces of a large number of bump electrodes at a time, resulting in a semiconductor device having excellent productivity. .
【００２７】本発明に係る半導体装置の製造方法は、ハ
ンダバンプをバンプ用電極と電気的に接続する方法が、
バンプ用電極の表面に接して絶縁層より厚み方向に突出
する厚みの金属パッドを設けた後、その金属パッドに接
するようにハンダバンプを設ける方法であるため、ハン
ダバンプの内部に亀裂が発生しにくい半導体装置を得る
ことが可能となる。In the method for manufacturing a semiconductor device according to the present invention, the method for electrically connecting the solder bumps to the bump electrodes includes:
A method in which a metal pad having a thickness protruding in the thickness direction from the insulating layer is provided in contact with the surface of the bump electrode, and then a solder bump is provided so as to be in contact with the metal pad. A device can be obtained.
【図１】本発明に係る半導体装置の一実施の形態を説明
する断面図である。FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device according to the present invention.
【図２】本発明に係る半導体装置の製造方法の、一実施
の形態を説明する断面図である。FIG. 2 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device according to the present invention.
【図３】本発明に係る半導体装置の製造方法の、他の実
施の形態を説明する断面図である。FIG. 3 is a sectional view illustrating another embodiment of the method for manufacturing a semiconductor device according to the present invention.
【図４】半導体装置を破断して示した要部拡大図であ
り、（ａ）は本発明に係る半導体装置を示し、（ｂ）は
従来の半導体装置を示す。FIG. 4 is an enlarged view of a main part of the semiconductor device, in which the semiconductor device is cut away, wherein FIG. 4A shows a semiconductor device according to the present invention, and FIG. 4B shows a conventional semiconductor device.
【図５】従来の半導体装置を説明する断面図である。FIG. 5 is a cross-sectional view illustrating a conventional semiconductor device.
１ 基板 ２ 半導体チップ ３ ボンディングワイヤー ４ 封止材 ５ バンプ用電極 ６ ハンダバンプ ７ 絶縁層 ８ 金属パッド Ａ 亀裂 DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor chip 3 Bonding wire 4 Sealant 5 Bump electrode 6 Solder bump 7 Insulating layer 8 Metal pad A Crack
Claims (5)
電極を有する基板上に半導体チップを搭載すると共に、
母基板に実装するための複数のハンダバンプをバンプ用
電極と電気的に接続して設けた半導体装置において、バ
ンプ用電極とハンダバンプとの間に、絶縁層より厚み方
向に突出する厚みの金属パッドを備え、その金属パッド
を介してハンダバンプとバンプ用電極とが電気的に接続
していることを特徴とする半導体装置。A semiconductor chip mounted on a substrate having a bump electrode having an insulating layer formed therearound;
In a semiconductor device in which a plurality of solder bumps for mounting on a mother board are electrically connected to bump electrodes, a metal pad having a thickness protruding in a thickness direction from an insulating layer is provided between the bump electrodes and the solder bumps. A semiconductor device comprising: a solder bump; and a bump electrode electrically connected through the metal pad.
れてなることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the metal pad is formed by metal plating.
てなることを特徴とする請求項１又は請求項２記載の半
導体装置。3. The semiconductor device according to claim 1, wherein the metal pad is formed by copper plating.
されてなることを特徴とする請求項１又は請求項２記載
の半導体装置。4. The semiconductor device according to claim 1, wherein the metal pad is formed by solder plating.
電極を有する基板上に半導体チップを搭載すると共に、
母基板に実装するための複数のハンダバンプをバンプ用
電極と電気的に接続して製造する半導体装置の製造方法
において、ハンダバンプをバンプ用電極と電気的に接続
する方法が、バンプ用電極の表面に接して絶縁層より厚
み方向に突出する厚みの金属パッドを設けた後、その金
属パッドに接するようにハンダバンプを設ける方法であ
ることを特徴とする半導体装置の製造方法。5. A semiconductor chip is mounted on a substrate having a bump electrode having an insulating layer formed around the semiconductor chip.
In a method of manufacturing a semiconductor device in which a plurality of solder bumps for mounting on a mother board are electrically connected to bump electrodes, a method of electrically connecting the solder bumps to the bump electrodes is performed on the surface of the bump electrodes. A method for manufacturing a semiconductor device, comprising: providing a metal pad having a thickness protruding in a thickness direction from an insulating layer in contact therewith, and then providing a solder bump so as to be in contact with the metal pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11083895A JP2000277649A (en) | 1999-03-26 | 1999-03-26 | Semiconductor and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11083895A JP2000277649A (en) | 1999-03-26 | 1999-03-26 | Semiconductor and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000277649A true JP2000277649A (en) | 2000-10-06 |
Family
ID=13815379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11083895A Pending JP2000277649A (en) | 1999-03-26 | 1999-03-26 | Semiconductor and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000277649A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
| JP2003007912A (en) * | 2001-06-26 | 2003-01-10 | Kyocera Corp | Wiring board |
| JP2008504696A (en) * | 2004-06-25 | 2008-02-14 | テッセラ，インコーポレイテッド | Parts with posts and pads |
| US8531039B2 (en) | 2003-12-30 | 2013-09-10 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
| US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US8604348B2 (en) | 2003-10-06 | 2013-12-10 | Tessera, Inc. | Method of making a connection component with posts and pads |
| US8641913B2 (en) | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
| US8723318B2 (en) | 2010-07-08 | 2014-05-13 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
| US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
| US8884448B2 (en) | 2007-09-28 | 2014-11-11 | Tessera, Inc. | Flip chip interconnection with double post |
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-
1999
- 1999-03-26 JP JP11083895A patent/JP2000277649A/en active Pending
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
| JP2003007912A (en) * | 2001-06-26 | 2003-01-10 | Kyocera Corp | Wiring board |
| JP4557461B2 (en) * | 2001-06-26 | 2010-10-06 | 京セラ株式会社 | Wiring board |
| US8604348B2 (en) | 2003-10-06 | 2013-12-10 | Tessera, Inc. | Method of making a connection component with posts and pads |
| US8641913B2 (en) | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
| US8531039B2 (en) | 2003-12-30 | 2013-09-10 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
| JP2008504696A (en) * | 2004-06-25 | 2008-02-14 | テッセラ，インコーポレイテッド | Parts with posts and pads |
| US8884448B2 (en) | 2007-09-28 | 2014-11-11 | Tessera, Inc. | Flip chip interconnection with double post |
| US8723318B2 (en) | 2010-07-08 | 2014-05-13 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
| US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9030001B2 (en) | 2010-07-27 | 2015-05-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9397063B2 (en) | 2010-07-27 | 2016-07-19 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
| US9496236B2 (en) | 2010-12-10 | 2016-11-15 | Tessera, Inc. | Interconnect structure |
| US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US9818713B2 (en) | 2015-07-10 | 2017-11-14 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10535626B2 (en) | 2015-07-10 | 2020-01-14 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10892246B2 (en) | 2015-07-10 | 2021-01-12 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US11710718B2 (en) | 2015-07-10 | 2023-07-25 | Adeia Semiconductor Technologies Llc | Structures and methods for low temperature bonding using nanoparticles |
| US11973056B2 (en) | 2016-10-27 | 2024-04-30 | Adeia Semiconductor Technologies Llc | Methods for low temperature bonding using nanoparticles |
| US12027487B2 (en) | 2016-10-27 | 2024-07-02 | Adeia Semiconductor Technologies Llc | Structures for low temperature bonding using nanoparticles |
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