JP2008504696A - Parts with posts and pads - Google Patents

Abstract

  The packaged microelectronic element includes a trace (58) spaced from the outer surface (26), a post (48) extending from the trace and protruding beyond the outer surface of the dielectric, and a pad exposed on the outer surface of the dielectric layer. Incorporating a dielectric layer (22) having (30) and including a connecting component wherein the pad is connected to the post by a trace. The dielectric element is mounted on the surface of the microelectronic element, and the contacts (74) exposed on the surface of the microelectronic element are connected to the pads by elongated leads (76) such as wire bonds. A method of making the connecting component is also disclosed.

Description

This application claims the filing date of US Provisional Application No. 60 / 583,109, filed Jun. 25, 2004, the disclosure of which is incorporated herein by reference.

The present invention relates to components and assemblies useful for microelectronic assemblies, assemblies incorporating such components, and methods of making such components.

  Microelectronic elements such as semiconductor chips are typically provided in packages that protect the semiconductor chip itself from the external environment and facilitate attachment of the chip to a circuit board. For example, some microelectronic packages include connecting components that incorporate a dielectric element such as a board or sheet having a top surface and a bottom surface and conductive terminals exposed on the bottom surface. The chip is attached to the top surface and connected to the terminals by various configurations such as conductive traces extending on or in the surface of the dielectric element. The chip typically has a front surface with small contacts and a back surface facing away. The chip can be mounted in a face-down configuration such that the top surface of the chip faces the top surface of the dielectric element and the back surface of the chip faces upwardly from the dielectric element. In other cases, the chip can be mounted in a face-up configuration such that the back side of the chip faces downwardly toward the top surface of the dielectric element. Contacts on the surface of the chip are typically connected to the traces on the dielectric element by either direct bonds or wire bonds between the contacts and the leads formed integrally with the traces. For example, as disclosed in US Pat. No. 6,177,636, the disclosure of which is incorporated herein by reference, a post in the form of a post protruding from the bottom surface of the dielectric element is formed in a similar chip package. be able to. The post can be made using an etching process. US patent co-pending provisional applications 60 / 533,210, 60 / 533,393, all filed December 30, 2003, all of which are assigned to the same assignee as the present application, the disclosure of which is incorporated herein by reference. And, as disclosed in 60 / 533,437, packages utilizing posts can provide a number of advantageous features. For example, the post and the dielectric layer or layers may facilitate the contact achieved between the post tip and the contact of the test socket when engaging the post tip with the test socket. In addition, it can be configured to promote the inclination of the post.

  Attempts have been made to make electronic connection structures such as individual layers for multilayer circuit boards that use metal post structures. In one process disclosed by North Corporation of Tokyo, Japan, a metal plate is etched to form a metal post protruding from the plate. The dielectric layer is applied to the plate so that the posts protrude through the dielectric layer. The inner surface or upper surface of the dielectric layer faces upward toward the metal plate, while the outer surface or lower surface of the dielectric layer faces downward toward the tip of the post. The dielectric layer is formed by coating a dielectric, such as polyimide, on a plate around the post, and more generally forcing the post to engage the dielectric sheet so that the post penetrates the sheet. It can be produced by combining them. After the sheet is in place, the metal plate is etched to form individual traces that extend to the base of the various posts inside the dielectric layer.

  Components made by this process are subject to certain disadvantages when used as connecting components in certain types of semiconductor chip packages. For example, the chip is mounted in a face-down orientation, and the chip contacts extend from the chip through large openings or slots in the dielectric element or around the edge of the dielectric element to access the outer or bottom surface of the dielectric element It is often desirable to connect to the traces of the connecting component using a wire bond. Such wire bonds can be formed by a simple one-step bonding operation. However, in the process described above, the trace is formed inside or above the dielectric element. Thus, the traces are not exposed to make such a simple one-step wire bond connection to the chip contacts.

  One solution to this problem is to use a two-stage wire bonding procedure, connecting the bonding wires to the traces before placing the chip on the component, and wire protruding through the slot or from the edge of the dielectric element You may leave the free end of. After placing the chip on the connecting part, the free end of the wire remains accessible so that the free end of the wire can be coupled to the chip contact in a second bonding step. However, the two-step bonding process increases the cost and complexity of the assembly procedure and such as adhesive contamination of the chip contact or bonding wire during the chip attachment phase, and misalignment between the free end of the bonding wire and the chip contact. Create a risk of defects.

  Disclosed in a specific embodiment of co-pending US Provisional Application No. 60 / 508,970, filed Oct. 6, 2003, assigned to the same assignee as the present application, the disclosure of which is incorporated herein by reference. As described above, the connection component including the post can be provided with a pad exposed on the bottom surface or outer surface of the dielectric. The component includes, as described above, a post such that the metal sheet is disposed on the top or inner surface of the dielectric layer, and the post protrudes through the dielectric layer and beyond the bottom surface of the dielectric layer. It can be produced by integrating a metal sheet having a dielectric layer with a dielectric layer. Some of the posts are crushed, polished, or otherwise treated to turn them into pads that protrude very slightly from the outer or bottom surface of the dielectric. The metal sheet is etched to form traces that connect the pads to the posts. The pad may be formed adjacent to the edge of the dielectric or adjacent to the slot of the dielectric. Such a component can be combined with the chip in a face-down orientation by placing the chip contacts outside the edge of the dielectric or in alignment with the dielectric slots. The pads, and thus the traces and posts, can be connected to contacts on the chip by a simple one-step wire bonding procedure.

  One aspect of the present invention provides a connection component for attaching a microelectronic element. The connecting component according to this aspect of the present invention preferably includes a dielectric layer having an upward inner surface and a downward outer surface. Preferably, the connecting component has conductive traces that extend away from the outer surface on the dielectric layer, for example, on the inner surface of the dielectric layer or within the thickness of the dielectric layer. A conductive post extends from the trace through the dielectric layer and projects downward beyond the outer surface of the dielectric layer. The component according to this aspect of the invention includes a conductive pad exposed on the outer surface of the dielectric layer, at least some of the pads being electrically connected to at least some of the posts by at least some of the traces. It is desirable that

  The post is for attaching the component and thus the microelectronic element carried on the component to a circuit panel, such as a circuit board, by soldering, for example, the end remote from the dielectric layer of the post to the circuit panel. Can be used. The pad can be used to make a connection with a microelectronic element attached to the component. In a particularly preferred configuration, the pad is used for wire bonding. The pad is preferably located near the edge of the dielectric layer or near a slot or other opening in the dielectric layer.

  A further aspect of the invention provides a packaged microelectronic element that includes the component described above and a microelectronic element attached to the component. The dielectric layer of the component is most commonly placed on the contact bearing surface or surface of the microelectronic element, and at least some of the contacts of the microelectronic element are attached to at least some of the pads of the component. Connected. Most preferably, the connection includes an elongate lead such as a wire bond that extends around the edge of the part or penetrates the opening in the part.

  A further aspect of the present invention provides a method for making a connection component. The method according to this aspect of the invention desirably begins with a starting structure that includes a dielectric layer and a conductive element, referred to herein as a connector, with an outer conductive layer covering the connector. Most preferably, the method includes the step of treating the layer to remove at least a portion of the outer conductive layer at the pad location while leaving at least a portion of the layer at the post location. Thus, the process forms pads and posts incorporating the connector. For example, the processing step removes the entire thickness of the outer conductive layer at the pad location, thereby forming a pad consisting of only the connector, and leaving the entire thickness of the outer conductive layer at the post location, It can be performed to leave a post that includes a connector along with a portion formed from the material.

  A method of making a component according to one embodiment of the present invention utilizes a dielectric layer 22 (FIG. 1) having an upward inner surface 24 and a downward outer surface 26. As used in this disclosure, terms such as “upward”, “downward”, “vertical”, and “horizontal” should be understood to refer to a frame of reference of a specified element. However, it is not necessary to comply with the normal gravity reference system. The dielectric layer has a hole 28 extending therethrough between the top surface and the bottom surface. The dielectric layer can be of any thickness, but is most commonly about 10-100 μm thick. It can be a solid, uniform layer, such as a layer of polyimide, BT resin, or other material of the type commonly used to form flexible circuit panels, or glass fiber reinforced It can be a reinforcing layer such as an epoxy. The dielectric layer can also include internal conductive structures such as ground planes or trace layers. Generally, such an internal conductive layer is isolated from most or all of the holes 28 so as not to contact conductive elements disposed within the holes as described below.

  The process also uses a conductive inner conductive layer 30 that is most typically about 5-50 μm thick, preferably formed from a metal such as copper or a copper-based alloy. Layer 30 is a unitary structure that is integrally formed with the rest of the layer and that extends from one side of the layer and has a protrusion 32 referred to herein as a “connector”. The connector 32 is arranged in a pattern corresponding to the pattern of the holes 28 in the dielectric layer. A planar outer conductive layer 34 formed from an etchable conductive material, preferably a metal such as copper or a copper-based alloy, is also used. The outer conductive layer 34 is most commonly about 50-300 μm thick.

  In one stage of the process, the conductive layer and the dielectric layer are stacked to form the process intermediate structure 38 (FIG. 2). The lamination process is performed such that the connector 32 extends through the hole 28 in the dielectric layer 22 and abuts the outer layer 34. In order to ensure abutting contact, the height of the protrusion 32 prior to lamination can be slightly greater than the thickness of the dielectric layer 22 so that the protrusion 32 is slightly planarized by engagement with the outer layer 34. Thus, both layers are clamped together in a press or nip. Most preferably, the abutment surfaces of the protrusion 32 and the layer 34 are joined together. For example, these surfaces can be joined by applying an electrical current between layers 30 and 32 and performing electrical resistance welding at the abutment surface. Also, sonic or ultrasonic energy can be applied to facilitate welding of the connector 32 and the outer layer 34. Alternatively or additionally, a thin layer (not shown) of a bonding material, such as a eutectic bonding alloy or solder, that is activated during the bonding process is applied to the abutment surface of connector 32, layer 34, or both. Can be provided.

  In the process intermediate unit 36, the inner conductive layer 30 is bonded to the upper surface of the dielectric layer 24. Such adhesion can be achieved by a layer of adhesive (not shown) carried on one of these layers. Alternatively, the dielectric layer is provided in a partially cured state and can be further cured in contact with layer 30 during the lamination process. Although the individual layers are depicted separately in FIG. 1, the dielectric layer 22 can most commonly be transferred to a lamination process on the inner layer 30 or the outer layer 34. For example, holes 28 can be provided in the dielectric layer, such as by ablating, drilling, or etching the continuous dielectric layer, and then laminating the dielectric layer over the external conductive layer. Alternatively, the dielectric layer 22 can be formed on the conductive layer, such as by coating the conductive layer with a liquid precursor and then curing the precursor to form a dielectric. If the dielectric is a photosensitive material, such as a type of photosensitive material commonly used as a solder mask on an electronic component, the holes 28 can be formed by forming a photographic pattern on the dielectric. In a further variation, a fully or partially cured solid dielectric layer without pre-formed holes is forced to engage the inner or outer conductive layer support connector so that the connector penetrates the dielectric layer. Can be combined. To facilitate this process, the connector can form a tip or point.

  Process intermediate unit 36 (FIG. 2) has internal and external conductive layers 30 and 34 that are interconnected by a connector 32 that extends through dielectric layer 22 disposed between the conductive layers.

  In a further stage of the process, the outer conductive layer 34 of the process intermediate unit is processed. In this processing step, an etch resistant material, such as photoresist 38, is applied to a location 42 on the outer surface 40 of the layer, aligned with a portion of the connector 32, referred to herein as a “post location”. The etching resistant material is removed at positions other than the post position. In particular, the position 44, referred to herein as the “pad position”, aligned with the other connector 32 is not coated with an etch resistant material. The etch resistant material can be applied by conventional photographic patterning procedures. After the application of resist 38, the outer surface 40 of layer 34 is exposed to an etchant that attacks the material of layer 34. Etch exposure is sustained for a time sufficient to remove the entire thickness of layer 34 at a location such as pad location 44. The entire thickness of the layer 34 remains at the post location 42 so as to form a set of posts 48 that protrude beyond the outer surface 26 of the dielectric layer by a protruding distance Dp. By way of example only, Dp can be about 50 to about 300 μm. Each post includes an upper portion formed from one of the connectors 30 such as the connector 30a (FIG. 3) and a lower portion 50 formed from the material originally present in the outer layer. The lower portion defines a base surface 52 at the junction between the upper and lower portions. In the particular embodiment shown, the base surface has a horizontal dimension (a direction parallel to the surface of the dielectric layer) that is greater than the horizontal dimension of the upper portion 30a at such a junction. In other words, the horizontal dimension of the post increases at the junction between the upper portion 30a and the lower portion 50.

  At the pad location 44, the downward facing surface 54 (FIG. 3) of the connector 30 is exposed by the removal of the outer conductive layer 34 (FIG. 2). Thus, the connector 30 forms a pad having a surface exposed to the outer surface of the dielectric layer, that is, the bottom surface 26. In the particular embodiment illustrated, the exposed surface 54 of the pad 30b is strictly flush with the outer surface 26 of the dielectric layer, but this is not required. The exposed surface can be retracted relative to the outer surface 26, or can protrude beyond such surface as described below. As used in this disclosure, conductive features may be considered “exposed” to the surface of a dielectric layer if the metal features are accessible to contacts or bonding materials applied to such surfaces. it can. In this way, metal features that protrude from the surface of the dielectric or are flush with the surface of the dielectric are exposed to such a surface, while placed in or aligned with the dielectric holes. Recessed conductive features that extend to the surface are also exposed on such surfaces.

  In a further stage of the process, the inner conductive layer 30 of the process intermediate unit 36 patterns additional photoresist or other etch resistant material 56 (FIG. 2) on this layer, which is then exposed to an etchant. Then, it is processed by removing a portion not covered with the photoresist. The remainder of the inner conductive layer forms traces 58 (FIG. 3) that extend between at least a portion of the pad locations 44 and at least a portion of the post locations 42, so that these traces are at least a portion of the pad 30a. It is electrically connected to at least a part of the post 48. Although only two pads 30b are depicted in the cross-sectional view of FIG. 3, a number of pads are formed in two parallel spaced apart rows extending in and out of the plane of the diagram of FIG. It is desirable. The exposed surface 54 of the pad and the surface of the post can be plated with an oxidation resistant metal such as nickel and gold.

  Slots 66 are formed in the central region of the dielectric layer such that the slots extend between the rows of pads 30b and the pads are positioned adjacent the edges of the slots. The slot 66 is formed, for example, by mechanically perforating the dielectric layer, by ablating the dielectric layer using a laser or other concentrated energy source, or by chemically etching the dielectric layer. can do. The connection piece thus completed has the shape shown in FIG. 3, with pads being placed in the slot edge region adjacent to the edge of the slot, while posts 48 are provided in other regions of the dielectric layer.

  The order of the steps used to create the part can be varied from the order described above. For example, for ease of understanding, the steps of processing the outer conductive layer 34 and the inner conductive layer 30 have been described sequentially above, but these steps can be performed in any order or simultaneously. For example, after application of photoresists 38 and 56 (FIG. 2), both the inner and outer conductive layers can be etched simultaneously. Also, the conductive layer 30 may be in the form of individual conductive features or traces 58 when first integrated with the dielectric layer. For example, the trace 58 can be formed by selectively disposing on the dielectric layer before or after processing the outer conductive layer. If the inner conductive layer 30 or trace 58 is formed by depositing on the inner surface 24 before processing the outer conductive layer, the connector 32 can be formed in the same deposition step. In a further variation, the connector 30 (FIG. 1) can be initially formed on the outer conductive layer rather than the inner conductive layer. In this case, the outer conductive layer can be treated before or after application of the inner conductive layer or trace. Also, the step of forming slots in the dielectric layer can be performed before or after other steps of the process. Also, various steps can and are most preferably performed while the dielectric layer 22 is part of a larger sheet or tape. As shown in FIG. 3, individual connecting components can be obtained by cutting such sheets or tapes. Most commonly, however, the connection components remain in sheet or tape form until after a semiconductor chip or other device is attached to the component.

  Other methods of forming the process intermediate unit 36 (FIG. 2) can be used. Merely by way of example, layer 22 is an uncured dielectric so as to engage inner conductive layer 30, connector 32, and outer conductive layer 34, for example, in a compression mold or injection mold, to properly form a dielectric layer. It can be cast or molded around the connector 32, such as by injecting a body around the connector. Alternatively, the dielectric can be applied as a flowable material and forms a layer around the connector under the influence of gravity or under the influence of centrifugal force applied to a centrifuge or similar device. Can be made to flow.

  Packaged microelectronic elements 68 (FIG. 4) made using the components of FIG. 3 are arranged in one or more rows on a surface with a semiconductor chip or other microelectronic element 70 having a surface 72. Integrated contact 74. The component and semiconductor chip are assembled such that the dielectric layer 22 of the component rests on the surface with the inner surface 24 of the dielectric layer facing the surface of the chip. The rows of contacts 74 on the chip are aligned with the slots 66 in the dielectric layer. The die attach layer 75 is provided between the surface of the chip and the inner surface of the dielectric layer. Generally, the die attach layer includes a dielectric adhesive. Optionally, the die attach layer can include a flexible layer to facilitate movement of the post 48 and other elements of the connecting component relative to the chip during testing and operation.

  Chip contacts 74 are connected to pads 62 by wire bonds 76 extending through slots 66. After the contacts are wire bonded to the pads, a dielectric encapsulant 78 is applied over the pads and wire bonds, and the encapsulant typically covers the contacts 74 on the chip and also contacts the die attach material 75. So that the slot 66 is filled. Insert additional overmold (not shown) into the chip so that the overmold covers the exposed edge of the chip and, in some applications, also covers the upper rear surface of the chip to provide additional physical protection. Can be provided around.

Desirably, the height or projecting distance from the bottom surface i.e. the exterior surface 26 of the sealing member D _E is equal to or lower than the height or projecting distance D _P of the post. Also, the height or protrusion distance of the wire bond 76 is lower than D _P and lower than D _E so that the wire bond 76 is completely covered by the encapsulant. In other words, the difference in height or protrusion distance between the pad 30b and the post 48 can accommodate the thickness of the wire bond 76 overlying the pad and the thickness of the encapsulant overlying the wire bond. It is enough. The wire bonding and sealing steps can be performed using conventional equipment and procedures. In particular, the wire bonding step can be performed in a single bonding operation using a bonding tool that approaches the assembly from the outer or bottom surface 26 of the dielectric layer. As mentioned above, the parts are typically provided in the form of a sheet or tape containing a number of parts. The chip is attached to these components, and the wire bonding and sealing procedures are preferably performed while the connecting components are in the form of a sheet or tape. After the procedure has been performed, the sheet or tape is typically cut so that a large number of individual units, each incorporating one or more chips, result.

  The packaged chip can be inspected by engaging the post 48 with a test fixture (not shown). In some cases, post 30 can be moved closer to or away from tip 70 vertically during the inspection procedure to ensure proper engagement of all posts 30 with the test fixture. Such movement can be facilitated by softening the dielectric layer 22 and the trace 58 and by providing compressibility to the die attach layer 75. In addition, the post, dielectric layer, and die attach layer can be used to facilitate post movement and preferably post tilting during engagement with the test fixture, as described above in co-pending application 60 / 533,210. No. 60 / 533,393 and 60 / 533,437 can be provided. The inspection operation can be performed before or after cutting individual units of the tape and before or after application of the sealant 78. If the inspection operation is performed prior to applying the encapsulant and overmold, the defective wire bond 76 detected in the inspection operation can be reworked.

  The packaged microelectronic element 68 can be attached to a circuit panel, such as the circuit board 80 partially shown in FIG. Posts 48 can be bonded to contact pads 82 on the top surface of the circuit board using conventional surface mount techniques. Preferably, only a thin layer of bonding material, such as solder 84, is provided between the tip of the post and the contact pad. Some bonding material can also be extended along the post (not shown) so that the end of the post remote from the dielectric layer 22 is engaged within the bonding material mass. In a conventional manner, circuit panel 80 includes conductive elements such as traces (not shown) that connect contact pads 82 with other elements of the electronic circuit. The sealing material 78 is irrelevant to the top surface of the circuit board.

  In the completed circuit, the post 48 preferably allows movement of the contact pads 82 on the circuit board relative to the chip contacts 74, for example during thermal expansion differences and thermal contractions of the operating element, and during manufacturing, for example during the solder bonding process. If caused by contraction, it can move or tilt slightly to accommodate it. The post may also be bent slightly to accommodate such movement.

  The diagrams of FIGS. 1-5 are simplified for clarity. Generally, the part includes more than one row of posts on either side of the slot. As shown in the bottom view of FIG. 6, the dielectric layer 22 can be substantially rectangular and the slot 66 can be elongated. One or more rows of pads 30b are provided in the slot edge region adjacent to the edge of the slot, but multiple rows of posts 48 are provided in other regions of the dielectric layer. Pad 30b is connected to post 48 by trace 58 as described above. As also shown in FIG. 6, each pad can be connected to one or more posts, and the posts can be connected to each other by several traces. Only a few traces 58 are shown in FIG. 7 for clarity. As described above, the dielectric layer 22 can have embedded conductive features such as a ground plane. In addition, conductive features formed in the same operation as trace 58 can serve as ground or power planes and can be connected to parts of posts and / or pads, such as other conductive features such as conductive planes. Sex elements can also be included.

  It is not essential to provide the slot in the center of the dielectric element. Thus, the slot 66 can be offset from the center of the dielectric element. Also, more than one slot can be provided in a single dielectric element. In a further variation, the slots can be replaced with a set of discrete openings, each surrounding one or more contacts 74 on the chip, and the wire bonds can extend through these openings.

  A packaged chip 168 (FIG. 7) according to a further embodiment of the invention includes a dielectric layer 122, pads 130b, posts 148, and traces 158 made in substantially the same manner as described above, It includes a connection component having conductive features similar to the corresponding features described above. However, in this embodiment, the dielectric layer includes opposing edges 102 and 104 and the pad 130b is formed adjacent to these edges in the edge region of the dielectric layer. In this embodiment as well, the chip or other microelectronic element 170 is mounted with its surface or contact bearing surface facing down and toward the dielectric element. The chip has opposing edges 106 and 108 and the edge region of the chip surface protrudes beyond the edges 102 and 104 of the dielectric layer. The chip contacts 174 are disposed in these edge regions on the chip surface, for example, by providing one or more contacts in each edge region. A wire bond 176 extends from the contact 174 and extends around the edges 102 and 104 of the dielectric element. The encapsulant 178 covers the wire bonds and covers the edge region of the chip and the edge region of the dielectric element. In a further variation, the encapsulant can also cover the chip edges to provide physical protection to the chip edges. Alternatively, a further overmold can be provided around the chip. It is not essential to provide pad and wire bonds only on the two opposite edges. For example, pads and wire bonds can be provided on the four edges of a rectangular dielectric element, and the chip can have edge regions that extend beyond all of these edges. Conversely, the chip can extend beyond only one edge of the dielectric element and the pad can be provided only on that edge. Also, the edge pad method illustrated in FIG. 7 is adapted to the slot edge pad shown in FIG. 6 such that pads are provided on both outer edges of the dielectric element and along the edges of one or more slots of the dielectric element. Can be combined.

  In the embodiment described above, the pad has an exposed surface that is substantially flush with the outer surface or bottom surface of the dielectric element. However, as shown in the partial cross-sectional view of FIG. 8, the pad may have an exposed surface 254 that is recessed over the outer surface 226 of the dielectric element. This type of pad is shown in FIGS. 2 and 3 to process the outer conductive layer, except that the etching step lasts longer than necessary to completely remove the outer conductive layer at the pad location. It can be fabricated using an etching process similar to that described above. The receding concave pad increases the difference between the pad height and the post height, thus increasing the spatial distance for wire bond and sealant thickness. The pad thickness can be further reduced, in fact reduced to zero, as the exposed surface of the pad is defined by the surface 255 of the lead itself exposed at the pad location through the dielectric layer hole 228 to the bottom surface 226. can do. Such a configuration may be used, for example, in a component having a thin dielectric layer so that the exposed surface 255 is sufficiently close to the bottom surface 226 of the dielectric layer for wire bonding, even with a zero thickness pad. it can.

  Conversely, the component of FIG. 9 includes a pad 330 b that extends downwardly from the outer surface 326. The pad and especially the exposed surface 354 of the pad thus protrudes downward beyond the outer surface. The post 348 includes an upper portion 330a that projects below the outer surface 326 such that the base surface 352 of the post is away from the outer surface of the dielectric layer. Here again, the post height exceeds the pad height so that wire bonds and encapsulant (not shown) can be received. A component of this configuration is, for example, initially higher than the thickness of the dielectric layer so that the connector is not substantially attacked by the etchant used to remove the portion of the outer conductive layer and form the post. This connector can be prepared by providing an etching resistant layer on the connector.

  In the embodiment described above, the entire thickness of the outer conductive layer, such as layer 34 (FIGS. 2 and 3), is removed at pad location 44. However, this is not essential. A portion of the thickness of the outer conductive layer can be left in place at the pad location so that a portion of the outer conductive layer remains as part of each pad. For example, a spot of etch resistant material can be applied to the pad location after the outer conductive layer has been etched to a certain degree. Alternatively, the outer conductive layer includes two layers of copper or other easily etchable conductive material, and a spot of an etch resistant material such as gold disposed between these layers at the pad location. It can be provided as a composite layer. In this case, the etching process is stopped at the pad position when it reaches the boundary between the layers.

  Also, in the process described above, the entire thickness of the external conductive layer is appropriate at the post position so that the post has a protruding distance Dp (FIG. 3) equal to the initial thickness of the external conductive layer 34 (FIGS. 1 and 2). Left behind. However, this is not essential. A portion of the initial thickness of the outer conductive layer may be removed during processing. In other words, the thickness of the external conductive layer may not be removed at all or may be removed at the post position, and part or all of the thickness of the external conductive layer may be removed at the pad position. it can. However, it is desirable to remove more of the outer conductive layer at the pad position than at the post position so that the post continues to protrude downward beyond the pad.

  In the discussion above, the post is idealized as a generally frustoconical element. However, it is not essential for the post to have this shape. As shown in FIG. 10 and as detailed in the above-mentioned US Pat. No. 6,177,636, the post may be an etch resistant that may be a photoresist or a corrosion resistant metal such as nickel, gold, etc. It can be formed by applying a functional material to the surface 404 of a metal plate or sheet. After application of the etch resistant material, an etchant is applied to this surface in the form of a jet directed generally perpendicular to the surface 404. The metal of the plate or sheet can be etched to form a post 448 having the configuration shown in broken lines in FIG. In this configuration, the lower portion 450 of the post 448 has the shape of a “cooling tower”. Each such lower portion has a base 452 connected to an upper portion 430a, a tip 433 spaced from the base, and an intermediate portion 435 between the base and the tip. The middle portion 435 is narrower than the tip portion 433 and narrower than the base 431 so that the post tapers inward in the direction from the base to the middle portion and tapers outward from the middle portion toward the tip. If the spot 402 of etch resistant material is round, the post generally has the shape of a rotating body about an axis 437 extending perpendicular to the surface 404 and perpendicular to the surface of the remainder 428. If the etch resistant material 402 is a photoresist or other material that is not desired in the final product, the etch resistant material can be removed prior to further processing. Alternatively, if the etch resistant material is a corrosion resistant metal such as nickel or gold, it can be left in place.

  A further embodiment of the present invention provides an elongated post 548 (FIG. 12). In one stage of the post forming process, a first set of post portions 550 (FIG. 11) protrudes from a surface 526, such as the surface of a dielectric element. The post portion 550 can be formed by any process, but is preferably formed by the process described above. After formation of the portion 550, a metal or other conductive layer 502 is applied over the tip 533 of the post portion 550. Layer 502 removes layer material from post portion 550, but leaves an additional post portion 504 (FIG. 12) that leaves at least a portion of the thickness of the layer overlying post portion 550 and thereby aligns with post portion 550. Processed selectively to form. The treatment applied to layer 502 can include the etching process described above using a spot of etch resistant material 506 aligned with post portion 550. Prior to etching layer 502, a protective layer, such as dielectric encapsulant 508, can be applied to cover post portion 550. Alternatively or additionally, post portion 550 can be plated or otherwise coated with an etch resistant conductive material such as nickel or gold prior to etching layer 502.

  The process of forming continuous post portions can be repeated to form additional portions under portion 504. Posts of essentially any length can be formed. Long posts increase the flexibility and mobility of the post tip. If one or more dielectric encapsulant layers are left around the already formed post portion, such as layer 508 in FIGS. 11 and 12, the encapsulant does not substantially limit post curvature. In addition, it is desirable to be flexible. In other embodiments, the sealant is removed prior to using the part. Although the posts are illustrated with a dielectric substrate 522 and traces 528 similar to those described above, this process can be used to make posts for essentially any structure.

  The above-described connecting component can be used for an assembly fitted in a socket, rather than being surface-mounted on a circuit board. For example, the packaged semiconductor chip described above can be attached to the socket such that each post extends into the socket's mating hole and makes electrical contact with the socket's contacts. Certain suitable sockets are described in the embodiments of US Pat. Nos. 5,802,699, 5,980,270, and 5,615,824, the disclosures of which are hereby incorporated herein by reference. Incorporate into. In a further alternative, the socket configuration can be used as a temporary test fixture and the assembly can be soldered or otherwise joined to the circuit board after inspection. In yet another configuration, the part can be used as an element of a stack assembly. For example, the assembly shown in FIG. 13 is stacked on each other so that each such packaged microelectronic element acts as a single unit in a multi-unit stack assembly, each of the packaged elements of FIG. 68 includes several packaged microelectronic elements 668a, 668b, and 668c that are similar to 68. Each unit has an upwardly conductive element, such as a portion of trace 658 that protrudes beyond chip 670 and is exposed on the top or inner surface 624 of the dielectric element. The upward conductive element of unit 668c is connected to the post 648 of the next higher unit 668b in the stack while the upward conductive element of unit 668b so that the post acts as a vertical interconnection element between the various units. The sex element is connected to post 648 of unit 668a. Other features of stack packages are described, for example, in US Patent Publication Nos. 20030107118A1 and 20040031972A1, the disclosures of which are incorporated herein by reference.

  Features other than posts and pads can be created using the processes discussed herein. For example, the thermally conductive element can be provided by leaving some or all of the thickness of the outer conductive layer during etching or other processing steps as described above. Such a thermally conductive element can have a height equal to the height of the post and can have a cross-sectional area that is greater than the cross-sectional area of the individual posts. The use of a thermally conductive element is referred to as “MICROELECTRONIC PACKAGES AND METHODS THEREFOR” in copending US Provisional Application No. 60 / 583,066 filed on June 25, 2004, in which Belgacem Haba was designated as inventor. Which has been described in detail, the disclosure of which is incorporated herein by reference.

  The assembly described above includes relatively simple parts with the single layer conductive traces described above. However, two or more layers of traces can be used and other conductive features such as conductive planes can be included. For example, as shown in FIG. 14, a component having multiple trace layers may include an additional dielectric layer 702 having additional traces 704, and traces on the first dielectric layer 722 through such additional dielectric layers. Additional connectors 706 can be formed that extend to conductive features such as 758. The additional dielectric layer 702 is preferably laminated to the first dielectric layer after forming the trace 758 on the first dielectric layer. This can be done before or after the formation of post 748 and before or after the outer conductive layer used to form the post is deposited on the first dielectric layer. In the embodiment described above, traces such as trace 58 (FIGS. 3-5) extend along the surface of the dielectric layer. However, this is not essential. Traces or other conductive features can be disposed in the dielectric layer. For example, in FIG. 14, trace 758 extends into a composite dielectric layer incorporating layers 702 and 722. As used in this disclosure, when a conductive element is said to be “on” a dielectric element or layer, the conductive element need not be disposed on the surface of the dielectric, but instead disposed within the dielectric. be able to. That is, the word “up” does not imply placement on the surface of the dielectric.

  In the embodiments described above, the chip or other microelectronic element is arranged in a face-down orientation with the contact bearing surface facing the dielectric element. However, connection components made in accordance with the present invention can be used to attach microelectronic elements in a face-up orientation. For example, as shown in FIG. 15, the packaged microelectronic device includes a chip 870 having a contact 874 on a surface 872. Surface 872 faces in the upward direction opposite the dielectric elements and traces. Wire bond 876 extends downward from contact 874 to trace 858, which is then connected to post 848 as described above. In this embodiment, it is not necessary to expose the pad to the outer surface of the dielectric layer, ie the downward surface. The process of creating the connection piece can be performed in substantially the same manner as described above, except that no connector is provided at the pad location, as described above in connection with FIGS. it can. In a further variation (FIG. 16), chip 871 has a contact 873 on the face down, but the contact is connected to the lead by a large amount of solder or other bonding material 875, commonly referred to as a “flip chip” implementation. Even in this embodiment, exposure of the pad is not essential.

  In a further variation (FIG. 17), the trace 958 formed from the inner conductive layer includes a lead portion 959 formed integrally with the trace. When initially formed, these lead portions are slot 966 in the dielectric element so that they can be coupled to contacts 974 of a microelectronic element such as a chip 970 arranged in a face-down orientation. Project partially or completely beyond. In a further variation, the lead portion projects beyond one or more edges of the dielectric element so that the lead portion can be coupled to a contact on the tip of the chip, such as contact 174 shown in FIG. Can do.

  In yet another variation (FIG. 18), the connecting component has both posts 1048 and pads 1030 exposed on the bottom or outer surface 1026 of the dielectric element 1022. In the embodiment described above in connection with FIGS. 1-5, post 1048 protrudes downward beyond the pad. A microelectronic element, such as chip 1070, is mounted under the dielectric element and connected to pad 1030 by solder element 1002 or other bonding technique. This microelectronic element is connected to trace 1058 by a pad. A further microelectronic element 1071 is optionally provided above the dielectric element and connected to the trace 1058 by flip chip bonding using a solder element 1004. Depending on the configuration of the trace, the trace can connect one or both of the chips 1070 and 1071 to the post 1048 and can connect the chips to each other. In this embodiment, the height difference between the pad and post provides space for mounting the bottom chip 1070. The bottom tip does not protrude below the tip of the post and therefore does not interfere with the connection between the post and the circuit panel. In other embodiments, some of the pads on the dielectric element can be used to connect to a chip or other element disposed above the dielectric element, such as by a wire bonding process. The other pads can be connected to a chip disposed below the dielectric element.

  These and other variations and combinations of the features set forth above may be utilized without departing from the invention as defined by the claims, and the above description of preferred embodiments will be described in terms of the invention as defined by the claims. It should be taken as an explanation, not as a limitation.

FIG. 6 is a schematic cross-sectional view showing elements of a connection component during one stage of a method according to an aspect of the present invention. FIG. 2 is a view similar to FIG. 1 showing elements at a later stage in the process. FIG. 3 is a schematic cross-sectional view of a part formed by the processes of FIGS. 1 and 2. FIG. 4 is a schematic cross-sectional view illustrating a packaged microelectronic element incorporating the component of FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating an assembly incorporating the packaged microelectronic element of FIG. 4 with a circuit board. FIG. 5 is a schematic plan view of the assembly shown in FIG. 4 with a portion removed for clarity of illustration. FIG. 6 is a schematic cross-sectional view illustrating a packaged microelectronic element and connection component according to a further embodiment of the present invention. It is a partial schematic sectional view which shows a part of connection component which concerns on another embodiment of this invention. It is a figure similar to FIG. 8 which shows the component which concerns on another embodiment of this invention. It is a schematic sectional drawing which shows the component which concerns on another embodiment of this invention in one step in a preparation process. FIG. 6 is a schematic cross-sectional view of such a component during the next stage when forming the component according to yet another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of such a component during the next stage when forming the component according to yet another embodiment of the present invention. 6 is a schematic cross-sectional view of an assembly incorporating a plurality of packaged semiconductor chips according to yet another embodiment of the present invention. FIG. FIG. 6 is a schematic cross-sectional view of a connection component and a packaged semiconductor chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a connection component and a packaged semiconductor chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a connection component and a packaged semiconductor chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a connection component and a packaged semiconductor chip according to a further embodiment of the present invention. FIG. 18 is a view similar to FIGS. 14-17 illustrating an assembly incorporating a packaged microelectronic element with an additional microelectronic element.

Claims (31)

(A) a dielectric layer having an upward inner surface and a downward outer surface;
(B) conductive traces extending on the dielectric layer spaced from the outer surface;
(C) a conductive post penetrating the dielectric layer from the trace and projecting downward beyond the outer surface of the dielectric layer;
(D) a conductive pad exposed on the outer surface of the dielectric layer, wherein at least a portion of the pad is electrically connected to at least a portion of the post by at least a portion of the trace; Connection parts for mounting microelectronic elements, including pads.   The component of claim 1, wherein the pad defines an exposed pad surface that is recessed upwardly from the outer surface.   The component of claim 2, wherein the pad protrudes downwardly from the trace at least partially through the dielectric layer.   The component of claim 2, wherein the pad defines a downward pad surface that is substantially flush with the outer surface of the dielectric layer.   The pad protrudes downward from the trace through the dielectric layer and protrudes downward beyond the outer surface by a pad protruding distance, the post protrudes downward by a post protruding distance beyond the outer surface, and the pad protrusion The component of claim 1, wherein the distance is less than the post protrusion distance.   The component of claim 1, wherein the post is adapted to be soldered to a circuit panel.   The post includes an upper portion extending downward from the trace, and a lower portion protruding downward from the upper portion, the upper portion defining an end surface having a horizontal dimension, and the lower portion being adjacent to the upper end surface The component of claim 1, wherein the component defines a surface and the base surface of the post has a horizontal dimension that is greater than a horizontal dimension of the end surface.   The component according to claim 1, wherein the upper end surface is substantially flush with the outer surface of the dielectric element.   The dielectric layer has a plurality of edges and an edge region adjacent to the edges, and at least a portion of the pad is exposed to a first edge region of the edge region adjacent to the first edge of the edge. 1. The component according to 1.   With the inner surface of the dielectric layer facing upward toward the surface, the dielectric layer rests on a portion of the surface, and the first contact region of the surface is the dielectric layer A length that protrudes outward beyond the first edge, the microelectronic element having contacts exposed on the surface in the first contact region, and extending between at least some of the contacts and at least some of the pads. A packaged microelectronic element comprising the component of claim 9 further comprising a scale lead and a microelectronic element having a surface.   The dielectric layer has a second edge opposite to the first edge and a second edge region adjacent to the second edge, and the surface of the microelectronic element is outside the second edge. A second contact region that protrudes into the first edge region, the pad including a second edge pad exposed at the second edge region, and the microelectronic element exposed at the first surface in the second contact region. 11. The packaged microelectronic element having a contact, further comprising an elongated second edge lead extending from at least some of the contacts in the second region to at least some of the second edge pads. Packaged microelement as described.   The dielectric layer has an elongated slot extending therethrough, the dielectric layer defining a pair of slot edge regions on either side of the slot, and the pad is in at least one of the slot edge regions The component of claim 1 including an exposed slot edge pad.   With the inner surface of the dielectric layer facing up toward the surface, the dielectric layer rests on a portion of the surface, the microelectronic element is exposed on the surface, and the slot 13. The component and surface of claim 12, further comprising an elongated slot lead extending through at least some of the contacts from the at least some of the contacts to at least some of the slot edge pads. Packaged microelectronic elements including microelectronic elements.   The packaged microelement according to claim 10, wherein the elongated lead is a wire bond.   The component of claim 1, wherein the trace extends on the inner surface of the dielectric layer.   The component of claim 1, wherein the pad has a downwardly exposed surface, the pad includes a first metal, and a layer of a second metal covers the surface.   The component of claim 1, wherein the pad has a downwardly exposed surface, and the surface of the pad is substantially flat.   The outer surface of the dielectric layer is removed to remove at least a portion of the outer conductive layer at a pad location and leave at least a portion of the outer layer at a post location, thereby forming a pad and a post incorporating the connector. A method of fabricating a connecting component comprising the steps of covering and removing a portion of the outer conductive layer covering the conductive connector on the dielectric layer, wherein the pad has a downward surface exposed to the outer surface; The method is configured such that the post projects downward from the outer surface of the dielectric layer and projects downward beyond the surface of the pad.   The method of claim 18, wherein the step of processing the outer conductive layer includes removing the entire thickness of the outer conductive layer at a pad location.   The method of claim 18, wherein the step of processing the outer conductive layer comprises leaving the entire thickness of the outer conductive layer at the post location.   The method of claim 18, wherein the step of processing the outer conductive layer includes etching the outer conductive layer.   The etching step is performed to remove the entire thickness of the outer conductive layer at the pad location, thereby exposing the connector at the pad location, and the method is further performed after the connector is exposed. The method of claim 21, further comprising continuing the etching step such that a portion is removed, thereby retreating the downwardly exposed surface of the pad above the outer surface of the dielectric layer.   An internal conductive layer spaced from the external conductive layer and connected to the pad so as to remove a portion of the internal conductive layer, thereby forming a trace connecting at least some of the pads with at least some of the posts; The method of claim 18, further comprising processing the layer.   24. The method of claim 23, wherein the inner and outer conductive layers are metal layers, and the step of processing the inner and outer metal layers includes etching both of the metal layers simultaneously.   The method of claim 18, further comprising joining the inner and outer conductive layers, the connector, and the dielectric layer prior to the step of processing the outer metal layer.   The joining step includes providing a hole extending between the outer surface and the inner surface in the dielectric layer, and laminating the conductive layer and the dielectric layer, wherein the connector is 26. The method of claim 25, wherein one of the conductive layers has the connector for placement in a hole.   27. The method of claim 26, wherein the inner conductive layer has the connector integrally formed therewith. (A) applying a conductive layer on the tip of the first post portion protruding from the structure;
(B) removing a portion of the layer from the first post portion and leaving a portion of the layer aligned with the first post portion, thereby forming a second post portion aligned with the first post portion; A method of forming an elongated post protruding from the structure, comprising: treating the conductive layer.   The step of treating the conductive layer includes exposing the conductive layer to an etchant, and the method further includes protecting the first post portion from the etchant prior to completion of the exposing step. 29. The method of claim 28, further comprising: applying a protective layer surrounding the first post portion.   30. The method of claim 29, wherein the protective layer is a dielectric layer.   30. The method of claim 29, further comprising removing the protective layer.

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