CN113937149A - Terminal structure of semiconductor power device and manufacturing method thereof - Google Patents

Terminal structure of semiconductor power device and manufacturing method thereof Download PDF

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Publication number
CN113937149A
CN113937149A CN202010670054.4A CN202010670054A CN113937149A CN 113937149 A CN113937149 A CN 113937149A CN 202010670054 A CN202010670054 A CN 202010670054A CN 113937149 A CN113937149 A CN 113937149A
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Prior art keywords
epitaxial layer
type epitaxial
region
semiconductor power
power device
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龚轶
刘伟
毛振东
徐真逸
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to CN202010670054.4A priority Critical patent/CN113937149A/en
Priority to PCT/CN2020/117287 priority patent/WO2022011834A1/en
Publication of CN113937149A publication Critical patent/CN113937149A/en
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Abstract

The invention belongs to the technical field of semiconductor power devices, and particularly discloses a terminal structure of a semiconductor power device and a manufacturing method thereof, wherein the terminal structure comprises the following steps: an n-type epitaxial layer; at least one termination region trench recessed within the n-type epitaxial layer, the termination region trench surrounding a cell region of a semiconductor power device; and the geometric center of the p-type doped region is positioned on one side, far away from the cellular region, of the geometric center of the terminal region groove. The invention can improve the breakdown voltage of the semiconductor power device.

Description

Terminal structure of semiconductor power device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a terminal structure of a semiconductor power device and a manufacturing method thereof.
Background
The semiconductor power device comprises a cell area and a terminal area, wherein the terminal area surrounds the cell area, and the design of the cell area determines the characteristics of the semiconductor power device, such as on-resistance, capacitance, breakdown voltage and the like, but is limited by the effectiveness and the area of the protection design of the terminal area. To ensure the reliability of the semiconductor power device, the voltage breakdown point should fall in the cell region, not in the termination region. In order to reduce the characteristic on-resistance of the semiconductor power device in the prior art, the doping concentration of the n-type epitaxial layer needs to be increased, so that the terminal region is difficult to be depleted in the transverse direction, the withstand voltage of the terminal region is lower than that of the cell region, and the withstand voltage of the semiconductor power device is affected.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a termination structure of a semiconductor power device and a method for manufacturing the same, so as to solve the problem that the withstand voltage of the semiconductor power device in the prior art is difficult to adjust.
To achieve the above object, the present invention provides a terminal structure of a semiconductor power device, including:
an n-type epitaxial layer;
at least one termination region trench recessed within the n-type epitaxial layer, the termination region trench surrounding a cell region of a semiconductor power device;
and the geometric center of the p-type doped region is positioned on one side, far away from the cellular region, of the geometric center of the terminal region groove.
Optionally, the bottom of the termination region trench is lower than the top of the p-type doped region.
Optionally, the device further includes a field oxide layer and a conductive polysilicon layer located in the termination region trench.
Optionally, the conductive polysilicon in at least one of the termination region trenches is externally connected to a source voltage.
Optionally, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located above the first n-type epitaxial layer, and the doping concentrations of the first n-type epitaxial layer and the second n-type epitaxial layer are different.
Optionally, the doping concentration of the second n-type epitaxial layer is greater than the doping concentration of the first n-type epitaxial layer.
Optionally, the p-type doped region is located in the first n-type epitaxial layer.
Optionally, the p-type doped region is located in the first n-type epitaxial layer and extends upward into the second n-type epitaxial layer.
The manufacturing method of the terminal structure of the semiconductor power device comprises the following steps:
forming at least one p-type injection region in the first part of the n-type epitaxial layer, wherein the p-type injection region surrounds a cellular region of the semiconductor power device;
forming an n-type epitaxial layer second division part on the n-type epitaxial layer first division part, wherein the n-type epitaxial layer first division part and the n-type epitaxial layer second division part form an n-type epitaxial layer of the semiconductor power device;
and forming a terminal area groove sunken in the n-type epitaxial layer through a photoetching process and an etching process, wherein the terminal area groove corresponds to the p-type injection area one by one, and the geometric center of the p-type injection area is positioned on one side of the geometric center of the terminal area groove far away from the cellular area.
Optionally, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located above the first n-type epitaxial layer;
the first part of the n-type epitaxial layer is the first n-type epitaxial layer, the second part of the n-type epitaxial layer is the second n-type epitaxial layer, and the doping concentration of the second part of the n-type epitaxial layer is greater than that of the first part of the n-type epitaxial layer.
According to the terminal structure of the semiconductor power device, the p-type doped region is positioned at the bottom of the terminal region groove, and the geometric center of the p-type doped region is positioned on one side, away from the cellular region, of the geometric center of the terminal region groove, so that the breakdown voltage of the terminal region of the semiconductor power device can be improved, and further the withstand voltage and the reliability of the semiconductor power device are improved.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments.
Fig. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided by the present invention;
fig. 2 to fig. 3 are schematic cross-sectional structures of main structures in a manufacturing process of one embodiment of a manufacturing method of a semiconductor power device provided by the present invention.
Detailed Description
The technical solution of the present invention will be fully described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic drawings listed in the accompanying drawings enlarge the thickness of the layers and regions of the present invention, and the listed sizes of the figures do not represent actual sizes.
Fig. 1 is a schematic cross-sectional structure diagram of an embodiment of a termination structure of a semiconductor power device provided by the present invention, and as shown in fig. 1, the termination structure of the semiconductor power device provided by the present invention includes an n-type epitaxial layer 20, the material of the n-type epitaxial layer 20 is usually silicon, and the n-type epitaxial layer 20 is usually formed on an n-type silicon substrate (not shown in fig. 1). At least one termination trench, only three termination trenches are shown by way of example in the embodiment of fig. 1, recessed within the n-type epitaxial layer 20, in which termination trenches field oxide 22 and conductive polysilicon 23 are formed, optionally with at least one conductive polysilicon 23 externally connected to the source voltage. The semiconductor power device includes a cell region and a terminal region, the terminal region surrounds the cell region, and the terminal region structure of the terminal region is only exemplarily shown in the embodiment of the present invention.
And the p-type doped region 21 is positioned in the n-type epitaxial layer 20 and at the bottom of the terminal region trench, and the geometric center of the p-type doped region 21 is positioned on one side of the geometric center of the terminal region trench, which is far away from the cell region. In the terminal region of the semiconductor power device, the highest point of voltage is located on one side of the terminal region groove far away from the cellular region, and the geometric center of the p-type doped region 21 is arranged on one side of the geometric center of the terminal region groove far away from the cellular region, so that the withstand voltage of the terminal region can be improved, and further the withstand voltage and the reliability of the semiconductor power device can be improved.
Optionally, the bottom of the termination region trench may be higher than the top of the p-type doped region 21, that is, the bottom of the termination region trench extends into the p-type doped region 21 (as shown in fig. 1), so that under the condition that the depth of the termination region trench is kept unchanged, the distance between the p-type doped region and the bottom of the n-type epitaxial layer 20 may be increased, and the withstand voltage of the semiconductor power device may be further improved.
Optionally, in the semiconductor power device provided by the present invention, the n-type epitaxial layer 20 may include a first n-type epitaxial layer and a second n-type epitaxial layer (not shown in the figure) located above the first n-type epitaxial layer, and the doping concentrations of the first n-type epitaxial layer and the second n-type epitaxial layer are different. Optionally, the doping concentration of the second n-type epitaxial layer is greater than that of the first n-type epitaxial layer, so that the first n-type epitaxial layer with low doping concentration is used for improving the withstand voltage of the semiconductor power device, and the second n-type epitaxial layer with high doping concentration is used for reducing the on-resistance of the semiconductor power device.
Optionally, when the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer, the bottom of the termination region trench may be located in the second n-type epitaxial layer, or the bottom of the termination region trench may be located in the first n-type epitaxial layer (not shown in the figure), which is not limited in the embodiment of the present invention.
Optionally, when the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer, the p-type doped region may be located in the first n-type epitaxial layer, or the p-type doped region may be located in the first n-type epitaxial layer and extend upward into the second n-type epitaxial layer (not shown in the figure), which is not limited in this embodiment of the present invention.
Fig. 2 to 3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a termination structure of a semiconductor power device provided by the present invention, first, as shown in fig. 2, an n-type epitaxial layer first sub-portion 31 is formed on an n-type substrate 30, then ion implantation is performed to form at least one p-type implantation region 41 in the n-type epitaxial layer first sub-portion 31, the p-type implantation region 41 should surround a cell region (not shown in fig. 2) of the semiconductor power device, and only three p-type implantation regions 41 are exemplarily shown in fig. 2.
Next, as shown in fig. 3, an n-type epitaxial layer second division 32 is formed on the n-type epitaxial layer first division 31, and the n-type epitaxial layer first division 31 and the n-type epitaxial layer second division 32 form an n-type epitaxial layer of the termination structure of the semiconductor power device of the present invention. Preferably, the doping concentration of the n-type epitaxial layer second subsection 32 is greater than the doping concentration of the n-type epitaxial layer first subsection 31, so that the n-type epitaxial layer first subsection 31 is used for improving the withstand voltage of the semiconductor power device, and the n-type epitaxial layer second subsection 32 is used for reducing the on-resistance of the semiconductor power device. And then, forming a terminal region groove 42 recessed in the n-type epitaxial layer through a photoetching process and an etching process, wherein the terminal region groove 42 corresponds to the p-type injection region 41 one by one, and the geometric center of the p-type injection region 41 is positioned on one side, away from the cellular region, of the geometric center of the terminal region groove 42.
Optionally, in the terminal structure of the semiconductor power device according to the embodiment of the present invention, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located above the first n-type epitaxial layer; the first part of the n-type epitaxial layer is a first n-type epitaxial layer, and the second part of the n-type epitaxial layer is a second n-type epitaxial layer.
Finally, the terminal structure of the semiconductor power device of the present invention can be manufactured by a conventional process, and it should be noted that, by controlling the implantation concentration and depth of the p-type implantation region 41, the position of the p-type doped region formed after the diffusion of the p-type implantation region 41 in the subsequent process can be controlled, for example, the p-type doped region may be only located in the first n-type epitaxial layer partition 31, or the p-type doped region may also be located in the first n-type epitaxial layer partition 31 and diffused into the second n-type epitaxial layer partition 32. Meanwhile, through the etching depth of the terminal region trench 42, the top of the p-type doped region formed after the diffusion of the p-type injection region 41 can be higher than the bottom of the terminal region trench, which is equivalent to the fact that the bottom of the terminal region trench extends into the p-type doped region; the top of the p-type doped region formed by the p-type implanted region 41 after diffusion may also be made lower than the bottom of the termination trench.
The terminal structure of the semiconductor power device can be suitable for semiconductor power devices with different grid structures, for example, the grid structure and the source polycrystalline silicon are in an up-and-down position relationship, or the grid structure and the source polycrystalline silicon are in a left-and-right position relationship, meanwhile, in order to match the grid structure in the cell region groove, a grid structure corresponding to the grid structure can be formed in the terminal region groove, and the grid structure in the terminal region groove is arranged in a floating mode or externally connected with source voltage.
The above embodiments and examples are specific supports for the technical ideas of the present invention, and the protection scope of the present invention should not be limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical solutions according to the technical ideas proposed by the present invention still belong to the protection scope of the technical solutions of the present invention.

Claims (10)

1. A termination structure for a semiconductor power device, comprising:
an n-type epitaxial layer;
at least one termination region trench recessed within the n-type epitaxial layer, the termination region trench surrounding a cell region of a semiconductor power device;
and the geometric center of the p-type doped region is positioned on one side, far away from the cellular region, of the geometric center of the terminal region groove.
2. The termination structure of claim 1, wherein a bottom of the termination region trench is lower than a top of the p-type doped region.
3. The termination structure of a semiconductor power device according to claim 1, further comprising a field oxide layer and conductive polysilicon located within said termination region trench.
4. The termination structure of claim 3, wherein at least one of said termination region trenches has conductive polysilicon therein which is external to a source voltage.
5. The termination structure of a semiconductor power device according to claim 1, wherein the n-type epitaxial layer comprises a first n-type epitaxial layer and a second n-type epitaxial layer located over the first n-type epitaxial layer, the first n-type epitaxial layer and the second n-type epitaxial layer having different doping concentrations.
6. The termination structure of a semiconductor power device according to claim 5, wherein the second n-type epitaxial layer has a doping concentration greater than the doping concentration of the first n-type epitaxial layer.
7. The termination structure of a semiconductor power device according to claim 5, wherein the p-type doped region is located within the first n-type epitaxial layer.
8. The termination structure of a semiconductor power device according to claim 5, wherein the p-type doped region is located within the first n-type epitaxial layer and extends up into the second n-type epitaxial layer.
9. A method of fabricating a termination structure for a semiconductor power device, comprising:
forming at least one p-type injection region in the first part of the n-type epitaxial layer, wherein the p-type injection region surrounds a cellular region of the semiconductor power device;
forming an n-type epitaxial layer second division part on the n-type epitaxial layer first division part, wherein the n-type epitaxial layer first division part and the n-type epitaxial layer second division part form an n-type epitaxial layer of the semiconductor power device;
and forming a terminal area groove sunken in the n-type epitaxial layer through a photoetching process and an etching process, wherein the terminal area groove corresponds to the p-type injection area one by one, and the geometric center of the p-type injection area is positioned on one side, far away from the cellular area, of the geometric center of the terminal area groove.
10. The method of fabricating a termination structure for a semiconductor power device according to claim 9, wherein said n-type epitaxial layer comprises a first n-type epitaxial layer and a second n-type epitaxial layer over said first n-type epitaxial layer;
the first part of the n-type epitaxial layer is the first n-type epitaxial layer, the second part of the n-type epitaxial layer is the second n-type epitaxial layer, and the doping concentration of the second part of the n-type epitaxial layer is greater than that of the first part of the n-type epitaxial layer.
CN202010670054.4A 2020-07-13 2020-07-13 Terminal structure of semiconductor power device and manufacturing method thereof Pending CN113937149A (en)

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Application publication date: 20220114