CN203277388U - Quantum field distributed Trench MOSFET groove terminal structure - Google Patents
Quantum field distributed Trench MOSFET groove terminal structure Download PDFInfo
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- CN203277388U CN203277388U CN 201320254968 CN201320254968U CN203277388U CN 203277388 U CN203277388 U CN 203277388U CN 201320254968 CN201320254968 CN 201320254968 CN 201320254968 U CN201320254968 U CN 201320254968U CN 203277388 U CN203277388 U CN 203277388U
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Abstract
Provided is a quantum field distributed Trench MOSFET groove terminal structure which comprises an epitaxial layer, a first isolation groove and a second isolation groove. The first isolation groove is arranged inside the epitaxial layer. The second isolation groove is arranged on one side, which is far from a silicon chip boundary, of the first isolation groove, and is parallel with the first isolation groove. The internal parts of both the first isolation groove and the second isolation groove have polycrystalline silicon electrodes. Gate oxide layers are arranged between the polycrystalline silicon electrodes and the inner walls of the grooves. A short isolation groove is connected between the first isolation groove and the second isolation groove. According to the quantum field distributed Trench MOSFET groove terminal structure, design manner of a conventional terminal structure is changed into a manner that a small groove is adopted to realize connection between isolation grooves. Therefore, the curvature radius of body area edge is eliminated by the structure, and the body area terminal part is changed into parallel plane junction more completely. With the application of the structure, distance difficulties of the junction structure of field board and field limiting ring do not need to be designed, and the chip area is also saved.
Description
Technical field
The utility model belongs to the integrated circuit of field of semiconductor technology and makes the field, relates to the Trench MOSFET groove terminal structure that a kind of quantum field distributes.
Background technology
The people such as D.Ueda have proposed Trench MOSFET structure in 1985, as a kind of novel vertical structure device that grows up on the VDMOS basis, VDMOS compares and possesses lower conducting resistance relatively, low grid leak charge density, thereby have low conducting and switching loss to reach switching speed faster, the raceway groove due to Trench MOSFET is vertical simultaneously, therefore can further improve gully density, reduce chip size, reduce manufacturing cost.
At present, the Trench MOSFET junction termination technique measure terminal technology of mainly using field plate to combine with field limiting ring.
Produce simply although the field limiting ring technology has, can reach the advantage of high breakdown voltage, it is very responsive to interface charge, and the effect of field limiting ring is had a greatly reduced quality.And the Metal field plate technology is not very sensitive to interface charge; and eliminate interface charge when being connected together with main junction electrode to the impact of device surface; but panel edges on the scene place electric field is concentrated, and the electric field that this high potential difference that can the additional guard ring in panel edges on the scene place weakens field plate and substrate causes is concentrated.Thereby the terminal structure that Metal field plate and field limiting ring combine proposed.This field plate and field limiting ring comprehensive combines both advantage.Adopt the device of this structure not only can realize the requirement of high breakdown voltage, and also have reliability preferably.
As shown in Figure 2; a kind of terminal structure sectional arrangement drawing of prior art is shown near silicon chip border 17; the silicon chip boundary vicinity has 3 annular tagmas 25; form three protection structures withstand voltage to improve terminal, the withstand voltage setting as required of the spacing between tagma 25,25 the turning 16 in the tagma; electric field line distribution is concentrated; withstand voltage weak spot between tagma 25 and epitaxial loayer 22 when puncturing, punctures at first herein.Overlook from silicon chip surface, these annular solids districts is positioned at the silicon chip boundary vicinity, surrounds the silicon chip internal structure.
But in the design that many field limiting rings and offset field plate combine, the upper field plate length of each ring and ring spacing determines it is a difficult point.And in high tension apparatus, this structure will take larger chip area, constantly reduces in characteristic size, and today that chip area constantly dwindles, this technology has not had advantage undoubtedly.
The utility model content
Large for overcoming existing terminal technology design difficulty, the technological deficiency that chip occupying area is large, the Trench MOSFET groove terminal structure that the utility model provides a kind of quantum field to distribute.
The Trench MOSFET groove terminal structure that quantum field described in the utility model distributes comprises epitaxial loayer, and is arranged in the first isolation channel of epitaxial loayer and is parallel to the first isolation channel, and is positioned at the first isolation channel near the second isolation channel of silicon chip border one side; The first isolation channel, the second isolation channel degree of depth are identical, and have same structure as described below: there is unsettled field plate inside, between described unsettled field plate and isolation channel inwall, gate oxide is arranged, be connected with short isolation channel between described the first isolation channel and the second isolation channel, the structure of described short isolation channel is identical with the second isolation channel with the first isolation channel, and the unsettled field plate of short isolation channel connects the unsettled field plate of the first isolation channel and the second isolation channel.
Preferably, also comprise and be positioned at the second isolation channel near silicon chip border one side and three isolation channel identical with the second isolation moat structure, be connected with the short isolation channel identical with the second isolation moat structure between described the 3rd isolation channel and the second isolation channel, the unsettled field plate of short isolation channel connects the unsettled field plate of the second isolation channel and the 3rd isolation channel.
Preferably, the short isolation channel between isolation channel has a plurality of, and the distribute spacing of short isolation channel is 3 to 10 times of isolation channel distance.
Preferably, the distribute spacing of short isolation channel is 5 times of isolation channel distance.
Preferably, also possess following feature: also have groove at the first isolation channel away from silicon chip border one side, groove is away from silicon
Sheet border one side has the tagma; Go back active area above the tagma; Also possess isolating oxide layer at silicon chip surface, have with the source region to form the source class contact structures that good ohmic contacts on isolating oxide layer; There is the gate electrode plate groove inside, also has gate oxide between gate electrode plate and trench wall; Described gash depth is identical with isolation channel.
Preferably, described groove possesses one of following at least feature:
A．The gate oxide structure of groove is identical with isolation channel with composition;
B．The gate electrode plate of groove is identical with field plate structure and the composition of isolation channel.
Preferably, the implantation concentration of described source region (27) is than large two orders of magnitude of epitaxial loayer (22) doping content.
Preferably, comprise the substrate that is positioned at the extension below, described resistance substrate rate is 1 ~ 3 ‰ ohmcm.
Adopt the Trench MOSFET groove terminal structure of quantum field distribution described in the utility model, changed the method for designing of original terminal structure.The groove of chip periphery as isolation channel, be connected with minor groove between isolation channel and isolation channel simultaneously, the effect of minor groove is simultaneously to its vertical direction expansion electric field, so just electric field have been carried out the quantization distribution at isolated groove minor groove in the external expansion electric field.This structure has been eliminated the radius of curvature at edge, tagma, and the tagma terminal part is become the parallel plane knot more fully.This structure both need not design field plate and field limiting ring in conjunction with in structure apart from difficult point, but also saved the area of chip.
Description of drawings
Fig. 1 illustrates the silicon chip terminal structure schematic diagram of conventional art;
Fig. 2 illustrates the structural profile schematic diagram of a kind of embodiment of the present utility model;
Fig. 3 illustrates the schematic top plan view of a kind of embodiment of the present utility model;
In each figure, the Reference numeral name is called: 1. the short isolation channel of silicon chip internal structure 3. 15. groove 16. turning 17. silicon chip border 18. the 3rd isolation channel 19. second isolation channel 20. first isolation channel 21. substrate 22. epitaxial loayer 23. gate oxide 24a. gate electrode 24b. suspension field plate 25. tagma 26. ohmic contact regions 27. source region 28. metal contact hole 29. isolating oxide layer 210. metal lead wires.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.
The Trench MOSFET groove terminal structure that quantum field described in the utility model distributes, comprise epitaxial loayer 22, and be arranged in the first isolation channel 20 of epitaxial loayer 22 and be parallel to the first isolation channel, and be positioned at the first isolation channel near the second isolation channel 19 of silicon chip border one side; The first isolation channel, the second isolation channel have same structure as described below: there is unsettled field plate inside, between described unsettled field plate and trench wall, gate oxide is arranged,
Be connected with short isolation channel 3 between described the first isolation channel and the second isolation channel, the structure of described short isolation channel is identical with the second isolation channel with the first isolation channel, and the unsettled field plate of short isolation channel connects the unsettled field plate of the first isolation channel and the second isolation channel.
the utility model is applied to Trench MOSFET groove terminal, Trench MOSFET is as the improvement structure of VDMOS, be applied under hyperbaric environment, when high pressure points to the second isolation channel direction from the first isolation channel, if there is no short isolation channel, electric field line extends to the second isolation channel along first and second isolation channel shortest path from the first isolation channel, comparatively intensive at this direction electric field line, after increasing short isolation channel be connected between the first isolation channel and the second isolation channel, electric field line no longer all points to the second isolation channel from the first isolation channel, the part electric field line will point to short isolation channel, reduced the closeness of electric field line, thereby improved the withstand voltage of terminal structure.
For realizing the withstand voltage purpose of above-mentioned raising, short isolation moat structure is identical with the second isolation channel with the first isolation channel, all consists of by deep-cutting in the epitaxial loayer of silicon chip terminal, and there is unsettled field plate isolation channel inside and is positioned at the inner gate oxide that surrounds unsettled field plate of isolation channel.The unsettled field plate of short isolation channel connects the unsettled field plate of the first isolation channel and the second isolation channel, and the current potential that makes the first isolation channel, the second isolation channel and short isolation channel same gradient place in electric field about equally, realizes the dispersion of electric field line.
Withstand voltage for further improving, can be at the second isolation channel near silicon chip border one side setting three isolation channel 18 identical with the second isolation moat structure, be connected with the short isolation channel 3 identical with the second isolation moat structure between described the 3rd isolation channel and the second isolation channel, the unsettled field plate of short isolation channel connects the unsettled field plate of the second isolation channel and the 3rd isolation channel.The withstand voltage principle of the raising of short isolation channel as hereinbefore,
Be illustrated in figure 3 as the vertical view of a kind of embodiment of the present utility model, between the first isolation channel and the second isolation channel, a plurality of short isolation channels can be set evenly, in general, the distribute spacing of short isolation channel is that the first isolation channel and the second isolation channel distance 3 to 10 times can better be realized improving withstand voltage, it is 5 times that the utility model preferably designs this value, and withstand voltage effect is best.
For realizing better withstand voltage effect, the utility model discloses a kind of power tube structure that utilizes groove to do isolation, as
Shown in Figure 2 also have groove at the first isolation channel away from silicon chip border one side, and groove has the tagma away from silicon chip border one side; Go back active area above the tagma; Also possess isolating oxide layer at silicon chip surface, have with the source region to form the source class contact structures that good ohmic contacts on isolating oxide layer; There is the gate electrode plate groove inside, also has gate oxide between gate electrode plate and trench wall; Described gash depth is identical with isolation channel.
As a rule, groove is darker, and the width of groove is larger, and withstand voltage effect is better.Simultaneously, when growing grid oxic horizon in groove, oxidated layer thickness has certain requirements, and must bear the added voltage of grid and source electrode.So will strictly control thickness and quality during this oxide layer growth.
After groove forms, need to form polysilicon electrode as gate electrode and suspension field plate in groove, and make polysilicon fill the whole inner surfaces of whole groove.During depositing polysilicon, can be at first groove and groove contiguous all surfaces on depositing polysilicon, until fill the whole surface, inside of full two grooves; Subsequently, will do not need the surperficial etching polysilicon that covers of polysilicon fall, polysilicon layer is etched back in groove, and on the surface recessed segment distance.Thereby form gate electrode 24a and unsettled field plate 24b in the first groove.Gate electrode 24a and unsettled field plate 24b form electricity isolation mutually by gate oxide 23 and epitaxial loayer 22.Gate electrode is drawn by conductor deposited material such as polysilicon etc. at gate electrode contact hole place (not shown in FIG.).The effect of unsettled field plate is to expand the power line of PN junction, thereby improves withstand voltage.
Subsequently, form the tagma at groove away from silicon chip border one side injection; Can adopt photomask to block injection, form the tagma 25 of device.The concrete dosage of tagma 25 implanted dopants and energy will decide according to the threshold voltage of this requirement on devices.Inject by the tagma of silicon chip border one side at the first groove subsequently and form the source region; Source region 27 implanted dopant types and tagma type opposite, for example the tagma implanted dopant is N-type, p type impurity is injected in the source region, preferred source region implantation concentration than high two orders of magnitude of concentration of epitaxial loayer 22 to realize device performance preferably.At silicon chip surface deposit isolating oxide layer, isolating oxide layer covers whole device surfaces subsequently, and the local perforate that only picks out at the needs lead-in wire is with the protection device internal structure; The material of isolating oxide layer is preferably BPSG, i.e. the boron-phosphorosilicate glass material.The last source class contact structures that structure contacts with source region formation good ohmic on isolating oxide layer.Conveniently to realize freely connecting of source class current potential.
Be to simplify processing step, the counter structure of each structure of the inside of groove and isolation channel can be identical, to save corresponding operation.For example the gate oxide structure of groove is identical with isolation channel with composition; In manufacture process, the gate oxide of groove and isolation channel can synchronously form simultaneously, and the gate electrode plate of groove can be identical with the field plate structure of isolation channel and composition.
As shown in Figure 2, provide a specific embodiment of the present utility model take substrate as N+ as example.
On substrate 21, growth N epitaxial loayer 22, form device drift region.The resistivity that substrate 21 is heavily doped to N-type impurity is the scope of 1 ~ 3 ‰ ohm.cm, and the N-type impurity doping content of epitaxial loayer 22 decides according to the withstand voltage of this device.Dig dark formation the first groove and be positioned at the first groove near the second groove of the inner side of silicon chip in epitaxial loayer 22.At trenched side-wall growth gate oxide 23a, the thickness of gate oxide is as the criterion can bear grid and source electrode institute making alive.Deposit is mixed with the polysilicon of N-type impurity as gate electrode 24a and unsettled field plate 24b.Form gate electrode 24a and unsettled field plate 24b in groove.Gate electrode 24a and unsettled field plate 24b form electricity isolation mutually by gate oxide 23 and epitaxial loayer 22.
Then utilize photomask to block and inject the tagma 25 that forms device, what tagma 25 was injected is p type impurity, and concrete dosage and energy will decide according to the threshold voltage of this requirement on devices.Reinject and form device source region 27.What source region 27 was injected is N-type impurity, and final concentration gets final product than high two orders of magnitude of concentration of epitaxial loayer 22.Deposit isolating oxide layer 29, material are the BPSG(boron-phosphorosilicate glass).And on isolating oxide layer 29 etching metal contact hole 28.Inject ohmic contact regions 26.What ohmic contact regions 26 injected be p type impurity, and purpose is the resistance that reduces herein with Metal Contact, prevents that in device, opening by mistake of parasitic NPN transistor opened, and this parasitic transistor is in case unlatching, and power MOSFET will not controlled by grid, cause component failure; The Impurity injection concentration of ohmic contact regions gets final product greater than two orders of magnitude of tagma Impurity injection concentration.The depositing metal lead-in wire 210 subsequently, as the source electrode contacting metal of device.
In the Trench MOSFET groove terminal structure manufacture method that quantum field described in the utility model distributes, short isolation channel is identical with the second isolation moat structure with the first isolation channel, and the step of therefore making short isolation channel is synchronizeed with the first isolation channel and the second isolation channel and completed simultaneously.
As previously mentioned, the utility model discloses a kind of power tube structure that utilizes trench isolations, this power tube structure comprises groove, groove is the same with isolation channel, be all to deep-cut to form in epitaxial loayer, there is the gate electrode plate groove inside, also has gate oxide between gate electrode plate and trench wall.Described gash depth is identical with isolation channel, for simplifying technique, the structure of groove is as far as possible identical with isolation channel, for example, the gate oxide structure of groove is identical with isolation channel with composition, the thick oxide layer structure of groove is identical with isolation channel with composition, and the gate electrode plate of groove is identical with field plate structure and the composition of isolation channel.The groove that possesses simultaneously above-mentioned feature can adopt identical step fully with isolation channel during fabrication, and the manufacturing step of described groove all is contained in the manufacturing step of isolation channel.
Adopt the Trench MOSFET groove terminal structure of quantum field distribution described in the utility model, changed the method for designing of original terminal structure.The groove of chip periphery as isolation channel, be connected with minor groove between isolation channel and isolation channel simultaneously, the effect of minor groove is simultaneously to its vertical direction expansion electric field, so just electric field have been carried out the quantization distribution at isolated groove minor groove in the external expansion electric field.This structure has been eliminated the radius of curvature at edge, tagma, and the tagma terminal part is become the parallel plane knot more fully.This structure both need not design field plate and field limiting ring in conjunction with in structure apart from difficult point, but also saved the area of chip.
previously described is each preferred embodiment of the present utility model, preferred implementation in each preferred embodiment is if not obviously contradictory or take a certain preferred implementation as prerequisite, each preferred implementation stack combinations is arbitrarily used, design parameter in described embodiment and embodiment is only the utility model proof procedure for clear statement utility model inventor, be not to limit scope of patent protection of the present utility model, scope of patent protection of the present utility model still is as the criterion with its claims, the equivalent structure that every utilization specification of the present utility model and accompanying drawing content are done changes, in like manner all should be included in protection range of the present utility model.
Claims (8)
1. the Trench MOSFET groove terminal structure that distributes of quantum field, comprise epitaxial loayer (22), and be arranged in first isolation channel (20) of epitaxial loayer (22) and be parallel to the first isolation channel, and be positioned at the first isolation channel near second isolation channel (19) of silicon chip border one side; The first isolation channel, the second isolation channel degree of depth are identical, and have same structure as described below: there is unsettled field plate inside, between described unsettled field plate and isolation channel inwall, gate oxide is arranged, and it is characterized in that:
Be connected with short isolation channel (3) between described the first isolation channel and the second isolation channel, the structure of described short isolation channel is identical with the second isolation channel with the first isolation channel, and the unsettled field plate of short isolation channel connects the unsettled field plate of the first isolation channel and the second isolation channel.
2. the Trench MOSFET groove terminal structure that distributes of quantum field as claimed in claim 1, also comprise and be positioned at the second isolation channel near silicon chip border one side and three isolation channel (18) identical with the second isolation moat structure, be connected with the short isolation channel (3) identical with the second isolation moat structure between described the 3rd isolation channel and the second isolation channel, the unsettled field plate of short isolation channel connects the unsettled field plate of the second isolation channel and the 3rd isolation channel.
3. the Trench MOSFET groove terminal structure that distributes of quantum field as claimed in claim 1, it is characterized in that: the short isolation channel between isolation channel has a plurality of, and the distribute spacing of short isolation channel is 3 to 10 times of isolation channel distance.
4. the Trench MOSFET groove terminal structure that distributes of quantum field as claimed in claim 1, it is characterized in that: the distribute spacing of short isolation channel is 5 times of isolation channel distance.
5. the Trench MOSFET groove terminal structure that distributes of quantum field as claimed in claim 1 also possesses following feature: also have groove at the first isolation channel away from silicon chip border one side, groove has the tagma away from silicon chip border (17) one sides
(25); Go back active area (27) above the tagma;
Also possess isolating oxide layer (29) at silicon chip surface, have with the source region to form the source class contact structures (210) that good ohmic contacts on isolating oxide layer;
There is gate electrode plate (24a) groove inside, also has gate oxide (23) between gate electrode plate and trench wall;
Described gash depth is identical with isolation channel.
6. the Trench MOSFET groove terminal structure that distributes of quantum field as claimed in claim 5, described groove possess one of following at least feature:
A. the gate oxide structure of groove is identical with isolation channel with composition;
B. the gate electrode plate of groove is identical with field plate structure and the composition of isolation channel.
7. the Trench MOSFET groove terminal structure that distributes of quantum field as claimed in claim 5, it is characterized in that: the implantation concentration of described source region (27) is than large two orders of magnitude of epitaxial loayer (22) doping content.
8. the Trench MOSFET groove terminal structure that distributes of quantum field as claimed in claim 1, comprise the substrate that is positioned at the extension below, and it is characterized in that: described resistance substrate rate is 1 ~ 3 ‰ ohmcm.
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| CN 201320254968 CN203277388U (en) | 2013-05-13 | 2013-05-13 | Quantum field distributed Trench MOSFET groove terminal structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103280452A (en) * | 2013-05-13 | 2013-09-04 | 成都瑞芯电子有限公司 | Quantum-field distributed Trench MOSFET (metallic oxide semiconductor field effect transistor) trench termination structure and manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103280452A (en) * | 2013-05-13 | 2013-09-04 | 成都瑞芯电子有限公司 | Quantum-field distributed Trench MOSFET (metallic oxide semiconductor field effect transistor) trench termination structure and manufacturing method |
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Denomination of utility model: Quantum-field distributed Trench MOSFET (metallic oxide semiconductor field effect transistor) trench termination structure and manufacturing method Effective date of registration: 20140325 Granted publication date: 20131106 Pledgee: Sichuan Yong Zhi financing Company limited by guarantee Pledgor: Chengdu Promising-chip Electronic Co., Ltd. Registration number: 2014510000006 |
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Granted publication date: 20131106 Termination date: 20160513 |