WO2022011834A1 - Terminal structure for semiconductor power device and manufacturing method therefor - Google Patents

Terminal structure for semiconductor power device and manufacturing method therefor Download PDF

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WO2022011834A1
WO2022011834A1 PCT/CN2020/117287 CN2020117287W WO2022011834A1 WO 2022011834 A1 WO2022011834 A1 WO 2022011834A1 CN 2020117287 W CN2020117287 W CN 2020117287W WO 2022011834 A1 WO2022011834 A1 WO 2022011834A1
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epitaxial layer
type epitaxial
region
type
termination
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PCT/CN2020/117287
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French (fr)
Chinese (zh)
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龚轶
刘伟
毛振东
徐真逸
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苏州东微半导体有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application belongs to the technical field of semiconductor power devices, for example, a terminal structure of a semiconductor power device and a manufacturing method thereof.
  • the semiconductor power device includes a cell area and a terminal area.
  • the terminal area surrounds the cell area.
  • the design of the cell area determines the on-resistance, capacitance and breakdown voltage of the semiconductor power device, but it is limited by the protection design of the terminal area. effectiveness and area.
  • the voltage breakdown point should fall in the cell region, not the terminal region.
  • it is necessary to increase the doping concentration of the n-type epitaxial layer which makes it difficult for the terminal region to be depleted in the lateral direction, resulting in the withstand voltage of the terminal region being lower than that of the cell region. It affects the withstand voltage of semiconductor power devices.
  • the present application provides a terminal structure of a semiconductor power device, including:
  • termination region trench recessed in the n-type epitaxial layer, the termination region trench surrounding a cell region surrounding the semiconductor power device;
  • a p-type doped region located in the n-type epitaxial layer and located at the bottom of the termination region trench, the geometric center of the p-type doped region is located at the geometric center of the termination region trench and away from the cell region side.
  • the present application also provides a method for manufacturing a terminal structure of a semiconductor power device, including:
  • the p-type implantation region in the first subsection of the n-type epitaxial layer, the p-type implantation region surrounding a cell region surrounding the semiconductor power device;
  • a second subsection of the n-type epitaxial layer is formed over the first subsection of the n-type epitaxial layer, and the first subsection of the n-type epitaxial layer and the second subsection of the n-type epitaxial layer form the n-type epitaxial layer of the semiconductor power device.
  • a termination region trench recessed in the n-type epitaxial layer is formed by a photolithography process and an etching process, the termination region trench corresponds to the p-type implanted region one-to-one, and the geometric center of the p-type implanted region is The geometric center of the trench in the terminal region is located on the side away from the cell region.
  • the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located on the first n-type epitaxial layer;
  • the first subsection of the n-type epitaxial layer is the first n-type epitaxial layer
  • the second subsection of the n-type epitaxial layer is the second n-type epitaxial layer
  • the second subsection of the n-type epitaxial layer The doping concentration of is greater than the doping concentration of the first portion of the n-type epitaxial layer.
  • FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided by the present application
  • 2-3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a semiconductor power device provided by the present application.
  • FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a terminal structure of a semiconductor power device provided by the present application.
  • the terminal structure of the semiconductor power device provided by the present application includes an n-type epitaxial layer 20.
  • the n-type epitaxial layer 20 The material is usually silicon and the n-forming epitaxial layer 20 is usually formed on an n-type silicon substrate (not shown in FIG. 1 ).
  • the semiconductor power device includes a cell area and a terminal area.
  • the terminal area surrounds and surrounds the cell area. In the embodiments of the present application, only the terminal area structure of the terminal area is exemplarily shown.
  • the highest voltage point is located on the side of the trench in the termination region away from the cell region, and the geometric center of the p-type doped region 21 is set at the geometric center of the trench in the termination region away from the cell region.
  • the withstand voltage of the termination region can be improved, thereby improving the withstand voltage and reliability of the semiconductor power device.
  • the bottom of the trench in the termination region can be made higher than the top of the p-type doped region 21, that is, the bottom of the trench in the termination region extends into the p-type doped region 21 (as shown in FIG.
  • the distance between the p-type doped region and the bottom of the n-type epitaxial layer 20 can be increased, thereby improving the withstand voltage of the semiconductor power device.
  • the n-type epitaxial layer 20 may include a first n-type epitaxial layer and a second n-type epitaxial layer (not shown in the figure) located on the first n-type epitaxial layer, The doping concentrations of the first n-type epitaxial layer and the second n-type epitaxial layer are different.
  • the doping concentration of the second n-type epitaxial layer is greater than the doping concentration of the first n-type epitaxial layer, so that the first n-type epitaxial layer with low doping concentration is set to improve the withstand voltage of the semiconductor power device,
  • the highly doped second n-type epitaxial layer is provided to reduce the on-resistance of the semiconductor power device.
  • the bottom of the trench in the termination region may be located in the second n-type epitaxial layer, or may be the bottom of the trench in the termination region. It is located in the first n-type epitaxial layer (not shown in the figure), which is not limited in this embodiment of the present application.
  • the p-type doped region may be located in the first n-type epitaxial layer, or the p-type doped region may be located in the first n-type epitaxial layer.
  • One n-type epitaxial layer extends upward to the second n-type epitaxial layer (not shown in the figure), which is not limited in this embodiment of the present application.
  • FIGS. 2 to 3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of the method for manufacturing a terminal structure of a semiconductor power device provided by the present application.
  • an n-type substrate 30 is formed.
  • the p-type implantation region 41 should surround the cell region surrounding the semiconductor power device ( Not shown in FIG. 2 ), only three p-type implanted regions 41 are exemplarily shown in FIG. 2 .
  • a second n-type epitaxial layer 32 , a first n-type epitaxial layer 31 and a second n-type epitaxial layer are formed on the first n-type epitaxial layer 31 32 forms the n-type epitaxial layer of the termination structure of the semiconductor power device of the present application.
  • the doping concentration of the second sub-section 32 of the n-type epitaxial layer is greater than the doping concentration of the first sub-section 31 of the n-type epitaxial layer, so that the first sub-section 31 of the n-type epitaxial layer is configured to improve the durability of the semiconductor power device.
  • the second sub-section 32 of the n-type epitaxial layer is configured to reduce the on-resistance of the semiconductor power device. Then, a terminal region trench 42 recessed in the n-type epitaxial layer is formed through a photolithography process and an etching process.
  • the termination region trench 42 corresponds to the p-type implantation region 41 one-to-one, and the geometric center of the p-type implantation region 41 The geometric center of the trench 42 in the termination region is on the side away from the cell region.
  • the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located on the first n-type epitaxial layer; the n-type epitaxial layer The first subsection is a first n-type epitaxial layer, and the second subsection of the n-type epitaxial layer is a second n-type epitaxial layer.
  • the terminal structure of the semiconductor power device of the present application can be manufactured by conventional processes. It should be noted that by controlling the implantation concentration and depth of the p-type implantation region 41, the diffusion of the p-type implantation region 41 in the subsequent process can be controlled.
  • the position of the p-type doped region formed later, for example, the p-type doped region may only be located in the first sub-section 31 of the n-type epitaxial layer, or the p-type doped region may also be located in the first sub-section 31 of the n-type epitaxial layer and diffuse into the second sub-section 32 of the n-type epitaxial layer.
  • the top of the p-type doped region formed by the diffusion of the p-type implant region 41 can be higher than the bottom of the trench in the termination region, that is, the bottom of the trench in the termination region is lower than the bottom of the trench in the termination region.
  • the top of the p-type doped region is equivalent to extending the bottom of the trench in the termination region to the p-type doped region; it is also possible to make the top of the p-type doped region formed by the diffusion of the p-type implanted region 41 lower than the trench in the termination region bottom of.
  • the terminal structure of the semiconductor power device of the present application can be applied to semiconductor power devices with different gate structures.
  • the gate structure and the source polysilicon are in an up-down positional relationship, or the gate structure and the source polysilicon are in a left-right positional relationship.
  • a corresponding gate structure can also be formed in the termination region trench, and the gate structure in the termination region trench should be set floating or externally connected to a source voltage.
  • the p-type doped region is located at the bottom of the trench in the termination region and the geometric center of the p-type doped region is located on the side of the geometric center of the termination region trench away from the cell region, This can improve the breakdown voltage of the terminal region of the semiconductor power device, thereby improving the withstand voltage and reliability of the semiconductor power device.

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Abstract

The present application belongs to the technical field of semiconductor power devices. Disclosed are a terminal structure for a semiconductor power device and a manufacturing method therefor. The terminal structure comprises: an n-type epitaxial layer; at least one terminal area trench which is recessed within the n-type epitaxial layer, the terminal area trench encircling a cellular area that surrounds a semiconductor power device; and a p-type doped area which is located in the n-type epitaxial layer and located at the bottom of the terminal area trench, the geometric center of the p-type doped area being located at the side of the geometric center of the terminal area trench that is away from the cellular area.

Description

半导体功率器件的终端结构及其制造方法Termination structure of semiconductor power device and manufacturing method thereof
本申请要求在2020年7月13日提交中国专利局、申请号为202010670054.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。This application claims the priority of the Chinese Patent Application No. 202010670054.4 filed with the China Patent Office on July 13, 2020, the entire contents of which are incorporated herein by reference.
技术领域technical field
本申请属于半导体功率器件技术领域，例如一种半导体功率器件的终端结构及其制造方法。The present application belongs to the technical field of semiconductor power devices, for example, a terminal structure of a semiconductor power device and a manufacturing method thereof.
背景技术Background technique
半导体功率器件包括元胞区和终端区，终端区环绕包围元胞区，元胞区的设计决定半导体功率器件的导通电阻、电容以及击穿电压等特性，但它受限于终端区保护设计的有效性和面积。为保证半导体功率器件的可靠性，电压击穿点应落在元胞区，而不是终端区。相关技术中的半导体功率器件为了降低特征导通电阻，需要提高n型外延层的掺杂浓度，这使得终端区在横向上难以耗尽，导致终端区耐压低于元胞区耐压，从而影响了半导体功率器件的耐压。The semiconductor power device includes a cell area and a terminal area. The terminal area surrounds the cell area. The design of the cell area determines the on-resistance, capacitance and breakdown voltage of the semiconductor power device, but it is limited by the protection design of the terminal area. effectiveness and area. In order to ensure the reliability of semiconductor power devices, the voltage breakdown point should fall in the cell region, not the terminal region. In order to reduce the characteristic on-resistance of semiconductor power devices in the related art, it is necessary to increase the doping concentration of the n-type epitaxial layer, which makes it difficult for the terminal region to be depleted in the lateral direction, resulting in the withstand voltage of the terminal region being lower than that of the cell region. It affects the withstand voltage of semiconductor power devices.
发明内容SUMMARY OF THE INVENTION
本申请提供一种半导体功率器件的终端结构及其制造方法，以避免相关技术中的半导体功率器件的耐压难以调整的情况。The present application provides a terminal structure of a semiconductor power device and a manufacturing method thereof, so as to avoid the situation that the withstand voltage of the semiconductor power device in the related art is difficult to adjust.
本申请提供了一种半导体功率器件的终端结构，包括：The present application provides a terminal structure of a semiconductor power device, including:
n型外延层；n-type epitaxial layer;
凹陷在所述n型外延层内的至少一个终端区沟槽，所述终端区沟槽环绕包围半导体功率器件的元胞区；at least one termination region trench recessed in the n-type epitaxial layer, the termination region trench surrounding a cell region surrounding the semiconductor power device;
位于所述n型外延层内且位于所述终端区沟槽底部的p型掺杂区，所述p型掺杂区的几何中心位于所述终端区沟槽的几何中心远离所述元胞区的一侧。a p-type doped region located in the n-type epitaxial layer and located at the bottom of the termination region trench, the geometric center of the p-type doped region is located at the geometric center of the termination region trench and away from the cell region side.
本申请还提供了一种半导体功率器件的终端结构的制造方法，包括：The present application also provides a method for manufacturing a terminal structure of a semiconductor power device, including:
在n型外延层第一分部内形成至少一个p型注入区，所述p型注入区环绕包围半导体功率器件的元胞区；forming at least one p-type implantation region in the first subsection of the n-type epitaxial layer, the p-type implantation region surrounding a cell region surrounding the semiconductor power device;
在所述n型外延层第一分部之上形成n型外延层第二分部，所述n型外延层第一分部和所述n型外延层第二分部形成半导体功率器件的n型外延层；A second subsection of the n-type epitaxial layer is formed over the first subsection of the n-type epitaxial layer, and the first subsection of the n-type epitaxial layer and the second subsection of the n-type epitaxial layer form the n-type epitaxial layer of the semiconductor power device. type epitaxial layer;
通过光刻工艺和刻蚀工艺形成凹陷在所述n型外延层内的终端区沟槽，所述终端区沟槽与所述p型注入区一一对应，所述p型注入区的几何中心位于所述终端区沟槽的几何中心远离所述元胞区的一侧。A termination region trench recessed in the n-type epitaxial layer is formed by a photolithography process and an etching process, the termination region trench corresponds to the p-type implanted region one-to-one, and the geometric center of the p-type implanted region is The geometric center of the trench in the terminal region is located on the side away from the cell region.
可选的，所述n型外延层包括第一n型外延层和位于所述第一n型外延层之上的第二n型外延层；Optionally, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located on the first n-type epitaxial layer;
所述n型外延层第一分部为所述第一n型外延层，所述n型外延层第二分部为所述第二n型外延层，所述n型外延层第二分部的掺杂浓度大于所述n型外延层第一分部的掺杂浓度。The first subsection of the n-type epitaxial layer is the first n-type epitaxial layer, the second subsection of the n-type epitaxial layer is the second n-type epitaxial layer, and the second subsection of the n-type epitaxial layer The doping concentration of is greater than the doping concentration of the first portion of the n-type epitaxial layer.
附图说明Description of drawings
图1是本申请提供的半导体功率器件的一个实施例的剖面结构示意图；1 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided by the present application;
图2-图3是本申请提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。2-3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a semiconductor power device provided by the present application.
具体实施方式detailed description
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出至少一个其它元件或其组合的存在或添加。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。The technical solutions of the present application will be completely described below in specific manners with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, embodiments of the present application. It should be understood that terms such as "having", "comprising", and "including" as used herein do not assign the presence or addition of at least one other element or combination thereof. Meanwhile, in order to clearly illustrate the specific embodiments of the present application, the schematic diagrams listed in the accompanying drawings of the specification have enlarged the thicknesses of the layers and regions described in the present application, and the sizes of the listed figures do not represent actual sizes.
图1是本申请提供的半导体功率器件的终端结构的一个实施例的剖面结构示意图，如图1所示，本申请提供的半导体功率器件的终端结构包括n型外延层20，n型外延层20的材质通常为硅且n形成外延层20通常形成于n型硅衬底(图1中未示出)之上。凹陷在n型外延层20内的至少一个终端区沟槽，在图1的实施例中，仅示例性的示出了三个终端区沟槽，在终端区沟槽形成有场氧化层22和导电多晶硅23，可选的，应至少有一个终端区沟槽内的导电多晶硅23外接源极电压。半导体功率器件包括元胞区和终端区，终端区环绕包围元胞区，在本申请实施例中仅示例性的示出了终端区的终端区结构。FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a terminal structure of a semiconductor power device provided by the present application. As shown in FIG. 1 , the terminal structure of the semiconductor power device provided by the present application includes an n-type epitaxial layer 20. The n-type epitaxial layer 20 The material is usually silicon and the n-forming epitaxial layer 20 is usually formed on an n-type silicon substrate (not shown in FIG. 1 ). At least one termination region trench recessed in the n-type epitaxial layer 20, in the embodiment of FIG. 1, only three termination region trenches are exemplarily shown, and field oxide layers 22 and 22 are formed in the termination region trenches. The conductive polysilicon 23, optionally, should have at least one conductive polysilicon 23 in the trench in the termination region connected to a source voltage. The semiconductor power device includes a cell area and a terminal area. The terminal area surrounds and surrounds the cell area. In the embodiments of the present application, only the terminal area structure of the terminal area is exemplarily shown.
位于n型外延层20内且位于终端区沟槽底部的p型掺杂区21，p型掺杂区21的几何中心位于所述终端区沟槽的几何中心远离所述元胞区的一侧。在半导体功率器件的终端区内，电压最高点位于终端区沟槽的远离元胞区的一侧，将p型掺杂区21的几何中心设置在终端区沟槽的几何中心远离元胞区的一侧，可以提高终端区的耐压，进而可以提高半导体功率器件的耐压和可靠性。A p-type doped region 21 located in the n-type epitaxial layer 20 and located at the bottom of the trench in the termination region, the geometric center of the p-type doped region 21 is located on the side of the geometric center of the trench in the termination region away from the cell region . In the termination region of the semiconductor power device, the highest voltage point is located on the side of the trench in the termination region away from the cell region, and the geometric center of the p-type doped region 21 is set at the geometric center of the trench in the termination region away from the cell region. On one side, the withstand voltage of the termination region can be improved, thereby improving the withstand voltage and reliability of the semiconductor power device.
可选的，可以使得终端区沟槽的底部高于p型掺杂区21的顶部，即相当于终端区沟槽底部延伸至p型掺杂区21内(如图1所示)，这样在保持终端区沟槽的深度不变的条件下，可以增大p型掺杂区与n型外延层20的底部之间的距离，提高半导体功率器件的耐压。Optionally, the bottom of the trench in the termination region can be made higher than the top of the p-type doped region 21, that is, the bottom of the trench in the termination region extends into the p-type doped region 21 (as shown in FIG. Under the condition that the depth of the trench in the termination region remains unchanged, the distance between the p-type doped region and the bottom of the n-type epitaxial layer 20 can be increased, thereby improving the withstand voltage of the semiconductor power device.
可选的，本申请提供的半导体功率器件，n型外延层20可以包括第一n型外延层和位于第一n型外延层之上的第二n型外延层(图中未示出)，第一n型外延层和第二n型外延层的掺杂浓度不同。可选的，第二n型外延层的掺杂浓度大于第一n型外延层的掺杂浓度，由此，低掺杂浓度的第一n型外延层设置为提高半导体功率器件的耐压，高掺杂浓度的第二n型外延层设置为降低半导体功率器件的导通电阻。Optionally, in the semiconductor power device provided by the present application, the n-type epitaxial layer 20 may include a first n-type epitaxial layer and a second n-type epitaxial layer (not shown in the figure) located on the first n-type epitaxial layer, The doping concentrations of the first n-type epitaxial layer and the second n-type epitaxial layer are different. Optionally, the doping concentration of the second n-type epitaxial layer is greater than the doping concentration of the first n-type epitaxial layer, so that the first n-type epitaxial layer with low doping concentration is set to improve the withstand voltage of the semiconductor power device, The highly doped second n-type epitaxial layer is provided to reduce the on-resistance of the semiconductor power device.
可选的，当n型外延层包括第一n型外延层和第二n型外延层时，终端区沟槽的底部可以位于第二n型外延层内，也可以是终端区沟槽的底部位于第一n 型外延层内(图中未示出)，本申请实施例对此不进行限定。Optionally, when the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer, the bottom of the trench in the termination region may be located in the second n-type epitaxial layer, or may be the bottom of the trench in the termination region. It is located in the first n-type epitaxial layer (not shown in the figure), which is not limited in this embodiment of the present application.
可选的，当n型外延层包括第一n型外延层和第二n型外延层时，p型掺杂区可以位于第一n型外延层内，也可以是p型掺杂区位于第一n型外延层内并向上延伸至第二n型外延层内(图中未示出)，本申请实施例对此不进行限定。Optionally, when the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer, the p-type doped region may be located in the first n-type epitaxial layer, or the p-type doped region may be located in the first n-type epitaxial layer. One n-type epitaxial layer extends upward to the second n-type epitaxial layer (not shown in the figure), which is not limited in this embodiment of the present application.
图2至图3是本申请提供的半导体功率器件的终端结构的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图，首先如图2所示，在n型衬底30上形成n型外延层第一分部31，然后进行离子注入在n型外延层第一分部31内形成至少一个p型注入区41，p型注入区41应环绕包围半导体功率器件的元胞区(图2中未示出)，在图2中仅示例性的示出了三个p型注入区41。FIGS. 2 to 3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of the method for manufacturing a terminal structure of a semiconductor power device provided by the present application. First, as shown in FIG. 2 , an n-type substrate 30 is formed. The first subsection 31 of the n-type epitaxial layer, and then ion implantation is performed to form at least one p-type implantation region 41 in the first subsection 31 of the n-type epitaxial layer. The p-type implantation region 41 should surround the cell region surrounding the semiconductor power device ( Not shown in FIG. 2 ), only three p-type implanted regions 41 are exemplarily shown in FIG. 2 .
接下来，如图3所示，在n型外延层第一分部31之上形成n型外延层第二分部32，n型外延层第一分部31和n型外延层第二分部32形成本申请的半导体功率器件的终端结构的n型外延层。示例性的，n型外延层第二分部32的掺杂浓度大于n型外延层第一分部31的掺杂浓度，从而n型外延层第一分部31设置为提高半导体功率器件的耐压，n型外延层第二分部32设置为降低半导体功率器件的导通电阻。然后，通过光刻工艺和刻蚀工艺形成凹陷在所述n型外延层内的终端区沟槽42，终端区沟槽42与p型注入区41一一对应，p型注入区41的几何中心位于终端区沟槽42的几何中心远离元胞区的一侧。Next, as shown in FIG. 3 , a second n-type epitaxial layer 32 , a first n-type epitaxial layer 31 and a second n-type epitaxial layer are formed on the first n-type epitaxial layer 31 32 forms the n-type epitaxial layer of the termination structure of the semiconductor power device of the present application. Exemplarily, the doping concentration of the second sub-section 32 of the n-type epitaxial layer is greater than the doping concentration of the first sub-section 31 of the n-type epitaxial layer, so that the first sub-section 31 of the n-type epitaxial layer is configured to improve the durability of the semiconductor power device. The second sub-section 32 of the n-type epitaxial layer is configured to reduce the on-resistance of the semiconductor power device. Then, a terminal region trench 42 recessed in the n-type epitaxial layer is formed through a photolithography process and an etching process. The termination region trench 42 corresponds to the p-type implantation region 41 one-to-one, and the geometric center of the p-type implantation region 41 The geometric center of the trench 42 in the termination region is on the side away from the cell region.
可选的，本申请实施例的半导体功率器件的终端结构中，n型外延层包括第一n型外延层和位于第一n型外延层之上的第二n型外延层；n型外延层第一分部为第一n型外延层，n型外延层第二分部为第二n型外延层。Optionally, in the terminal structure of the semiconductor power device according to the embodiment of the present application, the n-type epitaxial layer includes a first n-type epitaxial layer and a second n-type epitaxial layer located on the first n-type epitaxial layer; the n-type epitaxial layer The first subsection is a first n-type epitaxial layer, and the second subsection of the n-type epitaxial layer is a second n-type epitaxial layer.
最后，通过常规工艺即可制造得到本申请的半导体功率器件的终端结构，需要说明的是，通过控制p型注入区41的注入浓度和深度，可以控制在后续工艺中p型注入区41在扩散后形成的p型掺杂区的位置，如p型掺杂区可以仅位于n型外延层第一分部31内，或者p型掺杂区也可以位于n型外延层第一分部31内并扩散至n型外延层第二分部32内。同时，通过终端区沟槽42的刻蚀深 度，可以使得p型注入区41在扩散后形成的p型掺杂区的顶部高于终端区沟槽的底部，即终端区沟槽的底部低于p型掺杂区的顶部，相当于终端区沟槽底部延伸至p型掺杂区内；也可以使得p型注入区41在扩散后形成的p型掺杂区的顶部低于终端区沟槽的底部。Finally, the terminal structure of the semiconductor power device of the present application can be manufactured by conventional processes. It should be noted that by controlling the implantation concentration and depth of the p-type implantation region 41, the diffusion of the p-type implantation region 41 in the subsequent process can be controlled. The position of the p-type doped region formed later, for example, the p-type doped region may only be located in the first sub-section 31 of the n-type epitaxial layer, or the p-type doped region may also be located in the first sub-section 31 of the n-type epitaxial layer and diffuse into the second sub-section 32 of the n-type epitaxial layer. At the same time, through the etching depth of the trench 42 in the termination region, the top of the p-type doped region formed by the diffusion of the p-type implant region 41 can be higher than the bottom of the trench in the termination region, that is, the bottom of the trench in the termination region is lower than the bottom of the trench in the termination region. The top of the p-type doped region is equivalent to extending the bottom of the trench in the termination region to the p-type doped region; it is also possible to make the top of the p-type doped region formed by the diffusion of the p-type implanted region 41 lower than the trench in the termination region bottom of.
本申请的半导体功率器件的终端结构可以适用于不同的栅极结构的半导体功率器件，如栅极结构和源极多晶硅为上下位置关系，或者栅极结构和源极多晶硅为左右位置关系，同时为了匹配元胞区沟槽内的栅极结构，在终端区沟槽内也可以形成与之相对应的栅极结构，终端区沟槽内的栅极结构应浮空设置或外接源极电压。The terminal structure of the semiconductor power device of the present application can be applied to semiconductor power devices with different gate structures. For example, the gate structure and the source polysilicon are in an up-down positional relationship, or the gate structure and the source polysilicon are in a left-right positional relationship. At the same time, in order to Matching the gate structure in the cell region trench, a corresponding gate structure can also be formed in the termination region trench, and the gate structure in the termination region trench should be set floating or externally connected to a source voltage.
本申请提供的半导体功率器件的终端结构，p型掺杂区位于终端区沟槽的底部且p型掺杂区的几何中心位于所述终端区沟槽的几何中心远离元胞区的一侧，这能够提高半导体功率器件的终端区的击穿电压，进而提高半导体功率器件的耐压和可靠性。In the termination structure of the semiconductor power device provided by the present application, the p-type doped region is located at the bottom of the trench in the termination region and the geometric center of the p-type doped region is located on the side of the geometric center of the termination region trench away from the cell region, This can improve the breakdown voltage of the terminal region of the semiconductor power device, thereby improving the withstand voltage and reliability of the semiconductor power device.

Claims (10)

  1. 半导体功率器件的终端结构，包括：Termination structures for semiconductor power devices, including:
    n型外延层；n-type epitaxial layer;
    凹陷在所述n型外延层内的至少一个终端区沟槽，所述终端区沟槽环绕包围半导体功率器件的元胞区；at least one termination region trench recessed in the n-type epitaxial layer, the termination region trench surrounding a cell region surrounding the semiconductor power device;
    位于所述n型外延层内且位于所述终端区沟槽底部的p型掺杂区，所述p型掺杂区的几何中心位于所述终端区沟槽的几何中心远离所述元胞区的一侧。a p-type doped region located in the n-type epitaxial layer and located at the bottom of the termination region trench, the geometric center of the p-type doped region is located at the geometric center of the termination region trench and away from the cell region side.
  2. 如权利要求1所述的终端结构，其中，所述终端区沟槽的底部低于所述p型掺杂区的顶部。The termination structure of claim 1, wherein a bottom of the termination region trench is lower than a top of the p-type doped region.
  3. 如权利要求1所述的终端结构，还包括位于所述终端区沟槽内的场氧化层和导电多晶硅。The termination structure of claim 1, further comprising a field oxide layer and conductive polysilicon within the termination region trenches.
  4. 如权利要求3所述的终端结构，其中，至少有一个所述终端区沟槽内的导电多晶硅外接源极电压。4. The termination structure of claim 3, wherein at least one of the conductive polysilicon in the trenches in the termination region is connected to a source voltage.
  5. 如权利要求1所述的终端结构，其中，所述n型外延层包括第一n型外延层和位于所述第一n型外延层之上的第二n型外延层，所述第一n型外延层和所述第二n型外延层的掺杂浓度不同。The termination structure of claim 1, wherein the n-type epitaxial layer comprises a first n-type epitaxial layer and a second n-type epitaxial layer over the first n-type epitaxial layer, the first n-type epitaxial layer The doping concentrations of the n-type epitaxial layer and the second n-type epitaxial layer are different.
  6. 如权利要求5所述的终端结构，其中，所述第二n型外延层的掺杂浓度大于所述第一n型外延层的掺杂浓度。6. The termination structure of claim 5, wherein a doping concentration of the second n-type epitaxial layer is greater than a doping concentration of the first n-type epitaxial layer.
  7. 如权利要求5所述的终端结构，其中，所述p型掺杂区位于所述第一n型外延层内。6. The termination structure of claim 5, wherein the p-type doped region is located within the first n-type epitaxial layer.
  8. 如权利要求5所述的终端结构，其中，所述p型掺杂区位于所述第一n型外延层内并向上延伸至所述第二n型外延层内。6. The termination structure of claim 5, wherein the p-type doped region is located within the first n-type epitaxial layer and extends upward into the second n-type epitaxial layer.
  9. 半导体功率器件的终端结构的制造方法，包括：A method of manufacturing a terminal structure of a semiconductor power device, comprising:
    在n型外延层第一分部内形成至少一个p型注入区，所述p型注入区环绕包围半导体功率器件的元胞区；forming at least one p-type implantation region in the first subsection of the n-type epitaxial layer, the p-type implantation region surrounding a cell region surrounding the semiconductor power device;
    在所述n型外延层第一分部之上形成n型外延层第二分部，所述n型外延层第一分部和所述n型外延层第二分部形成半导体功率器件的n型外延层；A second subsection of the n-type epitaxial layer is formed over the first subsection of the n-type epitaxial layer, and the first subsection of the n-type epitaxial layer and the second subsection of the n-type epitaxial layer form the n-type epitaxial layer of the semiconductor power device. type epitaxial layer;
    通过光刻工艺和刻蚀工艺形成凹陷在所述n型外延层内的终端区沟槽，所述终端区沟槽与所述p型注入区一一对应，所述p型注入区的几何中心位于所述终端区沟槽的几何中心的远离所述元胞区的一侧。A termination region trench recessed in the n-type epitaxial layer is formed by a photolithography process and an etching process, the termination region trench corresponds to the p-type implanted region one-to-one, and the geometric center of the p-type implanted region is is located on the side of the geometric center of the trench in the termination region away from the cell region.
  10. 如权利要求9所述的方法，其中，所述n型外延层包括第一n型外延层和位于所述第一n型外延层之上的第二n型外延层；The method of claim 9, wherein the n-type epitaxial layer comprises a first n-type epitaxial layer and a second n-type epitaxial layer overlying the first n-type epitaxial layer;
    所述n型外延层第一分部为所述第一n型外延层，所述n型外延层第二分部为所述第二n型外延层，所述n型外延层第二分部的掺杂浓度大于所述n型外延层第一分部的掺杂浓度。The first subsection of the n-type epitaxial layer is the first n-type epitaxial layer, the second subsection of the n-type epitaxial layer is the second n-type epitaxial layer, and the second subsection of the n-type epitaxial layer The doping concentration of is greater than the doping concentration of the first portion of the n-type epitaxial layer.
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