CN113014270B - Partially folded polarization code decoder with configurable code length - Google Patents
Partially folded polarization code decoder with configurable code length Download PDFInfo
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Abstract
A partially folded polar code decoder with a configurable code length, comprising: two left information processing unit arrays, two right information processing unit arrays, an information exchange storage unit and a code length configuration control unit, wherein: the information exchange storage unit stores the intermediate information calculated by the information processing unit arrays for next iteration, and the code length configuration control unit configures the four information processing unit arrays according to different code lengths and adopts different shift registers to improve the clock frequency. The invention can realize the decoding of the polarization codes under different code length configurations, can support the configuration of different code lengths and the simultaneous decoding of multiple users, realizes the performance of high throughput and low time delay, and meets the application scene of 5G.
Description
Technical Field
The invention relates to a decoding technology in the field of wireless communication, in particular to a partially folded polarization code decoder with configurable code length, which can be applied to a control channel in a 5G eMB scene.
Background
There are two main decoding algorithms for polar codes: the Belief Propagation (BP) algorithm and the Serial Cancellation (SC) algorithm. The two algorithms have the same complexity, the main difference being the trade-off between decoding latency and hardware resource usage. The former has extremely low decoding time delay, high throughput rate and more resource usage; the latter uses less hardware resources, but the decoding time is prolonged and the throughput rate is low. In the environment of a 5G high-reliability low-delay (URLLC) and multi-user multi-input and multi-output (MU-MIMO) system in the future, the BP algorithm has certain advantages. However, the existing BP algorithm hardware has a complex implementation structure, occupies high hardware resources, and has low utilization rate and high requirement on clock frequency.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a partially folded polar code decoder with configurable code length, which performs data flow control on the input and information interaction storage of a processing unit array through a controller module, thereby realizing polar code decoding under different code length configurations, supporting different code length configurations and multi-user simultaneous decoding, realizing high throughput rate and low time delay performance and meeting the application scene of 5G.
The invention is realized by the following technical scheme:
the invention relates to a partial folding polarization code decoder with configurable code length, which comprises: two left information processing unit arrays, two right information processing unit arrays, an information exchange storage unit, and a code length configuration control unit, wherein: the information exchange storage unit stores the intermediate information calculated by the information processing unit arrays for next iteration, and the code length configuration control unit configures the four information processing unit arrays according to different code lengths and adopts different shift registers to improve the clock frequency.
The replacement cache and the two selectors are provided, wherein the first selector selects the initial information and the output of the information processing unit array and the replacement cache from the same direction, the second selector selects the information exchange storage unit and the output of the information processing unit array and the replacement cache from the opposite direction, the replacement cache is used for receiving the receiving result from the respective information processing unit array and outputting the left information or the right information for finishing the information index arrangement to the first selector, and the information processing unit array to which the replacement cache belongs is respectively connected with the first selectorReceiving left information or right information from the first selector and the second selector, and obtaining a result through BP decoding calculation, namely:
wherein: g (a, b) ═ sign (a) sign (b) min (| a |, | b |), L is information propagating from right to left, R is information propagating from left to right, subscripts i, j are information indexes, respectively, and superscript t is the current iteration number.
Registers are additionally arranged at the input end of the information processing unit array and behind the internal adder, and a two-stage flow design architecture is adopted to improve the clock frequency.
The shift register is internally pre-stored with control information of the first selector, the second selector and the information exchange storage unit under the condition of different code lengths, the control information is directly output to the first selector and the second selector for control, or is used as a gate control signal to control the self-increment operation of the address register, and the register signal is output to the information exchange storage unit.
Technical effects
The invention integrally solves the defects that the prior art can not carry out different code length decoding and multi-user decoding on the polar code decoder; compared with the prior art, the invention enables a plurality of short code words to be decoded simultaneously in the factor graph of one long code word, and the long code word can be decoded in the factor graph of the short code word, so that the decoding time is short, the throughput rate is high, and the chip area and the power consumption are moderate.
Drawings
FIG. 1 is a schematic diagram of the present invention;
FIG. 2 is a timing diagram of a long codeword (right half) and a short codeword (left half) according to an embodiment;
FIG. 3 is a diagram illustrating a coding factor graph of a polarization code;
FIG. 4 is a diagram illustrating a BP decoding factor graph of a polar code;
FIG. 5 is a schematic diagram of a Processing Element (PE) in the BP decoding architecture;
FIG. 6 is a diagram of coding two N's in a factor graph with N-8 CW A short code diagram of 4;
FIG. 7 is a diagram of coding an N in a factor graph with N being 8 CW A long code diagram of 16;
FIG. 8 is a schematic diagram of the data flow around the first left information handling unit array;
fig. 9 is a schematic diagram of an implementation of a shift register in the code length configuration control unit.
Detailed Description
As shown in fig. 1, the present embodiment relates to a code length configurable partially folded polarization code decoder applicable to a control channel in a 5G eMBB scenario, including: two Left information Processing Unit arrays LPU (Left-message Processing Unit) Array1, LPU Array2, two Right information Processing Unit arrays RPU (Right-message Processing Unit) Array1, RPU Array2, information exchange storage Unit mx (message ex change), and code length configuration control Unit Config Ctrl, wherein: 512 information processing units PE are arranged in each information processing unit array and used for calculating a left information calculation formula or a right information calculation formula, the information processing unit arrays adopt two-stage flow design to improve clock frequency, meanwhile, a replacement Buffer is arranged for information processing of long code words, MX stores intermediate information calculated by the information processing unit arrays and used for next iteration, a code length configuration control unit Config Ctrl configures four information processing unit arrays according to different code lengths, and different Shift registers are adopted to improve clock frequency, as shown in FIGS. 8 and 9.
As shown in fig. 8, there are a first left information processing unit array and two selectors arranged around the first left information processing unit array, wherein: the first selector provides left information for the left information processing unit array, wherein the left information is from initial information or from left information of common code words and short code words which are calculated by the left information processing unit array or from output of long code words of the replacement cache which finishes index sorting; the second selector provides the left information processing unit array with right information from the right information stored in the information exchange storage unit after the last iteration is completed or from the right information of the common code word and the short code word which are calculated by the other right information processing unit array or from the output of the long code word of the replacement cache corresponding to the right information processing unit array.
The first selector and the second selector are controlled by a shift register in the code length configuration control unit.
As shown in fig. 9, the address registers connected to the shift register pre-store bit information, and different shift registers represent configurations with different code lengths.
A pair of selectors are arranged at two sides of the shift register, and when the bit output by the shift register at any moment is 0, the output selector selects an upper-side passage, namely the address at the next moment is kept unchanged; otherwise the selector selects the following path, i.e. the address at the next instant is self-added or self-subtracted on the basis of that instant.
The code length configuration control unit Config Ctrl adopts a half-way scheduling mode, that is, the initial information is calculated from both sides of the factor graph to the center of the factor graph at the same time, and is calculated to both sides after reaching the center, so that the decoding time can be saved by the scheduling mode.
The decoder specifically performs short codeword decoding by the following method: short code word N CW ＝2 -k N, wherein: k is the scaling factor, N is the code length of the reason subgraph, k belongs to [1, N-1 ]]Only N are required for each codeword in CW 2 PE, so that simultaneously K is equal to
Decoding individual code words, using initial information of different code words
And
is shown, in which: i is an e [1, K ]]，j∈[1，N CW ]The initial information arrangement on both sides of the factor graph with the code length N is as follows:
R′ (0) ＝{R (1，2) ，R (3，4) ，...，R (K-1，K) }, wherein: r (a，a+1) ＝{r 1，a ，r 1，a+1 ，r 2，a r 2，a+1 ，...，r K，a ，r K，a+1 I.e. a partially folded decoder of a 1024 code length structure can process 8 short code words of code length 512 at the same time, as shown in the left half of the timing diagram of fig. 2.
With N being 8, N CW For example, K is 2, and in this case, as shown in fig. 6, a code word with a code length N in the factor graph requires N-log 2(N) columns of PEs, so that for a short code word, the dashed line in the graph indicates an extra PE that is not used.
The decoder specifically performs long codeword decoding by the following method: long code word N CW ＝2 k N, k ∈ N, wherein: k is the scaling factor and N is the code length of the causal subgraph. Since the number of available PEs is N/2, the code length is N CW Factor graph of (d) is expanded to log 2 N CW Each stage (column) is divided into several blocks, so that each complete block is factor graph with code length N, and log is calculated in two independent left and right information processing unit arrays 2 And N stages, and then carrying out information interaction between the arrays. At this time, the partial folding decoder with 1024 code length structure can process 2 long code words with 2048 code length simultaneously, as shown in the right half of the timing diagram of fig. 2.
With N being 8, N CW For example, 16, the factor graph is shown in fig. 7, and the long code word N CW The total number of the stages is 4, and the factor graph for decoding only has 3 stages, so that the division is needed to be carried out, and the division is carried out into a complete 3-stage block and a residual block with only one stage. And (3) respectively calculating factor graphs of respective colors of the left and right information processing unit arrays corresponding to the two columns, after 3-stage calculation is completed, mutually calculating information (shown by a dotted line frame) of the two arrays, and then respectively calculating one stage to finish. If there are longer codewords, then multiple exchanges of information between the two arrays are required.
Taking the coding of a polarization code with a code length of 8 as an example,as shown in fig. 3, wherein: the plus sign is binary addition (exclusive or), and the equal sign is straight-through. The bit matrixes before and after the polar code coding are respectively u and x, a linear relation exists between the two matrixes, and the linear algebra is expressed as follows:
wherein:
the notation is kronecker product (tensor product):
wherein: a. the ij Is a matrix A m×n Of (1). Therefore, it is
To make F log 2 Kronecker product N times, if code length N is 8, then:
a comparison of fig. 3 shows complete agreement.
As shown in fig. 3, the decoding structure and the encoding structure corresponding to the above-mentioned polar code BP have processing units PE, but the nodes connected before and after the PE are different, and the decoding structure adjusts the connection in order to take into account the hardware resource multiplexing. As shown in fig. 4, the node indexes connected before and after the three columns of PEs are the same. In the encoding step, the bit u to be encoded is on the left side of the factor graph in fig. 3, and the bit is calculated from left to right to the right side of the factor graph to obtain the bit x after encoding. After the channel is transmitted to a receiving end, soft information (log-likelihood ratio LLR) corresponding to the bit is on the right side of the factor graph in FIG. 4, and the soft information is repeatedly iterated by a method of taking the number of iterations from right to left and then from left to right through a plurality of calculation formulas. After a specified number of iterations (T), the soft information will propagate to the left on the factor graph
And hard decision is carried out by using a threshold, and soft information is decided into hard bits, so that the decoding process is completed. In the factor graph of fig. 4, there are multiple same PEs, and as shown in fig. 5, the information inside the PEs is calculated by the following method during decoding:
wherein: g (a, b) ═ sign (a) sign (b) min (| a |, | b |), L is information propagating from right to left, R is information propagating from left to right, the subscript is the node index in fig. 6, and the superscript is the current iteration number.
Through specific practical experiments, the partial folding polarization code decoder with the code length of 1024 can process five types of code lengths of 256, 512, 1024, 2048 and 4096 in a central core international 55 nanometer process library. The maximum throughput rate of the decoder is 19.29 Gbps. The indexes from top to bottom in the picture are: the decoding method comprises the following steps of manufacturing procedure, chip area, clock frequency, power consumption, code length, average iteration times, the number of users capable of decoding simultaneously (namely the number of the users capable of decoding simultaneously), throughput rate, area efficiency (the ratio of the throughput rate to the chip area), and energy consumption per bit. As shown in the following table:
in this embodiment, the device is started with a code length of 1024 parameters, and the obtained experimental data is: under the 55 nanometer process, the chip area is 5.63 square millimeters, the clock frequency reaches 650MHz, and the power consumption is 494.5 mW. The average decoding of the code word with the code length of 1024 needs 7.91 iterations, 4 users can be decoded at the same time, and the throughput rate can reach 15.48 Gbps. The area efficiency is 2.75Gbps per square millimeter and the energy consumption per bit is 31.95 picojoules per bit.
In summary, the present invention uses two left information processing unit arrays and two right information processing unit arrays; the flow design is adopted in the information processing unit array, so that higher frequency and more users can be supported to decode simultaneously; the factor graph is divided differently to achieve the functions of decoding long codes and short codes; the first selector, the second selector and the information exchange storage unit are controlled by shifting prestored bit information of the shift register. Compared with the prior conventional technical means, the method has the following technical details which are obviously improved: the decoding of the short code can be realized by arranging the left initial information and the initial information in the reason subgraph; the long code factor is divided into several N factor graphs, and the interaction between several small factor graphs can realize the decoding of long code.
The foregoing embodiments may be modified in many different ways by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (8)
1. A partially folded polar code decoder with a configurable code length, comprising: two left information processing unit arrays, two right information processing unit arrays, an information exchange storage unit and a code length configuration control unit, wherein: the information exchange storage unit stores the intermediate information calculated by the information processing unit arrays for next iteration, and the code length configuration control unit configures the four information processing unit arrays according to different code lengths and adopts different shift registers to improve the clock frequency;
in the replacement cache and the two selectors, the first selector selects the initial information and the output of the information processing unit array and the replacement cache from the same direction, the second selector selects the information exchange storage unit and the output of the information processing unit array and the replacement cache from the opposite direction, and the replacement cache is used for receiving the receiving result from each information processing unit array and outputting the left information or the right information which finishes the information index arrangement to the first selector.
2. The decoder of claim 1, wherein the information processing unit array to which the permutation buffer belongs receives left information or right information from the first selector and the second selector, respectively, and the result of the calculation is obtained by BP decoding:
wherein: g (a, b) ═ sign (a) sign (b) min (| a |, | b |), L is information propagating from right to left, R is information propagating from left to right, subscripts i, j are information indexes, respectively, and superscript t is the current iteration number.
3. The decoder of claim 1, wherein a register is added after the input end of the information processing unit array and the internal adder, and a two-stage pipeline design architecture is adopted to increase the clock frequency.
4. The decoder of claim 1, wherein the shift register has control information for the first selector, the second selector and the information exchange memory unit stored therein under different code lengths, the control information is directly outputted to the first selector and the second selector for control, or is used as a gate control signal for controlling the self-increment operation of the address register, and the register signal is outputted to the information exchange memory unit.
5. The decoder of claim 1, wherein a pair of selectors are provided at both sides of the shift register, and when the bit output from the shift register at any time is 0, the output selector selects the upper path, i.e. the address at the next time remains unchanged; otherwise the selector selects the following path, i.e. the address at the next instant is self-added or self-subtracted on the basis of that instant.
6. The decoder of claim 4, wherein a pair of selectors are disposed at two sides of the shift register, and when the bit output from the shift register at any time is 0, the output selector selects the upper path, i.e. the address at the next time remains unchanged; otherwise the selector selects the following path, i.e. the address at the next instant is self-added or self-subtracted on the basis of that instant.
7. A short code word decoding method of a partially folded polarization code decoder according to any one of claims 1 to 6, wherein the initial information arrangement on both sides of the factor graph with the code length N is:
R′ (0) ＝{R (1,2) ,R (3,4) ,…,R (K-1,K) }, wherein: r (a,a+1) ＝{r 1,a ,r 1,a+1 ,r 2,a ,r 2,a+1 ,…,r K ,a,r K,a+1 That is, a part-folding decoder with a 1024 code length structure can simultaneously process 8 short code words with the code length of 512.
8. A method for decoding a long code word by the partially folded polarization code decoder according to any of claims 1 to 6, wherein the code length is N CW Factor graph of (d) is expanded to log 2 N CW Each stage (column) is divided into several blocks, so that each complete block is a factor graph with code length N, and log is calculated in two independent arrays 2 And N stages, and then carrying out information interaction between the arrays, wherein at the moment, the part folding decoder with the 1024 code length structure can simultaneously process 2 long code words with the code length of 2048.
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