CN101854177B - LDPC decoder with high throughput rate - Google Patents
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Abstract
The invention discloses a high-throughput rate low-density parity check code decoder, which comprises an input cache, a check node operation unit, a variable node operation unit, an output cache, a control logic unit and an interconnection network, wherein: the decoder adopts a partial parallel decoding structure, and uses x variable node operation units and y check node operation units, wherein x and y are the column number and the row number of a basic matrix of H, 1 input cache and 1 output cache respectively; each variable node operation unit is composed of a channel information accessor and an external information memory, and each check node operation unit is composed of 1 operation unit for calculating an input minimum value and an input next minimum value. The invention realizes the simultaneous input and output of the decoding without increasing the hardware consumption, thereby greatly improving the throughput rate of the decoder. The decoder may be adapted for regular/irregular LDPC codes; especially for code words with longer code length, the improvement effect of the throughput rate is more obvious.
Description
Technical field
The present invention relates to high-speed wireless digital communication, technical field of optical fiber communication, be specifically related to a kind of low density parity check code (LDPC) decoder of high-throughput.
Background technology
Data always can be introduced various noises, for example synchronization loss in random noise, the demodulating process, and the multipath effect in the wireless transmission etc. in the process of transmission and storage.Because the existence of these noises has limited message transmission rate and transmission quality under certain bandwidth greatly.
Along with the continuous progress of modern communication technology, communication system gradually, capacity higher to throughput reaches more greatly the higher future development of reliability, and error control coding also thereby be widely used.Low density parity check code (LDPC) is a very important class code in the error control code, added glug (RobertGallager) at [R.G.Gallager in 1963 by the Robert, Low-DensityParity-Check Codes.Cambridge, MA:MIT Press, 1963.] propose.Empirical tests, the LDPC code can reach the error performance apart from shannon limit 0.0045dB, and simultaneously ldpc decoder is because check matrix structural, and has intrinsic decoding concurrency, can satisfy the requirement of high speed high-throughput.Thereby at aspects such as expansion new generation of wireless communication system service range, raising video broadcast system throughputs, the LDPC code table has revealed excellent performance and application prospect.
Ldpc decoder is the structure according to check matrix H, finishes decoding by iterative decoding algorithm.Because the H matrix is usually huge and sparse, thereby the structure of LDPC decoding is usually complicated, and hardware consumption is larger.And the decoding delay of iterative algorithm is also larger, so improve the emphasis that the throughput of LDPC decoding always is research.
For improving throughput, [Part 16:Air Interface for Fixed and MobileBroadbandWireless AccessSystems Amendment for Physical and MediumAccess Control Layers for Combined Fixed and Mobile Operation in LicensedBands, IEEE P802.16e-2005,2005] once used full parallel organization to make throughput reach 1Gb/s, but the hardware consumption of this method is very big; The relative complex that connects up simultaneously often can cause the problem of routing congestion for the larger code word of code length.
And famous hierarchical algorithm (is also referred to as the TDMP algorithm, with reference to M.M.Mansour and N.R.Shanbhag, " High-throughput LDPC decoders; " IEEE Trans.Very Large ScaleIntegr. (VLSI) Syst., vol.11, no.6, pp.976-996, Dec.2003.), although the fine use that reduces memory, total iterations also reduces to some extent, but a traditional iteration is divided into the little iteration of several times, thereby decoding delay is multiplied with the increase of the number of times of the little iteration of cutting apart, simultaneously since in its decode procedure be spreading factor with basis matrix as degree of parallelism, thereby the raising of the throughput of decoding is to increase hardware spending as cost.
Summary of the invention
The technical problem that (one) will solve
In view of this, main purpose of the present invention is to provide a kind of ldpc decoder, to realize improving the throughput of ldpc decoder on the basis that increases hardly any hardware spending.
(2) technical scheme
For achieving the above object, the invention provides a kind of low-density parity code transcoder, this decoder comprises input-buffer, check-node arithmetic element, variable node arithmetic element, output buffer memory, control logic unit and internet, wherein: this decoder adopts the part parallel decoding architecture, use x variable node arithmetic element, a y check-node arithmetic element, x and y are respectively columns and the line number of the basis matrix of H, 1 input-buffer, 1 output buffer memory; Each variable node arithmetic element is made of channel information memory access and external information memory, and each check-node arithmetic element is made of 1 arithmetic element of calculating input minimum value and input sub-minimum.
In the such scheme, described check-node arithmetic element adopts minimum-sum algorithm, consisted of by 1 arithmetic element of calculating input minimum value and input sub-minimum, each computing has the parallel input of a plurality of inputs, the check-node arithmetic element will calculate each input in the situation that do not comprise the minimum input of itself, and by the internet check information be passed to described variable node arithmetic element.
In the such scheme, described variable node arithmetic element is made of 1 channel information memory and 1 external information memory, channel information by described input-buffer output is not directly to enter described channel information memory access, but enters described external information memory as the initial value of external information; When iteration begins, described external information memory by the internet to described check-node arithmetic element transmission of information, and simultaneously channel information is deposited in the described channel information memory access, receive again afterwards the information of the described check-node arithmetic element of process verification by the internet, and by certain computing renewal external information, thereby finish iterative decoding one time.
In the such scheme, described input-buffer and described output buffer memory are used for finishing serial and parallel mutual conversion, consist of by several registers.
In the such scheme, described control logic unit is used for realizing whole decoder s operation control, realizes by state machine, and its decode procedure specifically comprises:
Step 1, beginning enter code word;
Step 2, after code word input is finished, enter the iterative decoding link;
Step 3, check-node arithmetic element and variable node arithmetic element replace computing;
Step 4, the decode results that when decoding finishes, begins to export;
Step 5, after decoding output is finished, the new code word of input was carried out the decoding of a new round when whole low-density parity code transcoder entered idle condition.
In the such scheme, the channel information of described input-buffer input not only is stored in the described channel information memory access, and the while also is stored in the described external information memory as the initial value of external information; And be stored in the described channel information memory access through the hard decision information that iterative decoding is exported each bit by described output buffer memory, when finally finishing decoding, will be by described channel information memory access by described output buffer memory output decode results.
In the such scheme, beginning when output decoding when previous code word, but next word input channel information to be decoded it only is stored in the external information memory, in the time of decoding output, can read in a new group code word; Because the information bit code length of decoding output is necessarily short than total code length, so when new code word end of input, old code word has necessarily been finished output, thereby can carry out the iterative decoding of a new round.
In the such scheme, the decode procedure of this decoder specifically comprises:
Step 1: beginning enter code word;
Step 2: after the code word input is finished, enter the iterative decoding link;
Step 3: check-node arithmetic element and variable node arithmetic element replace computing;
Step 4: when decoding finishes, begin to export decode results;
Step 5: when output is carried out, if new enter code word is arranged, then will carry out simultaneously input and output;
Step 6: when input was finished, already end of old code word output then entered the check-node arithmetic element and the variable node arithmetic element replaces computing;
Step 7: when output is carried out, if do not have new enter code word until end of output then returns idle condition.
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1, the present invention proposes this high-throughput ldpc decoder, the ldpc decoder that improves in the past can only be after a codeword decoding output be finished, just can carry out the sequential restriction of next code word input, when adding hardly any hardware complexity, finish the time-multiplexed of decoding input and output, make whole decode procedure will decipher output time fully and " hide ", thereby improved greatly the throughput of decoder.
2, this ldpc decoder structure of the present invention's proposition, when being applied in the certain system of throughput, traditional decoder can by methods such as increase maximum iteration time, obtain better error performance.
3, ldpc decoder provided by the invention on the basis that does not increase hardware consumption, carries out when realizing the decoding input and output, thereby has greatly improved the throughput of decoder.This decoder goes for rule/irregular LDPC codes; Especially long to code length code word, the raising effect of throughput is more obvious.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples:
Fig. 1 is the structural representation of the high-throughput ldpc decoder that provides according to the embodiment of the invention;
Fig. 2 is the structural representation of the variable node arithmetic element VNU in the high-throughput ldpc decoder that provides according to the embodiment of the invention;
Fig. 3 is the schematic diagram of the state of a control conversion of input and output traditional ldpc decoder that can not carry out simultaneously;
Fig. 4 is the state of a control transition diagram of high-throughput ldpc decoder provided by the invention, can realize the concurrency of input and output;
Fig. 5 is the sequential chart of input, iterative decoding and the output of input and output traditional ldpc decoder that can not carry out simultaneously;
Fig. 6 is the sequential chart of input, iterative decoding and the output of high-throughput ldpc decoder provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The ldpc decoder that (9216,4608) rule is provided according to embodiments of the invention shown in Figure 1, wherein the row of check matrix heavily is 6, column weight is 3.This decoder is made of input-buffer, check-node arithmetic element (CNU), variable node arithmetic element (VNU), output buffer memory, control logic and internet.The present embodiment adopts the part parallel decoding architecture, uses altogether 36 VNU, 18 CNU, 1 output buffer memory, 1 output buffer memory.Each VNU is made of channel information memory access (in_mem) and external information memory (ex_mem); Each CNU is made of 1 arithmetic element of calculating input minimum value and input sub-minimum.
Shown in Figure 2 is the basic structure of the variable node arithmetic element (VNU) of the present embodiment, is made of channel information memory and external information memory.For satisfying the needs of high-throughput, realize that decoding input decoding output carries out simultaneously, the interative computation in decode procedure finishes, will be by in_mem to output buffer memory output decode results; And if this is when inputting simultaneously the channel information of a new word to be decoded, this input channel information is not directly to enter in_mem, but enters ex_mem as the initial value of external information.When iteration began, ex_mem will be by the internet to the CNU transmission of information, and deposits channel information in in_mem simultaneously, has also stored so necessary channel information among the in_mem.After ex_mem finishes the renewal computing of a check-node, just can carry out the renewal computing of variable node by the channel information in in_mem, thereby finish iterative decoding one time.
The state transition diagram of the ldpc decoder that not use decoding input and output shown in Figure 3 are carried out simultaneously, the decode procedure of its decoder is as follows:
Step 1, beginning enter code word;
Step 2, after code word input is finished, enter the iterative decoding link;
Step 3, check-node arithmetic element and variable node arithmetic element replace computing;
Step 4, the decode results that when decoding finishes, begins to export;
Step 5, after decoding output is finished, the new code word of input was carried out the decoding of a new round when whole low-density parity code transcoder entered idle condition.
For reaching the requirement that improves data throughput, carry out when realizing the decoding input with output, the present embodiment improves Fig. 3, the state transition diagram that the control unit of the present embodiment adopts when circuit is realized as shown in Figure 4, as can be seen from the figure, the decode procedure of the ldpc decoder of the present embodiment:
Step 1: beginning enter code word;
Step 2: after the code word input is finished, enter the iterative decoding link;
Step 3: check-node arithmetic element and variable node arithmetic element replace computing;
Step 4: when decoding finishes, begin to export decode results;
Step 5: when output is carried out, if new enter code word is arranged, then will carry out simultaneously input and output;
Step 6: when input was finished, already end of old code word output then entered the check-node arithmetic element and the variable node arithmetic element replaces computing;
Step 7: when output is carried out, if do not have new enter code word until end of output then returns idle condition.
Fig. 5 and Fig. 6 represent respectively be input and output traditional ldpc decoder that can not carry out simultaneously input, iterative decoding and output sequential chart and according to the sequential chart of input, iterative decoding and the output of embodiments of the invention ldpc decoder.Wherein because the present embodiment adopts (9126,4608) 1/2 code check, all output times are half of input time, thereby in Fig. 6, the decoding input and output are carried out simultaneously, when new code word end of input, the output of a upper code word finishes already, can carry out the iterative decoding computing of new code word.
Fig. 5 and Fig. 6 are compared as can be known, and the present embodiment can greatly reduce decoding time, only has the output of last code word to take decoding time, and the decoding of other code word output is hidden fully.So that within the regular hour, mode more shown in Figure 5 can be finished the decoding of more code words, thereby improved greatly the throughput of decoder.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a low-density parity code transcoder is characterized in that, this decoder comprises input-buffer, check-node arithmetic element, variable node arithmetic element, output buffer memory, control logic unit and internet, wherein:
This decoder adopts the part parallel decoding architecture, uses x variable node arithmetic element, a y check-node arithmetic element, and x and y are respectively columns and the line number of the basis matrix of H, 1 input-buffer, 1 output buffer memory; Each variable node arithmetic element is made of channel information memory access and external information memory, and each check-node arithmetic element is made of 1 arithmetic element of calculating input minimum value and input sub-minimum;
Described variable node arithmetic element is made of 1 channel information memory and 1 external information memory, channel information by described input-buffer output is not directly to enter described channel information memory access, but enters described external information memory as the initial value of external information; When iteration begins, described external information memory by the internet to described check-node arithmetic element transmission of information, and simultaneously channel information is deposited in the described channel information memory access, receive again afterwards the information of the described check-node arithmetic element of process verification by the internet, and by certain computing renewal external information, thereby finish iterative decoding one time.
2. low-density parity code transcoder according to claim 1, it is characterized in that, described check-node arithmetic element adopts minimum-sum algorithm, consisted of by 1 arithmetic element of calculating input minimum value and input sub-minimum, each computing has the parallel input of a plurality of inputs, the check-node arithmetic element will calculate each input in the situation that do not comprise the minimum input of itself, and by the internet check information be passed to described variable node arithmetic element.
3. low-density parity code transcoder according to claim 1 is characterized in that, described input-buffer and described output buffer memory are used for finishing serial and parallel mutual conversion, consist of by several registers.
4. low-density parity code transcoder according to claim 1 is characterized in that, described control logic unit is used for realizing whole decoder s operation control, realizes by state machine, and its decode procedure specifically comprises:
Step 1, beginning enter code word;
Step 2, after code word input is finished, enter the iterative decoding link;
Step 3, check-node arithmetic element and variable node arithmetic element replace computing;
Step 4, the decode results that when decoding finishes, begins to export;
Step 5, after decoding output is finished, the new code word of input was carried out the decoding of a new round when whole low-density parity code transcoder entered idle condition.
5. low-density parity code transcoder according to claim 1, it is characterized in that, the channel information of described input-buffer input not only is stored in the described channel information memory access, and the while also is stored in the described external information memory as the initial value of external information; And be stored in the described channel information memory access through the hard decision information that iterative decoding is exported each bit by described output buffer memory, when finally finishing decoding, will be by described channel information memory access by described output buffer memory output decode results.
6. low-density parity code transcoder according to claim 1, it is characterized in that, when beginning decoding output when previous code word, but next word input channel information to be decoded, it only is stored in the external information memory, in the time of decoding output, can reads in a new group code word; Because the information bit code length of decoding output is necessarily short than total code length, so when new code word end of input, old code word has necessarily been finished output, thereby can carry out the iterative decoding of a new round.
7. low-density parity code transcoder according to claim 1 is characterized in that, the decode procedure of this decoder specifically comprises:
Step 1: beginning enter code word;
Step 2: after the code word input is finished, enter the iterative decoding link;
Step 3: check-node arithmetic element and variable node arithmetic element replace computing;
Step 4: when decoding finishes, begin to export decode results;
Step 5: when output is carried out, if new enter code word is arranged, then will carry out simultaneously input and output;
Step 6: when input was finished, already end of old code word output then entered the check-node arithmetic element and the variable node arithmetic element replaces computing;
Step 7: when output is carried out, if do not have new enter code word until end of output then returns idle condition.
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| CN106911336B (en) * | 2017-01-17 | 2020-07-07 | 清华大学 | High-speed parallel low-density parity check decoder with multi-core scheduling and decoding method thereof |
| CN107124187B (en) * | 2017-05-05 | 2020-08-11 | 南京大学 | LDPC code decoder based on equal-difference check matrix and applied to flash memory |
| CN108462496B (en) * | 2018-04-24 | 2021-04-02 | 成都吉纬科技有限公司 | LDPC decoder based on random bit stream updating |
| CN111211790B (en) * | 2020-02-25 | 2023-09-29 | 重庆邮电大学 | High throughput LDPC decoding algorithm and architecture for 5G terminal |
| CN112134570A (en) * | 2020-08-16 | 2020-12-25 | 复旦大学 | Multi-mode LDPC decoder applied to deep space communication |
| CN112187286A (en) * | 2020-09-24 | 2021-01-05 | 复旦大学 | Multi-mode LDPC decoder applied to CCSDS satellite deep space communication |
| CN112636767B (en) * | 2020-12-03 | 2023-04-07 | 重庆邮电大学 | Layered semi-parallel LDPC decoder system with single replacement network |
| CN113055028B (en) * | 2021-03-18 | 2022-05-17 | 北京得瑞领新科技有限公司 | LDPC decoding method, decoder, decoding device and storage medium |
| CN113612581B (en) * | 2021-08-03 | 2022-03-11 | 浙江极传信息技术有限公司 | Universal LDPC decoding method and system with high throughput rate |
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