CN111564436B - Fan-out type packaging structure and packaging method - Google Patents
Fan-out type packaging structure and packaging method Download PDFInfo
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- CN111564436B CN111564436B CN202010451986.XA CN202010451986A CN111564436B CN 111564436 B CN111564436 B CN 111564436B CN 202010451986 A CN202010451986 A CN 202010451986A CN 111564436 B CN111564436 B CN 111564436B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/031—Manufacture and pre-treatment of the bonding area preform
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
The invention provides a fan-out type packaging structure and a packaging method, and belongs to the technical field of chip packaging. The fan-out type packaging structure comprises a plate-shaped substrate, wherein a containing groove is formed in one side plate surface of the plate-shaped substrate, a first redistribution layer and a second redistribution layer are formed in the two side plate surfaces of the plate-shaped substrate respectively, the first redistribution layer is connected with the second redistribution layer through a conductive column, the conductive column penetrates through the plate-shaped substrate, a first chip is arranged in the containing groove, a circuit pad of the first chip is located on one side, away from the bottom of the containing groove, of the circuit pad and is connected with the first redistribution layer, a first shielding body is arranged in the containing groove, the first shielding body covers the periphery of the first chip, the side, away from the plate-shaped substrate, of the second redistribution layer is connected with a second chip, a second shielding body is formed on the second redistribution layer, and the second shielding body covers the periphery of the second chip. The packaging structure can shield electromagnetic interference between the chips so as to avoid bad generation caused by mutual interference between the chips and improve the product performance of the packaging structure.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a fan-out type packaging structure and a packaging method.
Background
With the rapid development of the semiconductor industry, a Fan-out wafer level package (FOWLP) structure is widely used in the semiconductor industry.
When a plurality of chips are packaged, the chips with different functions are generally subjected to double-sided packaging so as to realize high-density integration, reduce the size of a packaged product, improve the performance of the product, accelerate the frequency of signal transmission and the like.
However, in the use process of the existing fan-out type double-sided packaging structure, electromagnetic interference generated among chips in the fan-out type double-sided packaging structure cannot be shielded, so that the chips are easy to interfere with each other to generate poor performance, and the performance of the packaged product is reduced.
Disclosure of Invention
The invention aims to provide a fan-out type packaging structure and a packaging method, which can shield electromagnetic interference among chips so as to avoid the generation of defects caused by mutual interference among the chips and improve the product performance of the packaging structure.
The embodiment of the invention is realized by the following steps:
in one aspect of the embodiments of the present invention, a fan-out package structure is provided, including: the plate-shaped substrate is provided with a containing groove on one side plate surface, a first rewiring layer and a second rewiring layer are respectively formed on the two side plate surfaces of the plate-shaped substrate, the first rewiring layer is connected with the second rewiring layer through a conductive column, the conductive column penetrates through the plate-shaped substrate, a first chip is contained in the containing groove, a circuit pad of the first chip is located on one side away from the bottom of the containing groove and is connected with the first rewiring layer, a first shielding body is arranged in the containing groove, the first shielding body is arranged on the periphery of the first chip in a covering mode, a second chip is connected to one side, away from the plate-shaped substrate, of the second rewiring layer, a second shielding body is formed on the second rewiring layer, and the second shielding body is arranged on the periphery of the second chip in a covering mode.
Optionally, the first shielding body is a shielding layer formed on an inner wall of the receiving groove.
Optionally, the second shielding body is a plurality of wire bonds formed on the second redistribution layer, and two ends of each wire bond are respectively located at two opposite ends of the second chip.
Optionally, the first shield and the second shield are conducted through a connection column, and the connection column is embedded in the plate-shaped substrate.
Optionally, the fan-out package structure further includes a ground terminal, and the first shield is connected to the ground terminal.
Optionally, the ground terminal is a ground pad formed on the first redistribution layer, and the ground pad is connected to the first shield.
Optionally, the shielding layer is a metal layer.
Optionally, the accommodating groove is filled with heat dissipation glue, and the heat dissipation glue covers the first chip.
Optionally, the fan-out package structure further includes dielectric layers respectively formed on two board surfaces of the board-shaped substrate, and the first redistribution layer and the second redistribution layer are respectively embedded in the corresponding dielectric layers.
In another aspect of the embodiments of the present invention, a fan-out packaging method is provided, where the method includes:
forming a containing groove on one side plate surface of the plate-shaped substrate;
forming conductive columns penetrating through the plate surfaces on the two sides of the plate-shaped base material;
forming a shielding layer on the inner wall of the accommodating groove;
arranging a first chip in the accommodating groove, wherein a circuit bonding pad of the first chip is positioned on one side far away from the bottom of the accommodating groove;
forming a first redistribution layer on one side plate surface of the plate-shaped substrate, which is provided with the accommodating groove, so that the first redistribution layer is connected with the circuit bonding pad of the first chip and the conductive column;
forming a second redistribution layer on the plate surface of the plate-shaped substrate opposite to the first redistribution layer so as to connect the second redistribution layer with the conductive column;
mounting a second chip on one side of the second rewiring layer away from the plate-shaped base material;
and forming a second shielding body on the second rewiring layer, so that the second shielding body covers the periphery of the second chip.
The embodiment of the invention has the beneficial effects that:
the fan-out type packaging structure provided by the embodiment of the invention comprises a plate-shaped substrate, wherein a containing groove is formed on one side plate surface of the plate-shaped substrate. A first redistribution layer and a second redistribution layer are respectively formed on two side plate surfaces of the plate-shaped base material, and the first redistribution layer and the second redistribution layer are connected through a conductive column, wherein the conductive column penetrates through the plate-shaped base material to be arranged. The first chip is arranged in the accommodating groove, the circuit bonding pad of the first chip is positioned on one side far away from the bottom of the accommodating groove and is connected with the first redistribution layer, a first shielding body is arranged in the accommodating groove, and the first shielding body covers the periphery of the first chip. And one side of the second rewiring layer, which is far away from the plate-shaped base material, is connected with a second chip, a second shielding body is formed on the second rewiring layer, and the second shielding body covers the periphery of the second chip. Through the packaging structure, heat generated by the first chip and the second chip in the working process can be conducted to the outside by utilizing the plate-shaped base material, so that the heat dissipation effect of the first chip and the second chip is improved, and the probability of poor performance of the first chip and the second chip caused by overheating is reduced. In addition, in the packaging structure, the first chip is arranged in the accommodating groove formed by the plate-shaped base material, so that the first chip can be electromagnetically shielded by the first shielding body arranged in the accommodating groove. Therefore, the first chip can be prevented from generating electromagnetic interference on the second chip, the second shielding body is further formed on the second rewiring layer, the electromagnetic shielding effect can be achieved on the second chip, the second chip is prevented from generating electromagnetic interference on the first chip, namely, the packaging structure can avoid the electromagnetic interference between the chips, the external environment can be prevented from generating electromagnetic interference on the chips, and the product performance of the packaging structure can be improved.
The fan-out package method provided by the embodiment of the invention can be used for firstly forming the accommodating groove on one side plate surface of the plate-shaped substrate and forming the conductive column penetrating through the two side plate surfaces of the plate-shaped substrate. Then, a shielding layer is formed on the inner wall of the accommodating groove, and the first chip is arranged in the accommodating groove, so that the circuit bonding pad of the first chip is positioned on one side far away from the bottom of the accommodating groove. And then forming a first rewiring layer on the plate surface of the plate-shaped substrate on which the accommodating groove is formed, so that the first rewiring layer is connected with the circuit pad of the first chip and the conductive column, forming a second rewiring layer on the plate surface of the plate-shaped substrate opposite to the first rewiring layer, so that the second rewiring layer is connected with the conductive column, mounting a second chip on the side, away from the plate-shaped substrate, of the second rewiring layer, and forming a second shielding body on the second rewiring layer, so that the second shielding body covers the periphery of the second chip, thereby forming the fan-out packaging structure. The fan-out type packaging structure is formed by the fan-out type packaging method, so that heat generated by the first chip and the second chip in the working process can be conducted to the outside by utilizing the plate-shaped base material, the heat dissipation effect on the first chip and the second chip is improved, and the probability of poor performance of the first chip and the second chip caused by overheating is reduced. In addition, the first chip is arranged in the accommodating groove formed by the plate-shaped base material, and the shielding layer is formed on the inner wall of the accommodating groove, so that the first chip can be electromagnetically shielded. Therefore, the first chip can be prevented from generating electromagnetic interference on the second chip, the second shielding body is further formed on the second rewiring layer, the electromagnetic shielding effect can be achieved on the second chip, the second chip is prevented from generating electromagnetic interference on the first chip, the electromagnetic interference between the chips can be avoided, the external environment can be prevented from generating electromagnetic interference on the chips, and the product performance of the packaging structure can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a plate-shaped substrate of a fan-out package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a fan-out package structure according to an embodiment of the invention;
fig. 3 is a second schematic structural diagram of a fan-out package structure according to an embodiment of the invention;
fig. 4 is a third schematic structural diagram of a fan-out package structure according to an embodiment of the present invention;
FIG. 5 is a fourth schematic structural diagram of a fan-out package structure according to an embodiment of the present invention;
FIG. 6 is a fifth schematic structural diagram of a fan-out package structure according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a fan-out packaging method according to an embodiment of the present invention.
Icon: 110-a plate-like substrate; 111-a receiving groove; 112-a first shield; 120-a first redistribution layer; 130-a second rewiring layer; 140-a conductive post; 150-a first chip; 160-a second chip; 170-a second shield; 171-routing; 180-connecting column; 181-ground terminal; 190-heat dissipation glue; 200-dielectric layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Furthermore, the terms "horizontal", "vertical" and the like do not imply that the components are required to be absolutely horizontal or pendant, but rather may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
An embodiment of the present invention provides a fan-out package structure, as shown in fig. 2, including: a plate-shaped substrate 110 (as shown in fig. 1) having a receiving cavity 111 formed on one side of the substrate, a first Redistribution layer 120 (RDL) and a second Redistribution layer 130 formed on two sides of the substrate 110, the first Redistribution layer 120 and the second Redistribution layer 130 connected through a conductive pillar 140, the conductive pillar 140 penetrating through the substrate 110, the receiving cavity 111 containing a first chip 150, a circuit pad of the first chip 150 located on a side away from a bottom of the receiving cavity 111 and connected to the first Redistribution layer 120, the receiving cavity 111 containing a first shield 112, the first shield 112 covering an outer periphery of the first chip 150 (as shown in fig. 1 and 2), the second Redistribution layer 130 connected to a side away from the substrate 110, as shown in fig. 3, a second shield 170 is formed on the second redistribution layer 130, and the second shield 170 is disposed at the outer periphery of the second chip 160.
Among them, the plate-like base material 110 may be made of a material having a good dielectric property such as silicon, silica, or a resin polymer. For example, the conductive posts 140 may be made of a conductive material such as metal, graphite, conductive adhesive, and the like.
It should be noted that, in practical applications, the first chip 150 may have a plurality of first chips, and correspondingly, the plate-shaped substrate 110 is provided with corresponding receiving grooves 111 corresponding to the first chips 150, respectively. The first redistribution layers 120 may be disposed corresponding to the first chips 150, or one first redistribution layer 120 may be disposed to be connected to each first chip 150. Since each first chip 150 is shielded by the first shielding body 112 disposed in the corresponding receiving groove 111, each first chip 150 can be shielded from each other, and each first chip 150 and each second chip 160 can be shielded from each other, so that each second chip 160 and each first chip 150 are electromagnetically shielded from each other, thereby preventing the occurrence of defects due to mutual electromagnetic interference, and improving the performance of the package structure.
It should be further noted that, in practical application, those skilled in the art should know that a plastic package body may be further disposed on the fan-out package structure to perform plastic package protection on the second redistribution layer 130 and the second chip 160; and, a pin, a solder ball, or the like for connecting the first redistribution layer 120 with an external device is formed on a side of the first redistribution layer 120 away from the first chip 150.
In general, in the fan-out package structure, the conductive pillars 140 are respectively connected to the fan-out regions of the first redistribution layer 120 and the second redistribution layer 130, so as to avoid the conductive pillars 140 from adversely affecting the second chip 160 and the first chip 150.
The second shielding body 170 may be a shielding adhesive covering the second chip 160, a metal shell covering the second chip 160, or the like, which is not limited herein, as long as the second shielding body 170 can electromagnetically shield the second chip 160, and the first shielding body 112 and the second shielding body 170 may be arranged in the same manner, and of course, other manners may also be adopted without limitation herein.
By forming the second shielding body 170 on the second redistribution layer 130, the second chip 160 can be electromagnetically shielded by the second shielding body 170, so that the second chip 160 is prevented from being subjected to electromagnetic interference, and the effect of electromagnetic shielding between the first chip 150 and the second chip 160 can be enhanced. Moreover, since the first chip 150 and the second chip 160 are electromagnetically shielded correspondingly, the fan-out package structure can also avoid electromagnetic interference caused by an external environment, and has better performance.
It should be noted that, when the second chip 160 is electromagnetically shielded by the second shielding body 170, a plurality of second chips 160 and a plurality of first chips 150 may be disposed, and correspondingly, the second shielding body 170 is disposed corresponding to each second chip 160, so as to avoid mutual interference between the chips and improve performance of the package structure.
The fan-out package structure provided by the embodiment of the invention comprises a plate-shaped substrate 110 with a containing groove 111 formed on one side plate surface. A first redistribution layer 120 and a second redistribution layer 130 are formed on both side plate surfaces of the plate-shaped substrate 110, respectively, and the first redistribution layer 120 and the second redistribution layer 130 are connected by a conductive post 140, wherein the conductive post 140 is provided through the plate-shaped substrate 110. The first chip 150 is accommodated in the accommodating groove 111, and the circuit pad of the first chip 150 is located at a side away from the bottom of the accommodating groove 111 and connected to the first redistribution layer 120, the first shield 112 is disposed in the accommodating groove 111, and the first shield 112 covers the periphery of the first chip 150. The second redistribution layer 130 is connected to the second chip 160 on a side away from the plate-shaped substrate 110, a second shield 170 is formed on the second redistribution layer 130, and the second shield 170 is covered on the outer periphery of the second chip 160. With the package structure, heat generated by the first chip 150 and the second chip 160 during operation can be conducted to the outside by the plate-shaped base material 110, so that the heat dissipation effect of the first chip 150 and the second chip 160 is improved, and the probability of failure caused by overheating of the first chip 150 and the second chip 160 is reduced. In addition, in the package structure, the first chip 150 is disposed in the receiving groove 111 formed in the plate-shaped base material 110, so that the first shielding body 112 disposed in the receiving groove 111 can provide an electromagnetic shielding effect on the first chip 150. Therefore, the first chip 150 can be prevented from generating electromagnetic interference on the second chip 160, and the second shielding body 170 is further formed on the second redistribution layer 130, so that the electromagnetic shielding effect on the second chip 160 can be achieved, and the second chip 160 can be prevented from generating electromagnetic interference on the first chip 150, that is, the packaging structure can avoid the electromagnetic interference between the chips, and can avoid the external environment from generating electromagnetic interference on the chips, so that the product performance of the packaging structure can be improved.
Optionally, as shown in fig. 2 and fig. 1, the first shielding body 112 is a shielding layer formed on an inner wall of the receiving groove.
The shielding layer formed on the inner wall of the receiving groove 111 is usually made of a conductive material to achieve an electromagnetic shielding effect. Illustratively, the shielding layer may be a graphite layer, an indium tin oxide layer, a metal layer, or the like, for example, the shielding layer is a metal layer. The shielding layer is set as a metal layer, so that the cost is relatively low, and the shielding layer is convenient to set on the inner wall of the accommodating groove 111.
Alternatively, as shown in fig. 3, the second shielding body 170 is a plurality of wires 171 formed on the second redistribution layer 130, and two ends of each wire 171 are respectively located at two opposite ends of the second chip 160.
The wire bonds 171 may be arranged in a straight line at a certain interval, and of course, the wire bonds 171 may also be arranged in a staggered manner, which is not limited herein, as long as the second shielding body 170 formed by the wire bonds 171 can cover the second chip 160, so as to achieve the electromagnetic shielding effect on the second chip 160.
By forming a plurality of wires 171 on the second redistribution layer 130 to form the second shield 170, the cost is relatively low and the arrangement is convenient.
Optionally, as shown in fig. 4, the second shield 170 and the first shield 112 are conducted through a connection post 180, and the connection post 180 is embedded in the plate-shaped substrate 110.
The second shield 170 and the first shield 112 are conducted through the connection post 180, so that the electrostatic shielding effect of the first chip 150 and the second chip 160 can be enhanced. The connecting column 180 may be made of conductive materials such as metal, graphite, and conductive adhesive, which are not limited herein.
It should be noted that when the second shielding body 170 is a plurality of wires 171 formed on the second redistribution layer 130, the connection posts 180 may be connected to wire bonding pads on the second redistribution layer 130, for example.
Optionally, as shown in fig. 5, the fan-out package structure further includes a ground terminal 181, and the first shield 112 is connected to the ground terminal 181.
By providing the ground terminal 181 and connecting the first shield 112 to the ground terminal 181, it is possible to prevent the charges accumulated on the first shield 112 from forming a current on the first redistribution layer 120 and/or the second redistribution layer 130 to burn out a chip or a circuit, which may affect the performance of the package structure.
Of course, when the fan-out package structure further includes a second shielding body 170 for electromagnetically shielding the second chip 160, the second shielding body 170 may also be connected to the ground terminal 181 to prevent the accumulated charges from burning out the device. If the first shield 112 and the second shield 170 are connected by the connection post 180, one of the first shield 112 or the second shield 170 may be connected to the ground 181, for example, the first shield 112 is connected to the ground 181.
Alternatively, the ground terminal 181 is a ground pad formed on the first redistribution layer 120, and the ground pad is connected to the first shield 112.
Note that, in order to enable ground communication with an external device or device, a ground pad may be formed on a side of the first redistribution layer 120 facing away from the first chip 150. In practical applications, a ball or a solder pin may be mounted on the ground pad so that the ground pad is in ground connection with an external device.
Optionally, as shown in fig. 6, the accommodating groove 111 is filled with a heat dissipation adhesive 190, and the heat dissipation adhesive 190 covers the first chip 150.
By providing the heat dissipation paste 190, the heat of the first chip 150 can be more quickly and easily conducted to the plate-shaped base material 110, thereby enhancing the heat dissipation effect of the first chip 150.
In practical applications, the plate-shaped substrate 110 may be made of a dielectric material with low thermal resistance. Therefore, the efficiency of outward heat dissipation of the plate-shaped substrate 110 is improved, and the heat dissipation effect of the fan-out package structure is improved.
Optionally, as shown in fig. 6, the fan-out package structure further includes dielectric layers 200 respectively formed on two board surfaces of the board substrate 110, and the first redistribution layer 120 and the second redistribution layer 130 are respectively embedded in the corresponding dielectric layers 200.
By providing the dielectric layer 200, the first rewiring layer 120 and the second rewiring layer 130 can be fixed and protected.
In another aspect of the embodiments of the present invention, a fan-out package method is provided, which can be used to fabricate and generate the fan-out package structure described above, so as to avoid the generation of defects due to mutual interference between chips, and improve the product performance of the package structure.
As shown in fig. 7, the fan-out packaging method may include:
s701: a containing groove is formed on one side plate surface of the plate-shaped base material.
S702: forming conductive posts penetrating through the board surfaces on the two sides of the board-shaped substrate.
S703: and forming a shielding layer on the inner wall of the accommodating groove.
S704: and arranging a first chip in the accommodating groove, wherein a circuit bonding pad of the first chip is positioned on one side far away from the bottom of the accommodating groove.
S705: and forming a first redistribution layer on one side plate surface of the plate-shaped substrate, which is provided with the accommodating groove, so that the first redistribution layer is connected with the circuit bonding pad of the first chip and the conductive column.
S706: and forming a second redistribution layer on the plate surface of the plate-shaped substrate opposite to the first redistribution layer so as to connect the second redistribution layer with the conductive column.
S707: mounting a second chip on one side of the second rewiring layer away from the plate-shaped base material;
s708: and forming a second shielding body on the second rewiring layer, so that the second shielding body covers the periphery of the second chip.
The accommodating groove can be formed through an etching process, and the area of the plate surface outside the accommodating groove can be protected by the protective film in the etching process. The shielding layer is formed on the inner wall of the accommodating groove by adopting processes such as chemical vapor deposition, electroplating and the like. Of course, in the embodiment of the invention, the specific processes for forming the receiving groove and the shielding layer are not limited.
In this method, forming the conductive pillars may be implemented using a TSV (through silicon via) technique. Of course, the method can also be implemented by forming a through hole and then filling a conductive adhesive, and the like, which is not limited herein.
In general, in practical applications, the sequence of the step of forming the conductive pillar and the step of forming the shielding layer may be set according to practical situations, and is not limited herein.
It should be noted that when one side of the plate-shaped substrate is correspondingly processed, the other side of the plate-shaped substrate can be attached to the carrier plate, so as to avoid deformation such as warpage of the plate-shaped substrate during processing. The carrier plate can be made of glass, silicon oxide, metal and the like.
In the embodiment of the invention, after the first chip is arranged in the accommodating groove, the accommodating groove can be filled with the heat dissipation glue, so that the efficiency of conducting the heat of the first chip to the plate-shaped substrate is improved, and the heat dissipation effect is enhanced.
After the first redistribution layer is formed, the first redistribution layer may also be embedded within the dielectric layer for protection and planarization in the form of a filled dielectric layer. Accordingly, after the second rewiring layer is formed, the second rewiring layer may also be embedded in the dielectric layer in the form of a filled dielectric layer for protection and planarization.
The second shielding body may be formed by forming a plurality of wire bonding pads on the second redistribution layer at two opposite ends of the second chip, and performing wire bonding to form wire bonds with two ends located at two opposite ends of the second chip.
Through forming the second shielding body in order to carry out the electromagnetic shield to the second chip, can further avoid mutual interference between first chip and the second chip to, can avoid the interference of external environment to first chip and second chip respectively.
In practical applications, before the step of disposing the first chip in the receiving slot, a connection post may be further formed on the plate-shaped substrate, wherein one end of the connection post is connected to the shielding layer, and the other end of the connection post is used for being connected to the second redistribution layer, so that the second shielding body formed on the second redistribution layer can be connected to the shielding layer through the connection post. The process of forming the connecting stud may be the same as the process of forming the conductive stud, and is not described herein.
The fan-out package method provided by the embodiment of the invention can be used for firstly forming the accommodating groove on one side plate surface of the plate-shaped substrate and forming the conductive column penetrating through the two side plate surfaces of the plate-shaped substrate. Then, a shielding layer is formed on the inner wall of the accommodating groove, and the first chip is arranged in the accommodating groove, so that the circuit bonding pad of the first chip is positioned on one side far away from the bottom of the accommodating groove. And then forming a first rewiring layer on the plate surface of the plate-shaped substrate on which the accommodating groove is formed, so that the first rewiring layer is connected with the circuit pad of the first chip and the conductive column, forming a second rewiring layer on the plate surface of the plate-shaped substrate opposite to the first rewiring layer, so that the second rewiring layer is connected with the conductive column, mounting a second chip on the side, away from the plate-shaped substrate, of the second rewiring layer, and forming a second shielding body on the second rewiring layer, so that the second shielding body covers the periphery of the second chip, thereby forming the fan-out packaging structure. The fan-out type packaging structure is formed by the fan-out type packaging method, so that heat generated by the first chip and the second chip in the working process can be conducted to the outside by utilizing the plate-shaped base material, the heat dissipation effect on the first chip and the second chip is improved, and the probability of poor performance of the first chip and the second chip caused by overheating is reduced. In addition, the first chip is arranged in the accommodating groove formed by the plate-shaped base material, and the shielding layer is formed on the inner wall of the accommodating groove, so that the first chip can be electromagnetically shielded. Therefore, the first chip can be prevented from generating electromagnetic interference on the second chip, the second shielding body is further formed on the second rewiring layer, the electromagnetic shielding effect can be achieved on the second chip, the second chip is prevented from generating electromagnetic interference on the first chip, the electromagnetic interference between the chips can be avoided, the external environment can be prevented from generating electromagnetic interference on the chips, and the product performance of the packaging structure can be improved.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific implementation manners and effects of the structures and the like related to the fan-out package method described above may refer to the corresponding descriptions and explanations in the foregoing fan-out package structure embodiments, and no further description is provided in the present disclosure.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A fan-out package structure, comprising:
a plate-shaped substrate with a containing groove is formed on one side plate surface, a first redistribution layer and a second redistribution layer are respectively formed on the two side plate surfaces of the plate-shaped substrate, the first redistribution layer is connected with the second redistribution layer through a conductive column, the conductive column penetrates through the plate-shaped substrate, a first chip is contained in the containing groove, a circuit pad of the first chip is positioned on one side far away from the bottom of the containing groove and is connected with the first redistribution layer, a first shielding body is arranged in the containing groove, the first shielding body is covered on the periphery of the first chip, a second chip is connected on one side of the second redistribution layer far away from the plate-shaped substrate, a second shielding body is formed on the second redistribution layer, and the second shielding body is covered on the periphery of the second chip;
the first shielding body is a shielding layer formed on the inner wall of the accommodating groove;
the accommodating groove is filled with heat dissipation glue, and the heat dissipation glue covers the first chip;
the first shielding body and the second shielding body are conducted through a connecting column, and the connecting column is embedded in the platy substrate;
the fan-out package structure further comprises a grounding terminal, and the first shielding body is connected with the grounding terminal.
2. The fan-out package structure of claim 1, wherein the second shield is a plurality of wires formed on the second redistribution layer, and two ends of each wire are respectively located at two opposite ends of the second chip.
3. The fan-out package structure of claim 1, wherein the ground terminal is a ground pad formed on the first redistribution layer, the ground pad connected to the first shield.
4. The fan-out package structure of claim 1, wherein the shielding layer is a metal layer.
5. The fan-out package structure of claim 1, further comprising dielectric layers formed on two board surfaces of the board substrate, respectively, wherein the first redistribution layer and the second redistribution layer are embedded in the corresponding dielectric layers, respectively.
6. A fan-out packaging method, comprising:
forming a containing groove on one side plate surface of the plate-shaped substrate;
forming conductive columns penetrating through the plate surfaces on the two sides of the plate-shaped base material;
forming a shielding layer on the inner wall of the accommodating groove;
connecting columns penetrating through the board surfaces on the two sides of the platy substrate are formed, and one ends of the connecting columns are respectively connected with the shielding layer;
arranging a first chip in the accommodating groove, wherein a circuit bonding pad of the first chip is positioned on one side far away from the bottom of the accommodating groove;
forming a first redistribution layer on a side plate surface of the plate-shaped substrate, where the accommodating groove is formed, so that the first redistribution layer is connected with the circuit pad of the first chip and the conductive column;
forming a second redistribution layer on the plate surface of the plate-shaped substrate opposite to the first redistribution layer, so that the second redistribution layer is connected with the conductive column and the connecting column;
mounting a second chip on one side of the second rewiring layer away from the plate-shaped base material;
and forming a second shielding body on the second rewiring layer, so that the second shielding body covers the periphery of the second chip.
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